drm/radeon: fix typo in CP DMA register headers
commit aa3e146d04b6ae37939daeebaec060562b3db559 upstream. Wrong bit offset for SRC endian swapping. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -1104,7 +1104,7 @@
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* 6. COMMAND [29:22] | BYTE_COUNT [20:0]
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*/
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# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
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/* 0 - SRC_ADDR
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/* 0 - DST_ADDR
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* 1 - GDS
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*/
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# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
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@ -1119,7 +1119,7 @@
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# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
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/* COMMAND */
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# define PACKET3_CP_DMA_DIS_WC (1 << 21)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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@ -1259,7 +1259,7 @@
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*/
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# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
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/* COMMAND */
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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@ -928,7 +928,7 @@
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* 6. COMMAND [30:21] | BYTE_COUNT [20:0]
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*/
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# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
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/* 0 - SRC_ADDR
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/* 0 - DST_ADDR
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* 1 - GDS
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*/
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# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
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@ -943,7 +943,7 @@
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# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
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/* COMMAND */
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# define PACKET3_CP_DMA_DIS_WC (1 << 21)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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