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perf, x86: Deal with multiple state bits for pebs-fmt1 

Its unclear if the PEBS state record will have only a single bit set, in
case it does not and accumulates bits, deal with that by only processing
each event once.

Also, robustify some of the code.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Peter Zijlstra 2010-03-06 18:57:38 +01:00 committed by Ingo Molnar
parent d329527e47
commit 12ab854d74
1 changed files with 13 additions and 3 deletions
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16
arch/x86/kernel/cpu/perf_event_intel_ds.c
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@ -538,6 +538,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
struct perf_event *event = NULL;
struct perf_raw_record raw;
struct pt_regs regs;
u64 status = 0;
int bit, n;
if (!ds || !x86_pmu.pebs)
@ -561,13 +562,22 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
for ( ; at < top; at++) {
for_each_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) {
if (!cpuc->events[bit]->attr.precise)
event = cpuc->events[bit];
if (!test_bit(bit, cpuc->active_mask))
continue;
event = cpuc->events[bit];
WARN_ON_ONCE(!event);
if (!event->attr.precise)
continue;
if (__test_and_set_bit(bit, (unsigned long *)&status))
continue;
break;
}
if (!event)
if (!event || bit >= MAX_PEBS_EVENTS)
continue;
if (!intel_pmu_save_and_restart(event))