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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
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msm: cpu: Add l2 and core initialization sequence for msmterbium
L2 and core initialization sequences on msmterbium are different from existing targets, so add the new sequences. Change-Id: I9660d4cc7d6b8c39b2fbdb2d360bb221205aac68 Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org> Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
This commit is contained in:
Srinivas Ramana
parent
007cd467c0
commit
13102a14c6
3 changed files with 264 additions and 2 deletions
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@ -1,4 +1,4 @@
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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* Copyright (c) 2013 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -159,6 +159,25 @@ static int msm_cpu_boot(unsigned int cpu)
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return secondary_pen_release(cpu);
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}
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static int msmterbium_cpu_boot(unsigned int cpu)
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{
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int ret = 0;
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if (per_cpu(cold_boot_done, cpu) == false) {
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if (of_board_is_sim()) {
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ret = msm_unclamp_secondary_arm_cpu_sim(cpu);
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if (ret)
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return ret;
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} else {
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ret = msmterbium_unclamp_secondary_arm_cpu(cpu);
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if (ret)
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return ret;
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}
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per_cpu(cold_boot_done, cpu) = true;
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}
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return secondary_pen_release(cpu);
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}
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static int msm8994_cpu_boot(unsigned int cpu)
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{
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int ret = 0;
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@ -243,3 +262,18 @@ static const struct cpu_operations msm8994_cortex_a_ops = {
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.cpu_suspend = msm_pm_collapse,
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};
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CPU_METHOD_OF_DECLARE(msm8994_cortex_a_ops, &msm8994_cortex_a_ops);
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static const struct cpu_operations msmterbium_cortex_a_ops = {
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.name = "qcom,terbium-arm-cortex-acc",
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.cpu_init = msm_cpu_init,
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.cpu_prepare = msm_cpu_prepare,
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.cpu_boot = msmterbium_cpu_boot,
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.cpu_postboot = msm_cpu_postboot,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = msm_wfi_cpu_die,
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#endif
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#ifdef CONFIG_ARM64_CPU_SUSPEND
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.cpu_suspend = msm_pm_collapse,
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#endif
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};
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CPU_METHOD_OF_DECLARE(msmterbium_cortex_a_ops, &msmterbium_cortex_a_ops);
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@ -29,6 +29,7 @@
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#include <asm/barrier.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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/* CPU power domain register offsets */
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#define CPU_PWR_CTL 0x4
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@ -61,6 +62,77 @@ struct msm_l2ccc_of_info {
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};
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static int power_on_l2_msmterbium(struct device_node *l2ccc_node, u32 pon_mask,
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int cpu)
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{
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u32 pon_status;
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void __iomem *l2_base;
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l2_base = of_iomap(l2ccc_node, 0);
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if (!l2_base)
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return -ENOMEM;
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/* Skip power-on sequence if l2 cache is already powered up */
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pon_status = (__raw_readl(l2_base + L2_PWR_STATUS) & pon_mask)
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== pon_mask;
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if (pon_status) {
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iounmap(l2_base);
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return 0;
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}
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/* Close Few of the head-switches for L2SCU logic */
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writel_relaxed(0x10F700, l2_base + L2_PWR_CTL);
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mb();
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udelay(2);
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/* Close Rest of the head-switches for L2SCU logic */
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writel_relaxed(0x410F700, l2_base + L2_PWR_CTL);
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mb();
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udelay(2);
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/* Assert PRESETDBG */
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writel_relaxed(0x400000, l2_base + L2_PWR_CTL_OVERRIDE);
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mb();
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udelay(2);
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/* De-assert L2/SCU memory Clamp */
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writel_relaxed(0x4103700, l2_base + L2_PWR_CTL);
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/* Assert L2 memory slp_nret_n */
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writel_relaxed(0x4103703, l2_base + L2_PWR_CTL);
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mb();
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udelay(4);
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/* Assert L2 memory slp_ret_n */
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writel_relaxed(0x4101703, l2_base + L2_PWR_CTL);
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mb();
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udelay(4);
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/* Enable clocks via SW_CLK_EN */
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writel_relaxed(0x01, l2_base + L2_CORE_CBCR);
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/* De-assert L2/SCU logic clamp */
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writel_relaxed(0x4101603, l2_base + L2_PWR_CTL);
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mb();
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udelay(2);
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/* De-assert PRESETDBG */
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writel_relaxed(0x0, l2_base + L2_PWR_CTL_OVERRIDE);
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/* De-assert L2/SCU Logic reset */
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writel_relaxed(0x4100203, l2_base + L2_PWR_CTL);
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mb();
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udelay(54);
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/* Turn on the PMIC_APC */
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writel_relaxed(0x14100203, l2_base + L2_PWR_CTL);
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/* Set H/W clock control for the cluster CBC block */
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writel_relaxed(0x03, l2_base + L2_CORE_CBCR);
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mb();
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iounmap(l2_base);
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return 0;
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}
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static int power_on_l2_msm8916(struct device_node *l2ccc_node, u32 pon_mask,
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int cpu)
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{
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@ -265,6 +337,12 @@ static const struct msm_l2ccc_of_info l2ccc_info[] = {
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.l2_power_on = power_on_l2_msm8916,
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.l2_power_on_mask = BIT(9),
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},
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{
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.compat = "qcom,terbium-l2ccc",
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.l2_power_on = power_on_l2_msmterbium,
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.l2_power_on_mask = BIT(9) | BIT(28),
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},
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};
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static int power_on_l2_cache(struct device_node *l2ccc_node, int cpu)
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@ -487,6 +565,151 @@ out_acc:
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return ret;
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}
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static inline void msmterbium_unclamp_perf_cluster_cpu(void __iomem *reg)
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{
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/* Assert head switch enable few */
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writel_relaxed(0x00000001, reg + CPU_PWR_GATE_CTL);
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mb();
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udelay(2);
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/* Assert head switch enable rest */
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writel_relaxed(0x00000003, reg + CPU_PWR_GATE_CTL);
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mb();
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udelay(2);
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/* De-assert coremem clamp */
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writel_relaxed(0x00000079, reg + CPU_PWR_CTL);
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mb();
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udelay(2);
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/* Close coremem array gdhs */
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writel_relaxed(0x0000007D, reg + CPU_PWR_CTL);
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mb();
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udelay(2);
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/* Ungate clock */
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writel_relaxed(0x0000003D, reg + CPU_PWR_CTL);
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mb();
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/* De-assert clamp */
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writel_relaxed(0x0000003C, reg + CPU_PWR_CTL);
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mb();
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udelay(2);
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/* Deassert Core-n reset */
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writel_relaxed(0x0000000C, reg + CPU_PWR_CTL);
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mb();
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/* Assert PWRDUP */
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writel_relaxed(0x0000008C, reg + CPU_PWR_CTL);
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mb();
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}
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static inline void msmterbium_unclamp_power_cluster_cpu(void __iomem *reg)
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{
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/* Deassert CPU in sleep state */
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writel_relaxed(0x00000033, reg + CPU_PWR_CTL);
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mb();
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/* Program skew between en_few and en_rest to 16 XO clk cycles,
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close Core logic head switch*/
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writel_relaxed(0x10000001, reg + CPU_PWR_GATE_CTL);
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mb();
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udelay(2);
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/* De-assert coremem clamp */
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writel_relaxed(0x00000031, reg + CPU_PWR_CTL);
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mb();
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/* Assert Core memory slp_nret_n */
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writel_relaxed(0x00000039, reg + CPU_PWR_CTL);
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mb();
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udelay(2);
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/* Assert Core memory slp_ret_n */
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writel_relaxed(0x00000239, reg + CPU_PWR_CTL);
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mb();
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udelay(2);
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/* Deassert Clamp */
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writel_relaxed(0x00000238, reg + CPU_PWR_CTL);
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mb();
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udelay(2);
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/* Deassert Core0 reset */
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writel_relaxed(0x00000208, reg + CPU_PWR_CTL);
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mb();
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/* Assert PWRDUP; */
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writel_relaxed(0x00000288, reg + CPU_PWR_CTL);
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mb();
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}
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int msmterbium_unclamp_secondary_arm_cpu(unsigned int cpu)
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{
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int ret = 0;
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struct device_node *cpu_node, *acc_node, *l2_node, *l2ccc_node;
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void __iomem *reg;
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u32 mpidr = cpu_logical_map(cpu);
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cpu_node = of_get_cpu_node(cpu, NULL);
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if (!cpu_node)
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return -ENODEV;
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acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
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if (!acc_node) {
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ret = -ENODEV;
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goto out_acc;
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}
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l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
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if (!l2_node) {
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ret = -ENODEV;
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goto out_l2;
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}
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l2ccc_node = of_parse_phandle(l2_node, "power-domain", 0);
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if (!l2ccc_node) {
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ret = -ENODEV;
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goto out_l2ccc;
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}
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/*
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* Ensure L2-cache of the CPU is powered on before
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* unclamping cpu power rails.
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*/
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ret = power_on_l2_cache(l2ccc_node, cpu);
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if (ret) {
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pr_err("L2 cache power up failed for CPU%d\n", cpu);
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goto out_acc_reg;
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}
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reg = of_iomap(acc_node, 0);
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if (!reg) {
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ret = -ENOMEM;
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goto out_acc_reg;
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}
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if (MPIDR_AFFINITY_LEVEL(mpidr, 1))
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msmterbium_unclamp_perf_cluster_cpu(reg);
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else
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msmterbium_unclamp_power_cluster_cpu(reg);
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/* Secondary CPU-N is now alive */
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iounmap(reg);
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out_acc_reg:
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of_node_put(l2ccc_node);
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out_l2ccc:
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of_node_put(l2_node);
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out_l2:
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of_node_put(acc_node);
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out_acc:
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of_node_put(cpu_node);
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return ret;
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}
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int msm_unclamp_secondary_arm_cpu(unsigned int cpu)
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{
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@ -1,4 +1,4 @@
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -17,6 +17,7 @@
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int msm_unclamp_secondary_arm_cpu_sim(unsigned int cpu);
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int msm_unclamp_secondary_arm_cpu(unsigned int cpu);
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int msm8994_unclamp_secondary_arm_cpu(unsigned int cpu);
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int msmterbium_unclamp_secondary_arm_cpu(unsigned int cpu);
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int msm8994_cpu_ldo_config(unsigned int cpu);
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#else
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static inline int msm_unclamp_secondary_arm_cpu_sim(unsigned int cpu)
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@ -31,6 +32,10 @@ static inline int msm8994_unclamp_secondary_arm_cpu(unsigned int cpu)
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{
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return 0;
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}
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static inline int msmterbium_unclamp_secondary_arm_cpu(unsigned int cpu)
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{
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return 0;
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}
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static inline int msm8994_cpu_ldo_config(unsigned int cpu)
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{
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return 0;
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