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Merge "clk: qcom: clock-gcc-8976: Fix QDSS clock type for MSM8976"

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Linux Build Service Account 2015-06-16 08:20:23 -07:00 committed by Gerrit - the friendly Code Review server
parent f34a52522f fdd393b2b9
commit 186318ca45
2 changed files with 6 additions and 5 deletions
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10
drivers/clk/qcom/clock-gcc-8976.c
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@ -55,10 +55,10 @@ DEFINE_CLK_RPM_SMD_BRANCH(xo_clk_src, xo_a_clk_src,
DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL);
DEFINE_CLK_RPM_SMD(ipa_clk, ipa_a_clk, RPM_IPA_CLK_TYPE, IPA_ID, NULL);
DEFINE_CLK_RPM_SMD(pcnoc_clk, pcnoc_a_clk, RPM_BUS_CLK_TYPE, PCNOC_ID, NULL);
DEFINE_CLK_RPM_SMD(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID, NULL);
DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL);
DEFINE_CLK_RPM_SMD(sysmmnoc_clk, sysmmnoc_a_clk, RPM_BUS_CLK_TYPE,
SYSMMNOC_ID, NULL);
DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID);
/* SMD_XO_BUFFER */
DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk1, bb_clk1_a, BB_CLK1_ID);
@ -1047,7 +1047,7 @@ static struct rcg_clk gp3_clk_src = {
static struct clk_freq_tbl ftbl_byte0_clk_src[] = {
{
.div_src_val = BVAL(10, 8, dsi0_phypll_mm_source_val),
},
},
};
static struct rcg_clk byte0_clk_src = {
.cmd_rcgr_reg = BYTE0_CMD_RCGR,
@ -1064,8 +1064,8 @@ static struct rcg_clk byte0_clk_src = {
static struct clk_freq_tbl ftbl_byte1_clk_src[] = {
{
.div_src_val = BVAL(10, 8, dsi0_phypll_mm_source_val),
},
.div_src_val = BVAL(10, 8, dsi1_phypll_mm_source_val),
},
};
static struct rcg_clk byte1_clk_src = {
.cmd_rcgr_reg = BYTE1_CMD_RCGR,
@ -1167,7 +1167,7 @@ static struct rcg_clk pclk0_clk_src = {
static struct clk_freq_tbl ftbl_pclk1_clk_src[] = {
{
.div_src_val = BVAL(10, 8, dsi0_phypll_mm_source_val),
.div_src_val = BVAL(10, 8, dsi1_phypll_mm_source_val),
},
};
static struct rcg_clk pclk1_clk_src = {

1
include/dt-bindings/clock/msm-clocks-hwio-8976.h
View File

@ -314,6 +314,7 @@
#define gpll6_aux_source_val 2
#define dsi0_phypll_mm_source_val 1
#define dsi1_phypll_mm_source_val 1
#define F(f, s, div, m, n) \
{ \