Piteball
/
android_kernel_samsung_msm8976
mirror of https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
1
1
Fork 0
Code Issues Projects Releases Wiki Activity

rapidio/tsi721: modify PCIe capability settings 

Modify initialization of PCIe capability registers in Tsi721 mport driver:
 - change Completion Timeout value to avoid unexpected data transfer
   aborts during intensive traffic.
 - replace hardcoded offset of PCIe capability block by making it use the
   common function.

This patch is applicable to kernel versions starting from 3.2-rc1.

Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
Cc: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Alexandre Bounine 2011-12-08 14:34:42 -08:00 committed by Linus Torvalds
parent b439e66f04
commit 1cee22b7f3
2 changed files with 17 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/rapidio/devices/tsi721.c
View File

@ -2154,7 +2154,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct tsi721_device *priv;
int i;
int i, cap;
int err;
u32 regval;
@ -2262,10 +2262,20 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
}
/* Clear "no snoop" and "relaxed ordering" bits. */
pci_read_config_dword(pdev, 0x40 + PCI_EXP_DEVCTL, &regval);
regval &= ~(PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN);
pci_write_config_dword(pdev, 0x40 + PCI_EXP_DEVCTL, regval);
cap = pci_pcie_cap(pdev);
BUG_ON(cap == 0);
/* Clear "no snoop" and "relaxed ordering" bits, use default MRRS. */
pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, &regval);
regval &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |
PCI_EXP_DEVCTL_NOSNOOP_EN);
regval |= 0x2 << MAX_READ_REQUEST_SZ_SHIFT;
pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL, regval);
/* Adjust PCIe completion timeout. */
pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL2, &regval);
regval &= ~(0x0f);
pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL2, regval | 0x2);
/*
* FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block

2
drivers/rapidio/devices/tsi721.h
View File

@ -72,6 +72,8 @@
#define TSI721_MSIXPBA_OFFSET 0x2a000
#define TSI721_PCIECFG_EPCTL 0x400
#define MAX_READ_REQUEST_SZ_SHIFT 12
/*
* Event Management Registers
*/