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arm64: kvm: use inner-shareable barriers for inner-shareable maintenance
In order to ensure completion of inner-shareable maintenance instructions (cache and TLB) on AArch64, we can use the -ish suffix to the dsb instruction. This patch relaxes our dsb sy instructions to dsb ish where possible. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Git-commit: ee9e101c11478680d579bd20bb38a4d3e2514fe3 Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
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@ -630,9 +630,15 @@ ENTRY(__kvm_tlb_flush_vmid_ipa)
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* whole of Stage-1. Weep...
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*/
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tlbi ipas2e1is, x1
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dsb sy
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/*
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* We have to ensure completion of the invalidation at Stage-2,
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* since a table walk on another CPU could refill a TLB with a
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* complete (S1 + S2) walk based on the old Stage-2 mapping if
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* the Stage-1 invalidation happened first.
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*/
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dsb ish
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tlbi vmalle1is
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dsb sy
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dsb ish
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isb
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msr vttbr_el2, xzr
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@ -643,7 +649,7 @@ ENTRY(__kvm_flush_vm_context)
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dsb ishst
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tlbi alle1is
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ic ialluis
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dsb sy
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dsb ish
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ret
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ENDPROC(__kvm_flush_vm_context)
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