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arm64: kvm: use inner-shareable barriers for inner-shareable maintenance

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In order to ensure completion of inner-shareable maintenance instructions
(cache and TLB) on AArch64, we can use the -ish suffix to the dsb
instruction.

This patch relaxes our dsb sy instructions to dsb ish where possible.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Git-commit: ee9e101c11478680d579bd20bb38a4d3e2514fe3
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
This commit is contained in:
Will Deacon 2014-05-02 16:24:14 +01:00 committed by Joonwoo Park
parent 52d639ef51
commit 209a87d825
1 changed files with 9 additions and 3 deletions
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12
arch/arm64/kvm/hyp.S
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@ -630,9 +630,15 @@ ENTRY(__kvm_tlb_flush_vmid_ipa)
* whole of Stage-1. Weep...
*/
tlbi ipas2e1is, x1
dsb sy
/*
* We have to ensure completion of the invalidation at Stage-2,
* since a table walk on another CPU could refill a TLB with a
* complete (S1 + S2) walk based on the old Stage-2 mapping if
* the Stage-1 invalidation happened first.
*/
dsb ish
tlbi vmalle1is
dsb sy
dsb ish
isb
msr vttbr_el2, xzr
@ -643,7 +649,7 @@ ENTRY(__kvm_flush_vm_context)
dsb ishst
tlbi alle1is
ic ialluis
dsb sy
dsb ish
ret
ENDPROC(__kvm_flush_vm_context)