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msm: mdss: Move double bufferring mode support for dsi to dtsi

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Move double bufferring mode support property for dsi controller
to dtsi as it is not supported on 8909.

Change-Id: I2d99c34af7d4b9eef8f4503bad6fcd1480b2bde6
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
This commit is contained in:
Shivaraj Shetty 2014-10-21 23:46:37 +05:30 committed by Sandeep Panda
parent d52c796dc4
commit 2639a48f95
4 changed files with 9 additions and 6 deletions
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2
Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt
View file

@ -75,6 +75,7 @@ Optional properties:
- qcom,mmss-ulp-clamp-ctrl-offset: Specifies the offset for dsi ulps clamp control register.
- qcom,mmss-phyreset-ctrl-offset: Specifies the offset for dsi phy reset control register.
- qcom,dsi-irq-line: Boolean specifies if DSI has a different irq line than mdp.
- qcom,timing-db-mode: Boolean specifies dsi timing mode registers are supported or not.
Example:
mdss_dsi0: qcom,mdss_dsi@fd922800 {
@ -113,6 +114,7 @@ Example:
qcom,platform-mode-gpio = <&msmgpio 7 0>;
qcom,dsi-panel-bias-vreg;
qcom,dsi-irq-line;
qcom,timing-db-mode;
qcom,core-supply-entries {
#address-cells = <1>;

3
drivers/video/msm/mdss/mdss_dsi.c
View file

@ -1805,6 +1805,9 @@ int dsi_panel_device_register(struct device_node *pan_node,
ctrl_pdata->mode_gpio = -EINVAL;
}
ctrl_pdata->timing_db_mode = of_property_read_bool(
ctrl_pdev->dev.of_node, "qcom,timing-db-mode");
if (mdss_dsi_clk_init(ctrl_pdev, ctrl_pdata)) {
pr_err("%s: unable to initialize Dsi ctrl clks\n", __func__);
return -EPERM;

1
drivers/video/msm/mdss/mdss_dsi.h
View file

@ -374,6 +374,7 @@ struct mdss_dsi_ctrl_pdata {
bool ulps;
bool core_power;
bool mmss_clamp;
bool timing_db_mode;
struct dsi_buf tx_buf;
struct dsi_buf rx_buf;

9
drivers/video/msm/mdss/mdss_dsi_host.c
View file

@ -925,7 +925,7 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data, dst_bpp;
u32 dummy_xres = 0, dummy_yres = 0;
u32 hsync_period, vsync_period, ctrl_rev;
u32 hsync_period, vsync_period;
ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
panel_data);
@ -958,9 +958,7 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
mipi = &pdata->panel_info.mipi;
if (pdata->panel_info.type == MIPI_VIDEO_PANEL) {
ctrl_rev = MIPI_INP(ctrl_pdata->ctrl_base);
/* Enable DSI TIMING register double buffering for 8916/8939 */
if (ctrl_rev == MDSS_DSI_HW_REV_103_1)
if (ctrl_pdata->timing_db_mode)
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e8, 0x1);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x24,
((hspw + hbp + width + dummy_xres) << 16 |
@ -975,8 +973,7 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x30, (hspw << 16));
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x34, 0);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x38, (vspw << 16));
/* Flush DSI TIMING registers for 8916/8939 */
if (ctrl_rev == MDSS_DSI_HW_REV_103_1)
if (ctrl_pdata->timing_db_mode)
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e4, 0x1);
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)