edac: cortex_arm64_edac: Print out L2ECTLR register
The L2ECTLR register describes whether an interrupt was generated from the L2 memory or arrived through the AXI bus. Change-Id: Ic9416e5572743029c72f5b92b2bde978e2e7cd04 Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
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@ -1,4 +1,4 @@
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -204,10 +204,12 @@ static void ca53_ca57_print_error_state_regs(void)
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u64 l2merrsr;
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u64 cpumerrsr;
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u32 esr_el1;
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u32 l2ectlr;
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cpumerrsr = read_cpumerrsr_el1;
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l2merrsr = read_l2merrsr_el1;
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esr_el1 = read_esr_el1;
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l2ectlr = read_l2ectlr_el1;
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/* store data in uncached rtb logs */
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uncached_logk_pc(LOGK_READL, __builtin_return_address(0),
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@ -216,12 +218,15 @@ static void ca53_ca57_print_error_state_regs(void)
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(void *)l2merrsr);
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uncached_logk_pc(LOGK_READL, __builtin_return_address(0),
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(void *)((u64)esr_el1));
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uncached_logk_pc(LOGK_READL, __builtin_return_address(0),
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(void *)((u64)l2ectlr));
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edac_printk(KERN_CRIT, EDAC_CPU, "CPUMERRSR value = %#llx\n",
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cpumerrsr);
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edac_printk(KERN_CRIT, EDAC_CPU, "L2MERRSR value = %#llx\n", l2merrsr);
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edac_printk(KERN_CRIT, EDAC_CPU, "ESR value = %#x\n", esr_el1);
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edac_printk(KERN_CRIT, EDAC_CPU, "L2ECTLR value = %#x\n", l2ectlr);
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if (ESR_L2_DBE(esr_el1))
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edac_printk(KERN_CRIT, EDAC_CPU,
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"Double bit error on dirty L2 cacheline\n");
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