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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-11-07 04:09:21 +00:00
block: add helpers to run flush_dcache_page() against a bio and a request's pages
Mtdblock driver doesn't call flush_dcache_page for pages in request. So, this causes problems on architectures where the icache doesn't fill from the dcache or with dcache aliases. The patch fixes this. The ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE symbol was introduced to avoid pointless empty cache-thrashing loops on architectures for which flush_dcache_page() is a no-op. Every architecture was provided with this flush pages on architectires where ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE is equal 1 or do nothing otherwise. See "fix mtd_blkdevs problem with caches on some architectures" discussion on LKML for more information. Signed-off-by: Ilya Loginov <isloginov@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Peter Horton <phorton@bitbox.co.uk> Cc: "Ed L. Cashin" <ecashin@coraid.com> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
This commit is contained in:
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29 changed files with 83 additions and 0 deletions
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@ -9,6 +9,7 @@
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -408,6 +408,7 @@ extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
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* about to change to user space. This is the same method as used on SPARC64.
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* See update_mmu_cache for the user space part.
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*/
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *);
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extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
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@ -107,6 +107,7 @@ extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
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* do something here, but only for certain configurations. No such
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* configurations exist at this time.
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*/
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(page) do { } while (0)
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#define flush_dcache_mmap_unlock(page) do { } while (0)
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@ -68,9 +68,11 @@ do { memcpy(dst, src, len); \
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#endif
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#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
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# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
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#else
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# define flush_dcache_range(start,end) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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# define flush_dcache_page(page) do { } while (0)
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#endif
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@ -12,6 +12,7 @@
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -47,6 +47,7 @@ static inline void __flush_cache_all(void)
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}
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/* dcache/icache coherency... */
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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#ifdef CONFIG_MMU
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extern void flush_dcache_page(struct page *page);
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#else
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@ -15,6 +15,7 @@
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma,a,b)
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#define flush_cache_page(vma,p,pfn)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page)
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#define flush_dcache_mmap_lock(mapping)
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#define flush_dcache_mmap_unlock(mapping)
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@ -25,6 +25,7 @@
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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#define flush_dcache_page(page) \
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do { \
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clear_bit(PG_arch_1, &(page)->flags); \
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@ -12,6 +12,7 @@ extern void _flush_cache_copyback_all(void);
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -33,6 +34,7 @@ extern void smp_flush_cache_all(void);
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -46,6 +48,7 @@ extern void smp_flush_cache_all(void);
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -128,6 +128,7 @@ static inline void __flush_page_to_ram(void *vaddr)
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}
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}
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -12,6 +12,7 @@
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#define flush_cache_range(vma, start, end) __flush_cache_all()
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#define flush_cache_page(vma, vmaddr) do { } while (0)
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#define flush_dcache_range(start,len) __flush_cache_all()
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -37,6 +37,7 @@
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_dcache_range(start, end) __invalidate_dcache_range(start, end)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -38,6 +38,7 @@ extern void (*flush_cache_range)(struct vm_area_struct *vma,
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extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
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extern void __flush_dcache_page(struct page *page);
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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static inline void flush_dcache_page(struct page *page)
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{
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if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
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@ -26,6 +26,7 @@
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#define flush_cache_page(vma, vmaddr, pfn) do {} while (0)
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#define flush_cache_vmap(start, end) do {} while (0)
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#define flush_cache_vunmap(start, end) do {} while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do {} while (0)
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#define flush_dcache_mmap_lock(mapping) do {} while (0)
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#define flush_dcache_mmap_unlock(mapping) do {} while (0)
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@ -42,6 +42,7 @@ void flush_cache_mm(struct mm_struct *mm);
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *page);
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#define flush_dcache_mmap_lock(mapping) \
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@ -25,6 +25,7 @@
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *page);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -10,6 +10,7 @@
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -16,6 +16,7 @@ extern void flush_icache_range(unsigned long start, unsigned long end);
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extern void flush_dcache_range(unsigned long start, unsigned long end);
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#define flush_cache_dup_mm(mm) do {} while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do {} while (0)
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#define flush_dcache_mmap_lock(mapping) do {} while (0)
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#define flush_dcache_mmap_unlock(mapping) do {} while (0)
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@ -42,6 +42,7 @@ extern void flush_cache_page(struct vm_area_struct *vma,
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unsigned long addr, unsigned long pfn);
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extern void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end);
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *page);
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extern void flush_icache_range(unsigned long start, unsigned long end);
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extern void flush_icache_page(struct vm_area_struct *vma,
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@ -75,6 +75,7 @@ BTFIXUPDEF_CALL(void, flush_sig_insns, struct mm_struct *, unsigned long)
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extern void sparc_flush_page_to_ram(struct page *page);
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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#define flush_dcache_page(page) sparc_flush_page_to_ram(page)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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@ -37,6 +37,7 @@ extern void flush_dcache_page_all(struct mm_struct *mm, struct page *page);
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#endif
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extern void __flush_dcache_range(unsigned long start, unsigned long end);
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *page);
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#define flush_icache_page(vma, pg) do { } while(0)
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@ -12,6 +12,7 @@ static inline void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end) { }
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static inline void flush_cache_page(struct vm_area_struct *vma,
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unsigned long vmaddr, unsigned long pfn) { }
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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static inline void flush_dcache_page(struct page *page) { }
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static inline void flush_dcache_mmap_lock(struct address_space *mapping) { }
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static inline void flush_dcache_mmap_unlock(struct address_space *mapping) { }
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@ -101,6 +101,7 @@ static inline void __invalidate_icache_page_alias(unsigned long virt,
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#define flush_cache_vmap(start,end) flush_cache_all()
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#define flush_cache_vunmap(start,end) flush_cache_all()
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page*);
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extern void flush_cache_range(struct vm_area_struct*, ulong, ulong);
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extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned long);
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rq->rq_disk = bio->bi_bdev->bd_disk;
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}
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#if ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE
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/**
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* rq_flush_dcache_pages - Helper function to flush all pages in a request
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* @rq: the request to be flushed
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*
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* Description:
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* Flush all pages in @rq.
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*/
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void rq_flush_dcache_pages(struct request *rq)
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{
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struct req_iterator iter;
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struct bio_vec *bvec;
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rq_for_each_segment(bvec, rq, iter)
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flush_dcache_page(bvec->bv_page);
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}
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EXPORT_SYMBOL_GPL(rq_flush_dcache_pages);
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#endif
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/**
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* blk_lld_busy - Check if underlying low-level drivers of a device are busy
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* @q : the queue of the device being checked
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for (; nsect > 0; nsect--, block++, buf += tr->blksize)
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if (tr->readsect(dev, block, buf))
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return -EIO;
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rq_flush_dcache_pages(req);
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return 0;
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case WRITE:
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if (!tr->writesect)
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return -EIO;
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rq_flush_dcache_pages(req);
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for (; nsect > 0; nsect--, block++, buf += tr->blksize)
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if (tr->writesect(dev, block, buf))
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return -EIO;
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12
fs/bio.c
12
fs/bio.c
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}
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}
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#if ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE
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void bio_flush_dcache_pages(struct bio *bi)
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{
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int i;
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struct bio_vec *bvec;
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bio_for_each_segment(bvec, bi, i)
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flush_dcache_page(bvec->bv_page);
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}
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EXPORT_SYMBOL(bio_flush_dcache_pages);
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#endif
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/**
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* bio_endio - end I/O on a bio
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* @bio: bio
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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gfp_t, int);
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extern void bio_set_pages_dirty(struct bio *bio);
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extern void bio_check_pages_dirty(struct bio *bio);
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#ifndef ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE
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# error "You should define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE for your platform"
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#endif
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#if ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE
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extern void bio_flush_dcache_pages(struct bio *bi);
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#else
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static inline void bio_flush_dcache_pages(struct bio *bi)
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{
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}
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#endif
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extern struct bio *bio_copy_user(struct request_queue *, struct rq_map_data *,
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unsigned long, unsigned int, int, gfp_t);
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extern struct bio *bio_copy_user_iov(struct request_queue *,
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#define rq_iter_last(rq, _iter) \
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(_iter.bio->bi_next == NULL && _iter.i == _iter.bio->bi_vcnt-1)
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#ifndef ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE
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# error "You should define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE for your platform"
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#endif
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#if ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE
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extern void rq_flush_dcache_pages(struct request *rq);
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#else
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static inline void rq_flush_dcache_pages(struct request *rq)
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{
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}
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#endif
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extern int blk_register_queue(struct gendisk *disk);
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extern void blk_unregister_queue(struct gendisk *disk);
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extern void register_disk(struct gendisk *dev);
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