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Merge "crypto: msm: Add debug log"

This commit is contained in:
Linux Build Service Account 2014-01-23 03:21:48 -08:00 committed by Gerrit - the friendly Code Review server
parent dfcdc686dc e2bd6519fc
commit 35f90d26b1
1 changed files with 176 additions and 194 deletions
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370
drivers/crypto/msm/qce50.c
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@ -1042,6 +1042,68 @@ static int _ce_f8_setup(struct qce_device *pce_dev, struct qce_f8_req *req,
return 0;
}
static void _qce_dump_descr_fifos(struct qce_device *pce_dev)
{
int i, j, ents;
struct sps_iovec *iovec = pce_dev->ce_sps.in_transfer.iovec;
uint32_t cmd_flags = SPS_IOVEC_FLAG_CMD;
pr_info("==============================================\n");
pr_info("CONSUMER (TX/IN/DEST) PIPE DESCRIPTOR\n");
pr_info("==============================================\n");
for (i = 0; i < pce_dev->ce_sps.in_transfer.iovec_count; i++) {
pr_info(" [%d] addr=0x%x size=0x%x flags=0x%x\n", i,
iovec->addr, iovec->size, iovec->flags);
if (iovec->flags & cmd_flags) {
struct sps_command_element *pced;
pced = (struct sps_command_element *)
(GET_VIRT_ADDR(iovec->addr));
ents = iovec->size/(sizeof(struct sps_command_element));
for (j = 0; j < ents; j++) {
pr_info(" [%d] [0x%x] 0x%x\n", j,
pced->addr, pced->data);
pced++;
}
}
iovec++;
}
pr_info("==============================================\n");
pr_info("PRODUCER (RX/OUT/SRC) PIPE DESCRIPTOR\n");
pr_info("==============================================\n");
iovec = pce_dev->ce_sps.out_transfer.iovec;
for (i = 0; i < pce_dev->ce_sps.out_transfer.iovec_count; i++) {
pr_info(" [%d] addr=0x%x size=0x%x flags=0x%x\n", i,
iovec->addr, iovec->size, iovec->flags);
iovec++;
}
}
#ifdef QCE_DEBUG
static void _qce_dump_descr_fifos_dbg(struct qce_device *pce_dev)
{
_qce_dump_descr_fifos(pce_dev);
}
#define QCE_WRITE_REG(val, addr) \
{ \
pr_info(" [0x%x] 0x%x\n", (uint32_t)addr, (uint32_t)val); \
writel_relaxed(val, addr); \
}
#else
static void _qce_dump_descr_fifos_dbg(struct qce_device *pce_dev)
{
}
#define QCE_WRITE_REG(val, addr) \
writel_relaxed(val, addr)
#endif
static int _ce_setup_hash_direct(struct qce_device *pce_dev,
struct qce_sha_req *sreq)
{
@ -1057,9 +1119,9 @@ static int _ce_setup_hash_direct(struct qce_device *pce_dev,
uint32_t auth_cfg = 0;
/* clear status */
writel_relaxed(0, pce_dev->iobase + CRYPTO_STATUS_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_STATUS_REG);
writel_relaxed(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase +
QCE_WRITE_REG(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase +
CRYPTO_CONFIG_REG));
/*
* Ensure previous instructions (setting the CONFIG register)
@ -1071,22 +1133,22 @@ static int _ce_setup_hash_direct(struct qce_device *pce_dev,
if (sreq->alg == QCE_HASH_AES_CMAC) {
/* write seg_cfg */
writel_relaxed(0, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG);
/* write seg_cfg */
writel_relaxed(0, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);
/* write seg_cfg */
writel_relaxed(0, pce_dev->iobase + CRYPTO_ENCR_SEG_SIZE_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_ENCR_SEG_SIZE_REG);
/* Clear auth_ivn, auth_keyn registers */
for (i = 0; i < 16; i++) {
writel_relaxed(0, (pce_dev->iobase +
QCE_WRITE_REG(0, (pce_dev->iobase +
(CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t))));
writel_relaxed(0, (pce_dev->iobase +
QCE_WRITE_REG(0, (pce_dev->iobase +
(CRYPTO_AUTH_KEY0_REG + i*sizeof(uint32_t))));
}
/* write auth_bytecnt 0/1/2/3, start with 0 */
for (i = 0; i < 4; i++)
writel_relaxed(0, pce_dev->iobase +
QCE_WRITE_REG(0, pce_dev->iobase +
CRYPTO_AUTH_BYTECNT0_REG +
i * sizeof(uint32_t));
@ -1114,7 +1176,7 @@ static int _ce_setup_hash_direct(struct qce_device *pce_dev,
} else {
/* setup key */
for (i = 0; i < authk_size_in_word; i++)
writel_relaxed(mackey32[i], (pce_dev->iobase +
QCE_WRITE_REG(mackey32[i], (pce_dev->iobase +
(CRYPTO_AUTH_KEY0_REG +
i*sizeof(uint32_t))));
}
@ -1165,20 +1227,20 @@ static int _ce_setup_hash_direct(struct qce_device *pce_dev,
/* Set auth_ivn, auth_keyn registers */
for (i = 0; i < 5; i++)
writel_relaxed(auth32[i], (pce_dev->iobase +
QCE_WRITE_REG(auth32[i], (pce_dev->iobase +
(CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t))));
if ((sreq->alg == QCE_HASH_SHA256) ||
(sreq->alg == QCE_HASH_SHA256_HMAC)) {
for (i = 5; i < 8; i++)
writel_relaxed(auth32[i], (pce_dev->iobase +
QCE_WRITE_REG(auth32[i], (pce_dev->iobase +
(CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t))));
}
/* write auth_bytecnt 0/1/2/3, start with 0 */
for (i = 0; i < 2; i++)
writel_relaxed(sreq->auth_data[i], pce_dev->iobase +
QCE_WRITE_REG(sreq->auth_data[i], pce_dev->iobase +
CRYPTO_AUTH_BYTECNT0_REG +
i * sizeof(uint32_t));
@ -1197,28 +1259,29 @@ static int _ce_setup_hash_direct(struct qce_device *pce_dev,
auth_cfg |= 1 << CRYPTO_USE_PIPE_KEY_AUTH;
go_proc:
/* write seg_cfg */
writel_relaxed(auth_cfg, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG);
QCE_WRITE_REG(auth_cfg, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG);
/* write auth seg_size */
writel_relaxed(sreq->size, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG);
QCE_WRITE_REG(sreq->size, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG);
/* write auth_seg_start */
writel_relaxed(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG);
/* reset encr seg_cfg */
writel_relaxed(0, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);
/* write seg_size */
writel_relaxed(sreq->size, pce_dev->iobase + CRYPTO_SEG_SIZE_REG);
QCE_WRITE_REG(sreq->size, pce_dev->iobase + CRYPTO_SEG_SIZE_REG);
writel_relaxed(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase +
QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase +
CRYPTO_CONFIG_REG));
/* issue go to crypto */
if (use_hw_key == false)
writel_relaxed(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
if (use_hw_key == false) {
QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
pce_dev->iobase + CRYPTO_GOPROC_REG);
else
writel_relaxed(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
} else {
QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
pce_dev->iobase + CRYPTO_GOPROC_QC_KEY_REG);
}
/*
* Ensure previous instructions (setting the GO register)
* was completed before issuing a DMA transfer request
@ -1244,9 +1307,9 @@ static int _ce_setup_aead_direct(struct qce_device *pce_dev,
/* clear status */
writel_relaxed(0, pce_dev->iobase + CRYPTO_STATUS_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_STATUS_REG);
writel_relaxed(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase +
QCE_WRITE_REG(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase +
CRYPTO_CONFIG_REG));
/*
* Ensure previous instructions (setting the CONFIG register)
@ -1332,7 +1395,7 @@ static int _ce_setup_aead_direct(struct qce_device *pce_dev,
if (q_req->mode != QCE_MODE_ECB) {
_byte_stream_to_net_words(enciv32, q_req->iv, ivsize);
for (i = 0; i < enciv_in_word; i++)
writel_relaxed(enciv32[i], pce_dev->iobase +
QCE_WRITE_REG(enciv32[i], pce_dev->iobase +
(CRYPTO_CNTR0_IV0_REG + i * sizeof(uint32_t)));
}
@ -1342,35 +1405,35 @@ static int _ce_setup_aead_direct(struct qce_device *pce_dev,
*/
_byte_stream_to_net_words(enckey32, q_req->enckey, key_size);
for (i = 0; i < enck_size_in_word; i++)
writel_relaxed(enckey32[i], pce_dev->iobase +
QCE_WRITE_REG(enckey32[i], pce_dev->iobase +
(CRYPTO_ENCR_KEY0_REG + i * sizeof(uint32_t)));
/* write encr seg cfg */
if (q_req->dir == QCE_ENCRYPT)
encr_cfg |= (1 << CRYPTO_ENCODE);
writel_relaxed(encr_cfg, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);
QCE_WRITE_REG(encr_cfg, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);
/* we only support sha1-hmac at this point */
_byte_stream_to_net_words(mackey32, q_req->authkey,
q_req->authklen);
for (i = 0; i < authk_size_in_word; i++)
writel_relaxed(mackey32[i], pce_dev->iobase +
QCE_WRITE_REG(mackey32[i], pce_dev->iobase +
(CRYPTO_AUTH_KEY0_REG + i * sizeof(uint32_t)));
for (i = 0; i < 5; i++)
writel_relaxed(_std_init_vector_sha1[i], pce_dev->iobase +
QCE_WRITE_REG(_std_init_vector_sha1[i], pce_dev->iobase +
(CRYPTO_AUTH_IV0_REG + i * sizeof(uint32_t)));
/* write auth_bytecnt 0/1, start with 0 */
writel_relaxed(0, pce_dev->iobase + CRYPTO_AUTH_BYTECNT0_REG);
writel_relaxed(0, pce_dev->iobase + CRYPTO_AUTH_BYTECNT1_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_BYTECNT0_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_BYTECNT1_REG);
/* write encr seg size */
writel_relaxed(q_req->cryptlen, pce_dev->iobase +
QCE_WRITE_REG(q_req->cryptlen, pce_dev->iobase +
CRYPTO_ENCR_SEG_SIZE_REG);
/* write encr start */
writel_relaxed(coffset & 0xffff, pce_dev->iobase +
QCE_WRITE_REG(coffset & 0xffff, pce_dev->iobase +
CRYPTO_ENCR_SEG_START_REG);
a_cfg = (CRYPTO_AUTH_MODE_HMAC << CRYPTO_AUTH_MODE) |
@ -1384,24 +1447,24 @@ static int _ce_setup_aead_direct(struct qce_device *pce_dev,
a_cfg |= (CRYPTO_AUTH_POS_BEFORE << CRYPTO_AUTH_POS);
/* write auth seg_cfg */
writel_relaxed(a_cfg, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG);
QCE_WRITE_REG(a_cfg, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG);
/* write auth seg_size */
writel_relaxed(totallen_in, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG);
QCE_WRITE_REG(totallen_in, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG);
/* write auth_seg_start */
writel_relaxed(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG);
/* write seg_size */
writel_relaxed(totallen_in, pce_dev->iobase + CRYPTO_SEG_SIZE_REG);
QCE_WRITE_REG(totallen_in, pce_dev->iobase + CRYPTO_SEG_SIZE_REG);
writel_relaxed(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase +
QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase +
CRYPTO_CONFIG_REG));
/* issue go to crypto */
writel_relaxed(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
pce_dev->iobase + CRYPTO_GOPROC_REG);
/*
* Ensure previous instructions (setting the GO register)
@ -1427,9 +1490,9 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev,
int i;
/* clear status */
writel_relaxed(0, pce_dev->iobase + CRYPTO_STATUS_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_STATUS_REG);
writel_relaxed(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase +
QCE_WRITE_REG(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase +
CRYPTO_CONFIG_REG));
/*
* Ensure previous instructions (setting the CONFIG register)
@ -1463,20 +1526,20 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev,
/* Clear auth_ivn, auth_keyn registers */
for (i = 0; i < 16; i++) {
writel_relaxed(0, (pce_dev->iobase +
QCE_WRITE_REG(0, (pce_dev->iobase +
(CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t))));
writel_relaxed(0, (pce_dev->iobase +
QCE_WRITE_REG(0, (pce_dev->iobase +
(CRYPTO_AUTH_KEY0_REG + i*sizeof(uint32_t))));
}
/* write auth_bytecnt 0/1/2/3, start with 0 */
for (i = 0; i < 4; i++)
writel_relaxed(0, pce_dev->iobase +
QCE_WRITE_REG(0, pce_dev->iobase +
CRYPTO_AUTH_BYTECNT0_REG +
i * sizeof(uint32_t));
/* write nonce */
_byte_stream_to_net_words(nonce32, creq->nonce, MAX_NONCE);
for (i = 0; i < noncelen32; i++)
writel_relaxed(nonce32[i], pce_dev->iobase +
QCE_WRITE_REG(nonce32[i], pce_dev->iobase +
CRYPTO_AUTH_INFO_NONCE0_REG +
(i*sizeof(uint32_t)));
@ -1498,21 +1561,22 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev,
auth_cfg &= ~(1 << CRYPTO_USE_HW_KEY_AUTH);
/* write auth key */
for (i = 0; i < authklen32; i++)
writel_relaxed(enckey32[i], pce_dev->iobase +
QCE_WRITE_REG(enckey32[i], pce_dev->iobase +
CRYPTO_AUTH_KEY0_REG + (i*sizeof(uint32_t)));
}
writel_relaxed(auth_cfg, pce_dev->iobase +
QCE_WRITE_REG(auth_cfg, pce_dev->iobase +
CRYPTO_AUTH_SEG_CFG_REG);
if (creq->dir == QCE_ENCRYPT)
writel_relaxed(totallen_in, pce_dev->iobase +
if (creq->dir == QCE_ENCRYPT) {
QCE_WRITE_REG(totallen_in, pce_dev->iobase +
CRYPTO_AUTH_SEG_SIZE_REG);
else
writel_relaxed((totallen_in - creq->authsize),
} else {
QCE_WRITE_REG((totallen_in - creq->authsize),
pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG);
writel_relaxed(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG);
}
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG);
} else {
if (creq->op != QCE_REQ_AEAD)
writel_relaxed(0, pce_dev->iobase +
QCE_WRITE_REG(0, pce_dev->iobase +
CRYPTO_AUTH_SEG_CFG_REG);
}
/*
@ -1561,26 +1625,26 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev,
if (creq->mode != QCE_MODE_ECB) {
encr_cfg = pce_dev->reg.encr_cfg_des_cbc;
_byte_stream_to_net_words(enciv32, creq->iv, ivsize);
writel_relaxed(enciv32[0], pce_dev->iobase +
QCE_WRITE_REG(enciv32[0], pce_dev->iobase +
CRYPTO_CNTR0_IV0_REG);
writel_relaxed(enciv32[1], pce_dev->iobase +
QCE_WRITE_REG(enciv32[1], pce_dev->iobase +
CRYPTO_CNTR1_IV1_REG);
} else {
encr_cfg = pce_dev->reg.encr_cfg_des_ecb;
}
if (use_hw_key == false) {
writel_relaxed(enckey32[0], pce_dev->iobase +
QCE_WRITE_REG(enckey32[0], pce_dev->iobase +
CRYPTO_ENCR_KEY0_REG);
writel_relaxed(enckey32[1], pce_dev->iobase +
QCE_WRITE_REG(enckey32[1], pce_dev->iobase +
CRYPTO_ENCR_KEY1_REG);
}
break;
case CIPHER_ALG_3DES:
if (creq->mode != QCE_MODE_ECB) {
_byte_stream_to_net_words(enciv32, creq->iv, ivsize);
writel_relaxed(enciv32[0], pce_dev->iobase +
QCE_WRITE_REG(enciv32[0], pce_dev->iobase +
CRYPTO_CNTR0_IV0_REG);
writel_relaxed(enciv32[1], pce_dev->iobase +
QCE_WRITE_REG(enciv32[1], pce_dev->iobase +
CRYPTO_CNTR1_IV1_REG);
encr_cfg = pce_dev->reg.encr_cfg_3des_cbc;
} else {
@ -1589,7 +1653,7 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev,
if (use_hw_key == false) {
/* write encr key */
for (i = 0; i < 6; i++)
writel_relaxed(enckey32[0], (pce_dev->iobase +
QCE_WRITE_REG(enckey32[0], (pce_dev->iobase +
(CRYPTO_ENCR_KEY0_REG + i * sizeof(uint32_t))));
}
break;
@ -1607,7 +1671,7 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev,
creq->encklen/2);
/* write xts encr key */
for (i = 0; i < xtsklen; i++)
writel_relaxed(xtskey32[i],
QCE_WRITE_REG(xtskey32[i],
pce_dev->iobase +
CRYPTO_ENCR_XTS_KEY0_REG +
(i * sizeof(uint32_t)));
@ -1615,19 +1679,19 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev,
/* write xts du size */
switch (creq->flags & QCRYPTO_CTX_XTS_MASK) {
case QCRYPTO_CTX_XTS_DU_SIZE_512B:
writel_relaxed(
QCE_WRITE_REG(
min((uint32_t)QCE_SECTOR_SIZE,
creq->cryptlen), pce_dev->iobase +
CRYPTO_ENCR_XTS_DU_SIZE_REG);
break;
case QCRYPTO_CTX_XTS_DU_SIZE_1KB:
writel_relaxed(
QCE_WRITE_REG(
min((uint32_t)(QCE_SECTOR_SIZE * 2),
creq->cryptlen), pce_dev->iobase +
CRYPTO_ENCR_XTS_DU_SIZE_REG);
break;
default:
writel_relaxed(creq->cryptlen,
QCE_WRITE_REG(creq->cryptlen,
pce_dev->iobase +
CRYPTO_ENCR_XTS_DU_SIZE_REG);
break;
@ -1643,19 +1707,19 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev,
/* write encr cntr iv */
for (i = 0; i <= 3; i++)
writel_relaxed(enciv32[i], pce_dev->iobase +
QCE_WRITE_REG(enciv32[i], pce_dev->iobase +
CRYPTO_CNTR0_IV0_REG +
(i * sizeof(uint32_t)));
if (creq->mode == QCE_MODE_CCM) {
/* write cntr iv for ccm */
for (i = 0; i <= 3; i++)
writel_relaxed(enciv32[i],
QCE_WRITE_REG(enciv32[i],
pce_dev->iobase +
CRYPTO_ENCR_CCM_INT_CNTR0_REG +
(i * sizeof(uint32_t)));
/* update cntr_iv[3] by one */
writel_relaxed((enciv32[3] + 1),
QCE_WRITE_REG((enciv32[3] + 1),
pce_dev->iobase +
CRYPTO_CNTR0_IV0_REG +
(3 * sizeof(uint32_t)));
@ -1668,7 +1732,7 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev,
} else {
if ((use_hw_key == false) && (use_pipe_key == false)) {
for (i = 0; i < enck_size_in_word; i++)
writel_relaxed(enckey32[i],
QCE_WRITE_REG(enckey32[i],
pce_dev->iobase +
CRYPTO_ENCR_KEY0_REG +
(i * sizeof(uint32_t)));
@ -1688,35 +1752,37 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev,
else
encr_cfg &= ~(CRYPTO_USE_HW_KEY << CRYPTO_USE_HW_KEY_ENCR);
/* write encr seg cfg */
writel_relaxed(encr_cfg, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);
QCE_WRITE_REG(encr_cfg, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);
/* write encr seg size */
if ((creq->mode == QCE_MODE_CCM) && (creq->dir == QCE_DECRYPT))
writel_relaxed((creq->cryptlen + creq->authsize),
if ((creq->mode == QCE_MODE_CCM) && (creq->dir == QCE_DECRYPT)) {
QCE_WRITE_REG((creq->cryptlen + creq->authsize),
pce_dev->iobase + CRYPTO_ENCR_SEG_SIZE_REG);
else
writel_relaxed(creq->cryptlen,
} else {
QCE_WRITE_REG(creq->cryptlen,
pce_dev->iobase + CRYPTO_ENCR_SEG_SIZE_REG);
}
/* write encr seg start */
writel_relaxed((coffset & 0xffff),
QCE_WRITE_REG((coffset & 0xffff),
pce_dev->iobase + CRYPTO_ENCR_SEG_START_REG);
/* write encr seg start */
writel_relaxed(0xffffffff,
QCE_WRITE_REG(0xffffffff,
pce_dev->iobase + CRYPTO_CNTR_MASK_REG);
/* write seg size */
writel_relaxed(totallen_in, pce_dev->iobase + CRYPTO_SEG_SIZE_REG);
QCE_WRITE_REG(totallen_in, pce_dev->iobase + CRYPTO_SEG_SIZE_REG);
writel_relaxed(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase +
QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase +
CRYPTO_CONFIG_REG));
/* issue go to crypto */
if (use_hw_key == false)
writel_relaxed(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
if (use_hw_key == false) {
QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
pce_dev->iobase + CRYPTO_GOPROC_REG);
else
writel_relaxed(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
} else {
QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
pce_dev->iobase + CRYPTO_GOPROC_QC_KEY_REG);
}
/*
* Ensure previous instructions (setting the GO register)
* was completed before issuing a DMA transfer request
@ -1744,10 +1810,10 @@ static int _ce_f9_setup_direct(struct qce_device *pce_dev,
};
/* clear status */
writel_relaxed(0, pce_dev->iobase + CRYPTO_STATUS_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_STATUS_REG);
/* set big endian configuration */
writel_relaxed(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase +
QCE_WRITE_REG(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase +
CRYPTO_CONFIG_REG));
/*
* Ensure previous instructions (setting the CONFIG register)
@ -1758,48 +1824,48 @@ static int _ce_f9_setup_direct(struct qce_device *pce_dev,
mb();
/* write enc_seg_cfg */
writel_relaxed(0, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);
/* write ecn_seg_size */
writel_relaxed(0, pce_dev->iobase + CRYPTO_ENCR_SEG_SIZE_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_ENCR_SEG_SIZE_REG);
/* write key in CRYPTO_AUTH_IV0-3_REG */
_byte_stream_to_net_words(ikey32, &req->ikey[0], OTA_KEY_SIZE);
for (i = 0; i < key_size_in_word; i++)
writel_relaxed(ikey32[i], (pce_dev->iobase +
QCE_WRITE_REG(ikey32[i], (pce_dev->iobase +
(CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t))));
/* write last bits in CRYPTO_AUTH_IV4_REG */
writel_relaxed(req->last_bits, (pce_dev->iobase +
QCE_WRITE_REG(req->last_bits, (pce_dev->iobase +
CRYPTO_AUTH_IV4_REG));
/* write fresh to CRYPTO_AUTH_BYTECNT0_REG */
writel_relaxed(req->fresh, (pce_dev->iobase +
QCE_WRITE_REG(req->fresh, (pce_dev->iobase +
CRYPTO_AUTH_BYTECNT0_REG));
/* write count-i to CRYPTO_AUTH_BYTECNT1_REG */
writel_relaxed(req->count_i, (pce_dev->iobase +
QCE_WRITE_REG(req->count_i, (pce_dev->iobase +
CRYPTO_AUTH_BYTECNT1_REG));
/* write auth seg cfg */
if (req->direction == QCE_OTA_DIR_DOWNLINK)
auth_cfg |= BIT(CRYPTO_F9_DIRECTION);
writel_relaxed(auth_cfg, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG);
QCE_WRITE_REG(auth_cfg, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG);
/* write auth seg size */
writel_relaxed(req->msize, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG);
QCE_WRITE_REG(req->msize, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG);
/* write auth seg start*/
writel_relaxed(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG);
/* write seg size */
writel_relaxed(req->msize, pce_dev->iobase + CRYPTO_SEG_SIZE_REG);
QCE_WRITE_REG(req->msize, pce_dev->iobase + CRYPTO_SEG_SIZE_REG);
/* set little endian configuration before go*/
writel_relaxed(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase +
QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase +
CRYPTO_CONFIG_REG));
/* write go */
writel_relaxed(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
pce_dev->iobase + CRYPTO_GOPROC_REG);
/*
* Ensure previous instructions (setting the GO register)
@ -1828,55 +1894,55 @@ static int _ce_f8_setup_direct(struct qce_device *pce_dev,
break;
};
/* clear status */
writel_relaxed(0, pce_dev->iobase + CRYPTO_STATUS_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_STATUS_REG);
/* set big endian configuration */
writel_relaxed(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase +
QCE_WRITE_REG(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase +
CRYPTO_CONFIG_REG));
/* write auth seg configuration */
writel_relaxed(0, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG);
/* write auth seg size */
writel_relaxed(0, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG);
QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG);
/* write key */
_byte_stream_to_net_words(ckey32, &req->ckey[0], OTA_KEY_SIZE);
for (i = 0; i < key_size_in_word; i++)
writel_relaxed(ckey32[i], (pce_dev->iobase +
QCE_WRITE_REG(ckey32[i], (pce_dev->iobase +
(CRYPTO_ENCR_KEY0_REG + i*sizeof(uint32_t))));
/* write encr seg cfg */
if (key_stream_mode)
encr_cfg |= BIT(CRYPTO_F8_KEYSTREAM_ENABLE);
if (req->direction == QCE_OTA_DIR_DOWNLINK)
encr_cfg |= BIT(CRYPTO_F8_DIRECTION);
writel_relaxed(encr_cfg, pce_dev->iobase +
QCE_WRITE_REG(encr_cfg, pce_dev->iobase +
CRYPTO_ENCR_SEG_CFG_REG);
/* write encr seg start */
writel_relaxed((cipher_offset & 0xffff), pce_dev->iobase +
QCE_WRITE_REG((cipher_offset & 0xffff), pce_dev->iobase +
CRYPTO_ENCR_SEG_START_REG);
/* write encr seg size */
writel_relaxed(cipher_size, pce_dev->iobase +
QCE_WRITE_REG(cipher_size, pce_dev->iobase +
CRYPTO_ENCR_SEG_SIZE_REG);
/* write seg size */
writel_relaxed(req->data_len, pce_dev->iobase +
QCE_WRITE_REG(req->data_len, pce_dev->iobase +
CRYPTO_SEG_SIZE_REG);
/* write cntr0_iv0 for countC */
writel_relaxed(req->count_c, pce_dev->iobase +
QCE_WRITE_REG(req->count_c, pce_dev->iobase +
CRYPTO_CNTR0_IV0_REG);
/* write cntr1_iv1 for nPkts, and bearer */
if (npkts == 1)
npkts = 0;
writel_relaxed(req->bearer << CRYPTO_CNTR1_IV1_REG_F8_BEARER |
QCE_WRITE_REG(req->bearer << CRYPTO_CNTR1_IV1_REG_F8_BEARER |
npkts << CRYPTO_CNTR1_IV1_REG_F8_PKT_CNT,
pce_dev->iobase + CRYPTO_CNTR1_IV1_REG);
/* set little endian configuration before go*/
writel_relaxed(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase +
QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase +
CRYPTO_CONFIG_REG));
/* write go */
writel_relaxed(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)),
pce_dev->iobase + CRYPTO_GOPROC_REG);
/*
* Ensure previous instructions (setting the GO register)
@ -2225,90 +2291,6 @@ static int _f8_complete(struct qce_device *pce_dev)
return 0;
}
#ifdef QCE_DEBUG
static void _qce_dump_descr_fifos(struct qce_device *pce_dev)
{
int i, j, ents;
struct sps_iovec *iovec = pce_dev->ce_sps.in_transfer.iovec;
uint32_t cmd_flags = SPS_IOVEC_FLAG_CMD;
printk(KERN_INFO "==============================================\n");
printk(KERN_INFO "CONSUMER (TX/IN/DEST) PIPE DESCRIPTOR\n");
printk(KERN_INFO "==============================================\n");
for (i = 0; i < pce_dev->ce_sps.in_transfer.iovec_count; i++) {
printk(KERN_INFO " [%d] addr=0x%x size=0x%x flags=0x%x\n", i,
iovec->addr, iovec->size, iovec->flags);
if (iovec->flags & cmd_flags) {
struct sps_command_element *pced;
pced = (struct sps_command_element *)
(GET_VIRT_ADDR(iovec->addr));
ents = iovec->size/(sizeof(struct sps_command_element));
for (j = 0; j < ents; j++) {
printk(KERN_INFO " [%d] [0x%x] 0x%x\n", j,
pced->addr, pced->data);
pced++;
}
}
iovec++;
}
printk(KERN_INFO "==============================================\n");
printk(KERN_INFO "PRODUCER (RX/OUT/SRC) PIPE DESCRIPTOR\n");
printk(KERN_INFO "==============================================\n");
iovec = pce_dev->ce_sps.out_transfer.iovec;
for (i = 0; i < pce_dev->ce_sps.out_transfer.iovec_count; i++) {
printk(KERN_INFO " [%d] addr=0x%x size=0x%x flags=0x%x\n", i,
iovec->addr, iovec->size, iovec->flags);
iovec++;
}
}
#else
static void _qce_dump_descr_fifos(struct qce_device *pce_dev)
{
}
#endif
static void _qce_dump_descr_fifos_fail(struct qce_device *pce_dev)
{
int i, j, ents;
struct sps_iovec *iovec = pce_dev->ce_sps.in_transfer.iovec;
uint32_t cmd_flags = SPS_IOVEC_FLAG_CMD;
printk(KERN_INFO "==============================================\n");
printk(KERN_INFO "CONSUMER (TX/IN/DEST) PIPE DESCRIPTOR\n");
printk(KERN_INFO "==============================================\n");
for (i = 0; i < pce_dev->ce_sps.in_transfer.iovec_count; i++) {
printk(KERN_INFO " [%d] addr=0x%x size=0x%x flags=0x%x\n", i,
iovec->addr, iovec->size, iovec->flags);
if (iovec->flags & cmd_flags) {
struct sps_command_element *pced;
pced = (struct sps_command_element *)
(GET_VIRT_ADDR(iovec->addr));
ents = iovec->size/(sizeof(struct sps_command_element));
for (j = 0; j < ents; j++) {
printk(KERN_INFO " [%d] [0x%x] 0x%x\n", j,
pced->addr, pced->data);
pced++;
}
}
iovec++;
}
printk(KERN_INFO "==============================================\n");
printk(KERN_INFO "PRODUCER (RX/OUT/SRC) PIPE DESCRIPTOR\n");
printk(KERN_INFO "==============================================\n");
iovec = pce_dev->ce_sps.out_transfer.iovec;
for (i = 0; i < pce_dev->ce_sps.out_transfer.iovec_count; i++) {
printk(KERN_INFO " [%d] addr=0x%x size=0x%x flags=0x%x\n", i,
iovec->addr, iovec->size, iovec->flags);
iovec++;
}
}
static void _qce_sps_iovec_count_init(struct qce_device *pce_dev)
{
pce_dev->ce_sps.in_transfer.iovec_count = 0;
@ -2414,14 +2396,14 @@ static int _qce_sps_transfer(struct qce_device *pce_dev)
{
int rc = 0;
_qce_dump_descr_fifos(pce_dev);
_qce_dump_descr_fifos_dbg(pce_dev);
if (pce_dev->ce_sps.in_transfer.iovec_count) {
rc = sps_transfer(pce_dev->ce_sps.consumer.pipe,
&pce_dev->ce_sps.in_transfer);
if (rc) {
pr_err("sps_xfr() fail (consumer pipe=0x%x) rc = %d,",
(u32)pce_dev->ce_sps.consumer.pipe, rc);
_qce_dump_descr_fifos_fail(pce_dev);
_qce_dump_descr_fifos(pce_dev);
return rc;
}
}