amd64_edac: Remove two-stage initialization
Now that all prerequisites are in place, drop the two-stage driver instances initialization in favor of the following simple init sequence: 1. Probe PCI device: we only test ECC capabilities here and if none exit early. 2. If the hw supports ECC and it is/can be enabled, we init the per-node instance. Remove "amd64_" prefix from static functions touched, while at it. There actually should be no visible functional change resulting from this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov
parent
2299ef7114
commit
360b7f3c60
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@ -15,9 +15,13 @@ module_param(ecc_enable_override, int, 0644);
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static struct msr __percpu *msrs;
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/*
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* count successfully initialized driver instances for setup_pci_device()
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*/
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static atomic_t drv_instances = ATOMIC_INIT(0);
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/* Per-node driver instances */
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static struct mem_ctl_info **mcis;
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static struct amd64_pvt **pvts;
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static struct ecc_settings **ecc_stngs;
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/*
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@ -1993,8 +1997,7 @@ void amd64_decode_bus_error(int node_id, struct mce *m, u32 nbcfg)
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* Use pvt->F2 which contains the F2 CPU PCI device to get the related
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* F1 (AddrMap) and F3 (Misc) devices. Return negative value on error.
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*/
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static int amd64_reserve_mc_sibling_devices(struct amd64_pvt *pvt, u16 f1_id,
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u16 f3_id)
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static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id)
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{
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/* Reserve the ADDRESS MAP Device */
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pvt->F1 = pci_get_related_function(pvt->F2->vendor, f1_id, pvt->F2);
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@ -2024,7 +2027,7 @@ static int amd64_reserve_mc_sibling_devices(struct amd64_pvt *pvt, u16 f1_id,
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return 0;
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}
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static void amd64_free_mc_sibling_devices(struct amd64_pvt *pvt)
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static void free_mc_sibling_devs(struct amd64_pvt *pvt)
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{
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pci_dev_put(pvt->F1);
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pci_dev_put(pvt->F3);
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@ -2034,7 +2037,7 @@ static void amd64_free_mc_sibling_devices(struct amd64_pvt *pvt)
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* Retrieve the hardware registers of the memory controller (this includes the
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* 'Address Map' and 'Misc' device regs)
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*/
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static void amd64_read_mc_registers(struct amd64_pvt *pvt)
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static void read_mc_regs(struct amd64_pvt *pvt)
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{
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u64 msr_val;
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u32 tmp;
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@ -2185,7 +2188,7 @@ static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt)
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* Initialize the array of csrow attribute instances, based on the values
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* from pci config hardware registers.
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*/
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static int amd64_init_csrows(struct mem_ctl_info *mci)
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static int init_csrows(struct mem_ctl_info *mci)
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{
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struct csrow_info *csrow;
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struct amd64_pvt *pvt = mci->pvt_info;
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@ -2388,26 +2391,25 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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return ret;
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}
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static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
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static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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struct pci_dev *F3)
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{
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u8 nid = pvt->mc_node_id;
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struct ecc_settings *s = ecc_stngs[nid];
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u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
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if (!s->nbctl_valid)
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return;
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amd64_read_pci_cfg(pvt->F3, K8_NBCTL, &value);
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amd64_read_pci_cfg(F3, K8_NBCTL, &value);
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value &= ~mask;
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value |= s->old_nbctl;
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pci_write_config_dword(pvt->F3, K8_NBCTL, value);
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pci_write_config_dword(F3, K8_NBCTL, value);
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/* restore previous BIOS DRAM ECC "off" setting we force-enabled */
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if (!s->flags.nb_ecc_prev) {
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amd64_read_pci_cfg(pvt->F3, K8_NBCFG, &value);
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amd64_read_pci_cfg(F3, K8_NBCFG, &value);
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value &= ~K8_NBCFG_ECC_ENABLE;
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pci_write_config_dword(pvt->F3, K8_NBCFG, value);
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pci_write_config_dword(F3, K8_NBCFG, value);
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}
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/* restore the NB Enable MCGCTL bit */
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@ -2457,7 +2459,7 @@ struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) +
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struct mcidev_sysfs_attribute terminator = { .attr = { .name = NULL } };
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static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
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static void set_mc_sysfs_attrs(struct mem_ctl_info *mci)
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{
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unsigned int i = 0, j = 0;
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@ -2472,7 +2474,7 @@ static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
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mci->mc_driver_sysfs_attributes = sysfs_attrs;
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}
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static void amd64_setup_mci_misc_attributes(struct mem_ctl_info *mci)
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static void setup_mci_misc_attrs(struct mem_ctl_info *mci)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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@ -2538,14 +2540,16 @@ static int amd64_init_one_instance(struct pci_dev *F2)
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{
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struct amd64_pvt *pvt = NULL;
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struct amd64_family_type *fam_type = NULL;
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struct mem_ctl_info *mci = NULL;
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int err = 0, ret;
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u8 nid = get_node_id(F2);
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ret = -ENOMEM;
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pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
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if (!pvt)
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goto err_exit;
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goto err_ret;
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pvt->mc_node_id = get_node_id(F2);
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pvt->mc_node_id = nid;
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pvt->F2 = F2;
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ret = -EINVAL;
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@ -2554,61 +2558,36 @@ static int amd64_init_one_instance(struct pci_dev *F2)
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goto err_free;
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ret = -ENODEV;
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err = amd64_reserve_mc_sibling_devices(pvt, fam_type->f1_id,
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fam_type->f3_id);
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err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f3_id);
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if (err)
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goto err_free;
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/*
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* Save the pointer to the private data for use in 2nd initialization
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* stage
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*/
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pvts[pvt->mc_node_id] = pvt;
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return 0;
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err_free:
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kfree(pvt);
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err_exit:
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return ret;
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}
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/*
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* This is the finishing stage of the init code. Needs to be performed after all
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* MCs' hardware have been prepped for accessing extended config space.
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*/
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static int amd64_init_2nd_stage(struct amd64_pvt *pvt)
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{
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int node_id = pvt->mc_node_id;
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struct mem_ctl_info *mci;
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int ret = -ENODEV;
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amd64_read_mc_registers(pvt);
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read_mc_regs(pvt);
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/*
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* We need to determine how many memory channels there are. Then use
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* that information for calculating the size of the dynamic instance
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* tables in the 'mci' structure
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* tables in the 'mci' structure.
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*/
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ret = -EINVAL;
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pvt->channel_count = pvt->ops->early_channel_count(pvt);
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if (pvt->channel_count < 0)
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goto err_exit;
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goto err_siblings;
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ret = -ENOMEM;
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mci = edac_mc_alloc(0, pvt->cs_count, pvt->channel_count, node_id);
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mci = edac_mc_alloc(0, pvt->cs_count, pvt->channel_count, nid);
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if (!mci)
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goto err_exit;
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goto err_siblings;
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mci->pvt_info = pvt;
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mci->dev = &pvt->F2->dev;
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amd64_setup_mci_misc_attributes(mci);
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if (amd64_init_csrows(mci))
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setup_mci_misc_attrs(mci);
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if (init_csrows(mci))
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mci->edac_cap = EDAC_FLAG_NONE;
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amd64_set_mc_sysfs_attributes(mci);
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set_mc_sysfs_attrs(mci);
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ret = -ENODEV;
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if (edac_mc_add_mc(mci)) {
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@ -2616,34 +2595,31 @@ static int amd64_init_2nd_stage(struct amd64_pvt *pvt)
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goto err_add_mc;
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}
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mcis[node_id] = mci;
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pvts[node_id] = NULL;
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/* register stuff with EDAC MCE */
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if (report_gart_errors)
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amd_report_gart_errors(true);
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amd_register_ecc_decoder(amd64_decode_bus_error);
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mcis[nid] = mci;
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atomic_inc(&drv_instances);
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return 0;
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err_add_mc:
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edac_mc_free(mci);
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err_exit:
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debugf0("failure to init 2nd stage: ret=%d\n", ret);
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err_siblings:
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free_mc_sibling_devs(pvt);
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amd64_restore_ecc_error_reporting(pvt);
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amd64_free_mc_sibling_devices(pvt);
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kfree(pvts[pvt->mc_node_id]);
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pvts[node_id] = NULL;
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err_free:
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kfree(pvt);
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err_ret:
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return ret;
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}
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static int __devinit amd64_probe_one_instance(struct pci_dev *pdev,
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const struct pci_device_id *mc_type)
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{
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@ -2678,8 +2654,10 @@ static int __devinit amd64_probe_one_instance(struct pci_dev *pdev,
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}
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ret = amd64_init_one_instance(pdev);
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if (ret < 0)
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if (ret < 0) {
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amd64_err("Error probing instance: %d\n", nid);
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restore_ecc_error_reporting(s, nid, F3);
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}
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return ret;
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@ -2695,6 +2673,9 @@ static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
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{
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struct mem_ctl_info *mci;
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struct amd64_pvt *pvt;
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u8 nid = get_node_id(pdev);
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struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
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struct ecc_settings *s = ecc_stngs[nid];
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/* Remove from EDAC CORE tracking list */
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mci = edac_mc_del_mc(&pdev->dev);
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@ -2703,20 +2684,20 @@ static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
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pvt = mci->pvt_info;
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amd64_restore_ecc_error_reporting(pvt);
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restore_ecc_error_reporting(s, nid, F3);
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amd64_free_mc_sibling_devices(pvt);
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free_mc_sibling_devs(pvt);
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/* unregister from EDAC MCE */
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amd_report_gart_errors(false);
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amd_unregister_ecc_decoder(amd64_decode_bus_error);
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kfree(ecc_stngs[pvt->mc_node_id]);
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ecc_stngs[pvt->mc_node_id] = NULL;
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kfree(ecc_stngs[nid]);
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ecc_stngs[nid] = NULL;
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/* Free the EDAC CORE resources */
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mci->pvt_info = NULL;
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mcis[pvt->mc_node_id] = NULL;
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mcis[nid] = NULL;
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kfree(pvt);
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edac_mc_free(mci);
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@ -2755,7 +2736,7 @@ static struct pci_driver amd64_pci_driver = {
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.id_table = amd64_pci_table,
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};
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static void amd64_setup_pci_device(void)
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static void setup_pci_device(void)
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{
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struct mem_ctl_info *mci;
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struct amd64_pvt *pvt;
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@ -2782,8 +2763,7 @@ static void amd64_setup_pci_device(void)
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static int __init amd64_edac_init(void)
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{
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int nb, err = -ENODEV;
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bool load_ok = false;
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int err = -ENODEV;
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edac_printk(KERN_INFO, EDAC_MOD_STR, EDAC_AMD64_VERSION "\n");
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@ -2793,49 +2773,40 @@ static int __init amd64_edac_init(void)
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goto err_ret;
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err = -ENOMEM;
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pvts = kzalloc(amd_nb_num() * sizeof(pvts[0]), GFP_KERNEL);
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mcis = kzalloc(amd_nb_num() * sizeof(mcis[0]), GFP_KERNEL);
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ecc_stngs = kzalloc(amd_nb_num() * sizeof(ecc_stngs[0]), GFP_KERNEL);
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if (!(pvts && mcis && ecc_stngs))
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if (!(mcis && ecc_stngs))
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goto err_ret;
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msrs = msrs_alloc();
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if (!msrs)
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goto err_ret;
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goto err_free;
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err = pci_register_driver(&amd64_pci_driver);
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if (err)
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goto err_pci;
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/*
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* At this point, the array 'pvts[]' contains pointers to alloc'd
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* amd64_pvt structs. These will be used in the 2nd stage init function
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* to finish initialization of the MC instances.
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*/
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err = -ENODEV;
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for (nb = 0; nb < amd_nb_num(); nb++) {
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if (!pvts[nb])
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continue;
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if (!atomic_read(&drv_instances))
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goto err_no_instances;
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err = amd64_init_2nd_stage(pvts[nb]);
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if (err)
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goto err_2nd_stage;
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setup_pci_device();
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return 0;
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load_ok = true;
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}
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if (load_ok) {
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amd64_setup_pci_device();
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return 0;
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}
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err_2nd_stage:
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err_no_instances:
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pci_unregister_driver(&amd64_pci_driver);
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err_pci:
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msrs_free(msrs);
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msrs = NULL;
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err_free:
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kfree(mcis);
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mcis = NULL;
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kfree(ecc_stngs);
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ecc_stngs = NULL;
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err_ret:
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return err;
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}
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@ -2853,9 +2824,6 @@ static void __exit amd64_edac_exit(void)
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kfree(mcis);
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mcis = NULL;
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kfree(pvts);
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pvts = NULL;
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msrs_free(msrs);
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msrs = NULL;
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}
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