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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
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ASoC: msm8x16-wcd: add boost and hph updates for cajon 2.0
In cajon 2.0, as per latest qcrg FSM toggle is required at powerup. Also update boost mode sequences for speaker. For combo usecase, HPH turn on is not ensuring MCLK bits are set before NCP or PA enable. Make changes to turn on MCLK bits first at HPH powerup sequence always. Change-Id: Icf858b83be0bdd6890335eaee6b33cc74fd189d3 Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
This commit is contained in:
Laxminath Kasam
parent
00edb936a5
commit
37cee28a55
1 changed files with 80 additions and 48 deletions
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@ -69,6 +69,9 @@
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#define MSM8X16_DIGITAL_CODEC_REG_SIZE 0x400
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#define MAX_ON_DEMAND_SUPPLY_NAME_LENGTH 64
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#define MCLK_RATE_9P6MHZ 9600000
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#define MCLK_RATE_12P288MHZ 12288000
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#define BUS_DOWN 1
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/*
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@ -1182,14 +1185,31 @@ static void msm8x16_wcd_boost_on(struct snd_soc_codec *codec)
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL,
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0xE1, 0xE1);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
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0x20, 0x20);
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usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
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0xDF, 0xDF);
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usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
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if (get_codec_version(msm8x16_wcd) < CAJON_2_0) {
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
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0x20, 0x20);
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usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
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0xDF, 0xDF);
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usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
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} else {
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
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0x40, 0x00);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
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0x20, 0x20);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
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0x80, 0x80);
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usleep_range(500, 510);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
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0x40, 0x40);
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usleep_range(500, 510);
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}
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}
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static void msm8x16_wcd_boost_off(struct snd_soc_codec *codec)
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@ -1623,6 +1643,39 @@ out:
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return ret;
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}
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static int msm8x16_wcd_codec_enable_clock_block(struct snd_soc_codec *codec,
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int enable)
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{
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struct msm8916_asoc_mach_data *pdata = NULL;
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pdata = snd_soc_card_get_drvdata(codec->card);
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if (enable) {
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_CDC_CLK_MCLK_CTL, 0x01, 0x01);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x03);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_MASTER_BIAS_CTL, 0x30, 0x30);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_DIGITAL_CDC_RST_CTL, 0x80, 0x80);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x0C);
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if (pdata->mclk_freq == MCLK_RATE_12P288MHZ)
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x00);
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else if (pdata->mclk_freq == MCLK_RATE_9P6MHZ)
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x01);
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} else {
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x00);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x00);
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}
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return 0;
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}
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static int msm8x16_wcd_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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@ -1632,6 +1685,7 @@ static int msm8x16_wcd_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
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dev_dbg(codec->dev, "%s: event = %d\n", __func__, event);
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switch (event) {
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case SND_SOC_DAPM_PRE_PMU:
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msm8x16_wcd_codec_enable_clock_block(codec, 1);
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if (!(strcmp(w->name, "EAR CP"))) {
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
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@ -2886,7 +2940,8 @@ static int msm8x16_wcd_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
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usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x10);
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msm8x16_wcd_boost_mode_sequence(codec, SPK_PMD);
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if (get_codec_version(msm8x16_wcd) < CAJON_2_0)
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msm8x16_wcd_boost_mode_sequence(codec, SPK_PMD);
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snd_soc_update_bits(codec, w->reg, 0x80, 0x00);
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switch (msm8x16_wcd->boost_option) {
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case BOOST_SWITCH:
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@ -2922,6 +2977,8 @@ static int msm8x16_wcd_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
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MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 0x01, 0x00);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
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if (get_codec_version(msm8x16_wcd) >= CAJON_2_0)
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msm8x16_wcd_boost_mode_sequence(codec, SPK_PMD);
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break;
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}
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return 0;
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@ -2940,6 +2997,7 @@ static int msm8x16_wcd_codec_enable_dig_clk(struct snd_soc_dapm_widget *w,
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event, w->name);
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switch (event) {
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case SND_SOC_DAPM_PRE_PMU:
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msm8x16_wcd_codec_enable_clock_block(codec, 1);
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snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
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msm8x16_wcd_boost_mode_sequence(codec, SPK_PMU);
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break;
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@ -3669,11 +3727,22 @@ static int msm8x16_wcd_hphl_dac_event(struct snd_soc_dapm_widget *w,
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switch (event) {
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case SND_SOC_DAPM_PRE_PMU:
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if (get_codec_version(msm8x16_wcd) > CAJON)
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN,
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0x08, 0x08);
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if (get_codec_version(msm8x16_wcd) >= CAJON) {
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST,
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0x80, 0x80);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST,
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0x80, 0x80);
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}
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if (get_codec_version(msm8x16_wcd) > CAJON)
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN,
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0x08, 0x00);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x02);
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snd_soc_update_bits(codec,
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@ -3705,17 +3774,11 @@ static int msm8x16_wcd_hphr_dac_event(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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struct snd_soc_codec *codec = w->codec;
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struct msm8x16_wcd_priv *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
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dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
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switch (event) {
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case SND_SOC_DAPM_PRE_PMU:
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if (get_codec_version(msm8x16_wcd) >= CAJON) {
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST,
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0x80, 0x80);
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}
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x02);
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snd_soc_update_bits(codec,
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@ -4010,39 +4073,6 @@ static void msm8x16_wcd_shutdown(struct snd_pcm_substream *substream,
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substream->name, substream->stream);
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}
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static int msm8x16_wcd_codec_enable_clock_block(struct snd_soc_codec *codec,
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int enable)
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{
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struct msm8916_asoc_mach_data *pdata = NULL;
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pdata = snd_soc_card_get_drvdata(codec->card);
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if (enable) {
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_CDC_CLK_MCLK_CTL, 0x01, 0x01);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x03);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_ANALOG_MASTER_BIAS_CTL, 0x30, 0x30);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_DIGITAL_CDC_RST_CTL, 0x80, 0x80);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x0C);
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if (pdata->mclk_freq == 12288000)
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x00);
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else if (pdata->mclk_freq == 9600000)
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x01);
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} else {
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x00);
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snd_soc_update_bits(codec,
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MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x00);
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}
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return 0;
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}
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int msm8x16_wcd_mclk_enable(struct snd_soc_codec *codec,
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int mclk_enable, bool dapm)
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{
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@ -4731,6 +4761,7 @@ static const struct msm8x16_wcd_reg_mask_val cajon_wcd_reg_defaults[] = {
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MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DRV_DBG, 0x01),
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MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL, 0xE1),
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MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
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MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_PA, 0xFA),
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};
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static const struct msm8x16_wcd_reg_mask_val cajon2p0_wcd_reg_defaults[] = {
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@ -4749,6 +4780,7 @@ static const struct msm8x16_wcd_reg_mask_val cajon2p0_wcd_reg_defaults[] = {
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MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
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MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_RX_EAR_STATUS, 0x10),
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MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_BYPASS_MODE, 0x18),
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MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_PA, 0xFA),
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};
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static void msm8x16_wcd_update_reg_defaults(struct snd_soc_codec *codec)
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