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r8169: Modify the mothod for PHY settings of RTL8111G 

Replace the current settings with rtl_writephy and rtl_readphy.
For the hardware, the settings are same with previous ones. This
make the setting method like the previous chips.

Signed-off-by: Hayes Wang <hayeswang@realtek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
hayeswang 2013-04-01 22:23:36 +00:00 committed by David S. Miller
parent 0427d0152e
commit 41f44d1389
1 changed files with 31 additions and 21 deletions
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52
drivers/net/ethernet/realtek/r8169.c
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@ -1024,14 +1024,6 @@ static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
(RTL_R32(GPHY_OCP) & 0xffff) : ~0;
}
static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
{
int val;
val = r8168_phy_ocp_read(tp, reg);
r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
}
static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
{
void __iomem *ioaddr = tp->mmio_addr;
@ -3370,23 +3362,41 @@ static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
{
rtl_apply_firmware(tp);
if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
else
rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
rtl_writephy(tp, 0x1f, 0x0a46);
if (rtl_readphy(tp, 0x10) & 0x0100) {
rtl_writephy(tp, 0x1f, 0x0bcc);
rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
} else {
rtl_writephy(tp, 0x1f, 0x0bcc);
rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
}
if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
else
rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
rtl_writephy(tp, 0x1f, 0x0a46);
if (rtl_readphy(tp, 0x13) & 0x0100) {
rtl_writephy(tp, 0x1f, 0x0c41);
rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
} else {
rtl_writephy(tp, 0x1f, 0x0bcc);
rtl_w1w0_phy(tp, 0x12, 0x0000, 0x0002);
}
rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
/* Enable PHY auto speed down */
rtl_writephy(tp, 0x1f, 0x0a44);
rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
r8168_phy_ocp_write(tp, 0xa436, 0x8012);
rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
/* EEE auto-fallback function */
rtl_writephy(tp, 0x1f, 0x0a4b);
rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
/* Enable UC LPF tune function */
rtl_writephy(tp, 0x1f, 0x0a43);
rtl_writephy(tp, 0x13, 0x8012);
rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
rtl_writephy(tp, 0x1f, 0x0c42);
rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
rtl_writephy(tp, 0x1f, 0x0000);
}
static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)