mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-11-07 04:09:21 +00:00
mips/kvm: Fix ABI by moving manipulation of CP0 registers to KVM_{G,S}ET_ONE_REG
Because not all 256 CP0 registers are ever implemented, we need a different method of manipulating them. Use the KVM_SET_ONE_REG/KVM_GET_ONE_REG mechanism. Now unused code and definitions are removed. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
David Daney
Gleb Natapov
parent
8d17dd041a
commit
4c73fb2b05
4 changed files with 322 additions and 75 deletions
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@ -496,10 +496,6 @@ struct kvm_mips_callbacks {
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uint32_t cause);
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int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority,
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uint32_t cause);
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int (*vcpu_ioctl_get_regs) (struct kvm_vcpu *vcpu,
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struct kvm_regs *regs);
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int (*vcpu_ioctl_set_regs) (struct kvm_vcpu *vcpu,
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struct kvm_regs *regs);
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};
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extern struct kvm_mips_callbacks *kvm_mips_callbacks;
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int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
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@ -13,10 +13,11 @@
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#include <linux/types.h>
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#define __KVM_MIPS
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#define N_MIPS_COPROC_REGS 32
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#define N_MIPS_COPROC_SEL 8
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/*
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* KVM MIPS specific structures and definitions.
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*
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* Some parts derived from the x86 version of this file.
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*/
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/*
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* for KVM_GET_REGS and KVM_SET_REGS
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@ -31,12 +32,6 @@ struct kvm_regs {
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__u64 hi;
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__u64 lo;
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__u64 pc;
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__u32 cp0reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
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};
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/* for KVM_GET_SREGS and KVM_SET_SREGS */
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struct kvm_sregs {
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};
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/*
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@ -55,21 +50,89 @@ struct kvm_fpu {
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__u32 pad;
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};
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/*
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* For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access CP0
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* registers. The id field is broken down as follows:
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*
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* bits[2..0] - Register 'sel' index.
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* bits[7..3] - Register 'rd' index.
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* bits[15..8] - Must be zero.
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* bits[63..16] - 1 -> CP0 registers.
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*
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* Other sets registers may be added in the future. Each set would
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* have its own identifier in bits[63..16].
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*
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* The addr field of struct kvm_one_reg must point to an aligned
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* 64-bit wide location. For registers that are narrower than
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* 64-bits, the value is stored in the low order bits of the location,
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* and sign extended to 64-bits.
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*
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* The registers defined in struct kvm_regs are also accessible, the
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* id values for these are below.
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*/
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#define KVM_REG_MIPS_R0 0
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#define KVM_REG_MIPS_R1 1
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#define KVM_REG_MIPS_R2 2
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#define KVM_REG_MIPS_R3 3
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#define KVM_REG_MIPS_R4 4
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#define KVM_REG_MIPS_R5 5
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#define KVM_REG_MIPS_R6 6
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#define KVM_REG_MIPS_R7 7
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#define KVM_REG_MIPS_R8 8
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#define KVM_REG_MIPS_R9 9
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#define KVM_REG_MIPS_R10 10
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#define KVM_REG_MIPS_R11 11
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#define KVM_REG_MIPS_R12 12
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#define KVM_REG_MIPS_R13 13
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#define KVM_REG_MIPS_R14 14
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#define KVM_REG_MIPS_R15 15
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#define KVM_REG_MIPS_R16 16
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#define KVM_REG_MIPS_R17 17
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#define KVM_REG_MIPS_R18 18
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#define KVM_REG_MIPS_R19 19
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#define KVM_REG_MIPS_R20 20
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#define KVM_REG_MIPS_R21 21
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#define KVM_REG_MIPS_R22 22
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#define KVM_REG_MIPS_R23 23
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#define KVM_REG_MIPS_R24 24
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#define KVM_REG_MIPS_R25 25
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#define KVM_REG_MIPS_R26 26
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#define KVM_REG_MIPS_R27 27
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#define KVM_REG_MIPS_R28 28
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#define KVM_REG_MIPS_R29 29
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#define KVM_REG_MIPS_R30 30
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#define KVM_REG_MIPS_R31 31
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#define KVM_REG_MIPS_HI 32
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#define KVM_REG_MIPS_LO 33
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#define KVM_REG_MIPS_PC 34
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/*
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* KVM MIPS specific structures and definitions
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*
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*/
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struct kvm_debug_exit_arch {
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__u64 epc;
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};
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/* for KVM_SET_GUEST_DEBUG */
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struct kvm_guest_debug_arch {
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};
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/* definition of registers in kvm_run */
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struct kvm_sync_regs {
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};
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/* dummy definition */
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struct kvm_sregs {
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};
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struct kvm_mips_interrupt {
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/* in */
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__u32 cpu;
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__u32 irq;
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};
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/* definition of registers in kvm_run */
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struct kvm_sync_regs {
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};
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#endif /* __LINUX_KVM_MIPS_H */
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@ -485,15 +485,253 @@ kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
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return -EINVAL;
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}
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#define KVM_REG_MIPS_CP0_INDEX (0x10000 + 8 * 0 + 0)
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#define KVM_REG_MIPS_CP0_ENTRYLO0 (0x10000 + 8 * 2 + 0)
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#define KVM_REG_MIPS_CP0_ENTRYLO1 (0x10000 + 8 * 3 + 0)
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#define KVM_REG_MIPS_CP0_CONTEXT (0x10000 + 8 * 4 + 0)
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#define KVM_REG_MIPS_CP0_USERLOCAL (0x10000 + 8 * 4 + 2)
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#define KVM_REG_MIPS_CP0_PAGEMASK (0x10000 + 8 * 5 + 0)
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#define KVM_REG_MIPS_CP0_PAGEGRAIN (0x10000 + 8 * 5 + 1)
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#define KVM_REG_MIPS_CP0_WIRED (0x10000 + 8 * 6 + 0)
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#define KVM_REG_MIPS_CP0_HWRENA (0x10000 + 8 * 7 + 0)
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#define KVM_REG_MIPS_CP0_BADVADDR (0x10000 + 8 * 8 + 0)
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#define KVM_REG_MIPS_CP0_COUNT (0x10000 + 8 * 9 + 0)
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#define KVM_REG_MIPS_CP0_ENTRYHI (0x10000 + 8 * 10 + 0)
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#define KVM_REG_MIPS_CP0_COMPARE (0x10000 + 8 * 11 + 0)
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#define KVM_REG_MIPS_CP0_STATUS (0x10000 + 8 * 12 + 0)
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#define KVM_REG_MIPS_CP0_CAUSE (0x10000 + 8 * 13 + 0)
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#define KVM_REG_MIPS_CP0_EBASE (0x10000 + 8 * 15 + 1)
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#define KVM_REG_MIPS_CP0_CONFIG (0x10000 + 8 * 16 + 0)
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#define KVM_REG_MIPS_CP0_CONFIG1 (0x10000 + 8 * 16 + 1)
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#define KVM_REG_MIPS_CP0_CONFIG2 (0x10000 + 8 * 16 + 2)
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#define KVM_REG_MIPS_CP0_CONFIG3 (0x10000 + 8 * 16 + 3)
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#define KVM_REG_MIPS_CP0_CONFIG7 (0x10000 + 8 * 16 + 7)
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#define KVM_REG_MIPS_CP0_XCONTEXT (0x10000 + 8 * 20 + 0)
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#define KVM_REG_MIPS_CP0_ERROREPC (0x10000 + 8 * 30 + 0)
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static u64 kvm_mips_get_one_regs[] = {
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KVM_REG_MIPS_R0,
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KVM_REG_MIPS_R1,
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KVM_REG_MIPS_R2,
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KVM_REG_MIPS_R3,
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KVM_REG_MIPS_R4,
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KVM_REG_MIPS_R5,
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KVM_REG_MIPS_R6,
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KVM_REG_MIPS_R7,
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KVM_REG_MIPS_R8,
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KVM_REG_MIPS_R9,
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KVM_REG_MIPS_R10,
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KVM_REG_MIPS_R11,
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KVM_REG_MIPS_R12,
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KVM_REG_MIPS_R13,
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KVM_REG_MIPS_R14,
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KVM_REG_MIPS_R15,
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KVM_REG_MIPS_R16,
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KVM_REG_MIPS_R17,
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KVM_REG_MIPS_R18,
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KVM_REG_MIPS_R19,
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KVM_REG_MIPS_R20,
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KVM_REG_MIPS_R21,
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KVM_REG_MIPS_R22,
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KVM_REG_MIPS_R23,
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KVM_REG_MIPS_R24,
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KVM_REG_MIPS_R25,
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KVM_REG_MIPS_R26,
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KVM_REG_MIPS_R27,
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KVM_REG_MIPS_R28,
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KVM_REG_MIPS_R29,
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KVM_REG_MIPS_R30,
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KVM_REG_MIPS_R31,
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KVM_REG_MIPS_HI,
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KVM_REG_MIPS_LO,
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KVM_REG_MIPS_PC,
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KVM_REG_MIPS_CP0_INDEX,
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KVM_REG_MIPS_CP0_CONTEXT,
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KVM_REG_MIPS_CP0_PAGEMASK,
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KVM_REG_MIPS_CP0_WIRED,
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KVM_REG_MIPS_CP0_BADVADDR,
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KVM_REG_MIPS_CP0_ENTRYHI,
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KVM_REG_MIPS_CP0_STATUS,
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KVM_REG_MIPS_CP0_CAUSE,
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/* EPC set via kvm_regs, et al. */
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KVM_REG_MIPS_CP0_CONFIG,
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KVM_REG_MIPS_CP0_CONFIG1,
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KVM_REG_MIPS_CP0_CONFIG2,
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KVM_REG_MIPS_CP0_CONFIG3,
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KVM_REG_MIPS_CP0_CONFIG7,
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KVM_REG_MIPS_CP0_ERROREPC
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};
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static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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u64 __user *uaddr = (u64 __user *)(long)reg->addr;
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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s64 v;
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switch (reg->id) {
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case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
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v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
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break;
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case KVM_REG_MIPS_HI:
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v = (long)vcpu->arch.hi;
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break;
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case KVM_REG_MIPS_LO:
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v = (long)vcpu->arch.lo;
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break;
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case KVM_REG_MIPS_PC:
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v = (long)vcpu->arch.pc;
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break;
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case KVM_REG_MIPS_CP0_INDEX:
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v = (long)kvm_read_c0_guest_index(cop0);
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break;
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case KVM_REG_MIPS_CP0_CONTEXT:
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v = (long)kvm_read_c0_guest_context(cop0);
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break;
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case KVM_REG_MIPS_CP0_PAGEMASK:
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v = (long)kvm_read_c0_guest_pagemask(cop0);
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break;
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case KVM_REG_MIPS_CP0_WIRED:
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v = (long)kvm_read_c0_guest_wired(cop0);
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break;
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case KVM_REG_MIPS_CP0_BADVADDR:
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v = (long)kvm_read_c0_guest_badvaddr(cop0);
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break;
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case KVM_REG_MIPS_CP0_ENTRYHI:
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v = (long)kvm_read_c0_guest_entryhi(cop0);
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break;
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case KVM_REG_MIPS_CP0_STATUS:
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v = (long)kvm_read_c0_guest_status(cop0);
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break;
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case KVM_REG_MIPS_CP0_CAUSE:
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v = (long)kvm_read_c0_guest_cause(cop0);
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break;
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case KVM_REG_MIPS_CP0_ERROREPC:
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v = (long)kvm_read_c0_guest_errorepc(cop0);
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break;
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case KVM_REG_MIPS_CP0_CONFIG:
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v = (long)kvm_read_c0_guest_config(cop0);
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break;
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case KVM_REG_MIPS_CP0_CONFIG1:
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v = (long)kvm_read_c0_guest_config1(cop0);
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break;
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case KVM_REG_MIPS_CP0_CONFIG2:
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v = (long)kvm_read_c0_guest_config2(cop0);
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break;
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case KVM_REG_MIPS_CP0_CONFIG3:
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v = (long)kvm_read_c0_guest_config3(cop0);
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break;
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case KVM_REG_MIPS_CP0_CONFIG7:
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v = (long)kvm_read_c0_guest_config7(cop0);
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break;
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default:
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return -EINVAL;
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}
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return put_user(v, uaddr);
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}
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static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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u64 __user *uaddr = (u64 __user *)(long)reg->addr;
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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u64 v;
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if (get_user(v, uaddr) != 0)
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return -EFAULT;
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switch (reg->id) {
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case KVM_REG_MIPS_R0:
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/* Silently ignore requests to set $0 */
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break;
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case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
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vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
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break;
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case KVM_REG_MIPS_HI:
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vcpu->arch.hi = v;
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break;
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case KVM_REG_MIPS_LO:
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vcpu->arch.lo = v;
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break;
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case KVM_REG_MIPS_PC:
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vcpu->arch.pc = v;
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break;
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case KVM_REG_MIPS_CP0_INDEX:
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kvm_write_c0_guest_index(cop0, v);
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break;
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case KVM_REG_MIPS_CP0_CONTEXT:
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kvm_write_c0_guest_context(cop0, v);
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break;
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case KVM_REG_MIPS_CP0_PAGEMASK:
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kvm_write_c0_guest_pagemask(cop0, v);
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break;
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case KVM_REG_MIPS_CP0_WIRED:
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kvm_write_c0_guest_wired(cop0, v);
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break;
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case KVM_REG_MIPS_CP0_BADVADDR:
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kvm_write_c0_guest_badvaddr(cop0, v);
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break;
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case KVM_REG_MIPS_CP0_ENTRYHI:
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kvm_write_c0_guest_entryhi(cop0, v);
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break;
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case KVM_REG_MIPS_CP0_STATUS:
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kvm_write_c0_guest_status(cop0, v);
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break;
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case KVM_REG_MIPS_CP0_CAUSE:
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kvm_write_c0_guest_cause(cop0, v);
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break;
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case KVM_REG_MIPS_CP0_ERROREPC:
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kvm_write_c0_guest_errorepc(cop0, v);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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long
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kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
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{
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struct kvm_vcpu *vcpu = filp->private_data;
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void __user *argp = (void __user *)arg;
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long r;
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int intr;
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switch (ioctl) {
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case KVM_SET_ONE_REG:
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case KVM_GET_ONE_REG: {
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struct kvm_one_reg reg;
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if (copy_from_user(®, argp, sizeof(reg)))
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return -EFAULT;
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if (ioctl == KVM_SET_ONE_REG)
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return kvm_mips_set_reg(vcpu, ®);
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else
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return kvm_mips_get_reg(vcpu, ®);
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}
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case KVM_GET_REG_LIST: {
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struct kvm_reg_list __user *user_list = argp;
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u64 __user *reg_dest;
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struct kvm_reg_list reg_list;
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unsigned n;
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if (copy_from_user(®_list, user_list, sizeof(reg_list)))
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return -EFAULT;
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n = reg_list.n;
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reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
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if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
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return -EFAULT;
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if (n < reg_list.n)
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return -E2BIG;
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reg_dest = user_list->reg;
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if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
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sizeof(kvm_mips_get_one_regs)))
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return -EFAULT;
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return 0;
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}
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case KVM_NMI:
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/* Treat the NMI as a CPU reset */
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r = kvm_mips_reset_vcpu(vcpu);
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@ -505,8 +743,6 @@ kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
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if (copy_from_user(&irq, argp, sizeof(irq)))
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goto out;
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intr = (int)irq.irq;
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kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
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irq.irq);
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@ -514,7 +750,7 @@ kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
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break;
|
||||
}
|
||||
default:
|
||||
r = -EINVAL;
|
||||
r = -ENOIOCTLCMD;
|
||||
}
|
||||
|
||||
out:
|
||||
|
|
@ -627,6 +863,9 @@ int kvm_dev_ioctl_check_extension(long ext)
|
|||
int r;
|
||||
|
||||
switch (ext) {
|
||||
case KVM_CAP_ONE_REG:
|
||||
r = 1;
|
||||
break;
|
||||
case KVM_CAP_COALESCED_MMIO:
|
||||
r = KVM_COALESCED_MMIO_PAGE_OFFSET;
|
||||
break;
|
||||
|
|
@ -635,7 +874,6 @@ int kvm_dev_ioctl_check_extension(long ext)
|
|||
break;
|
||||
}
|
||||
return r;
|
||||
|
||||
}
|
||||
|
||||
int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
|
||||
|
|
@ -684,7 +922,7 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
|
|||
vcpu->arch.lo = regs->lo;
|
||||
vcpu->arch.pc = regs->pc;
|
||||
|
||||
return kvm_mips_callbacks->vcpu_ioctl_set_regs(vcpu, regs);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
|
||||
|
|
@ -698,7 +936,7 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
|
|||
regs->lo = vcpu->arch.lo;
|
||||
regs->pc = vcpu->arch.pc;
|
||||
|
||||
return kvm_mips_callbacks->vcpu_ioctl_get_regs(vcpu, regs);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void kvm_mips_comparecount_func(unsigned long data)
|
||||
|
|
|
|||
|
|
@ -345,54 +345,6 @@ static int kvm_trap_emul_handle_break(struct kvm_vcpu *vcpu)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
kvm_trap_emul_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
|
||||
{
|
||||
struct mips_coproc *cop0 = vcpu->arch.cop0;
|
||||
|
||||
kvm_write_c0_guest_index(cop0, regs->cp0reg[MIPS_CP0_TLB_INDEX][0]);
|
||||
kvm_write_c0_guest_context(cop0, regs->cp0reg[MIPS_CP0_TLB_CONTEXT][0]);
|
||||
kvm_write_c0_guest_badvaddr(cop0, regs->cp0reg[MIPS_CP0_BAD_VADDR][0]);
|
||||
kvm_write_c0_guest_entryhi(cop0, regs->cp0reg[MIPS_CP0_TLB_HI][0]);
|
||||
kvm_write_c0_guest_epc(cop0, regs->cp0reg[MIPS_CP0_EXC_PC][0]);
|
||||
|
||||
kvm_write_c0_guest_status(cop0, regs->cp0reg[MIPS_CP0_STATUS][0]);
|
||||
kvm_write_c0_guest_cause(cop0, regs->cp0reg[MIPS_CP0_CAUSE][0]);
|
||||
kvm_write_c0_guest_pagemask(cop0,
|
||||
regs->cp0reg[MIPS_CP0_TLB_PG_MASK][0]);
|
||||
kvm_write_c0_guest_wired(cop0, regs->cp0reg[MIPS_CP0_TLB_WIRED][0]);
|
||||
kvm_write_c0_guest_errorepc(cop0, regs->cp0reg[MIPS_CP0_ERROR_PC][0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
kvm_trap_emul_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
|
||||
{
|
||||
struct mips_coproc *cop0 = vcpu->arch.cop0;
|
||||
|
||||
regs->cp0reg[MIPS_CP0_TLB_INDEX][0] = kvm_read_c0_guest_index(cop0);
|
||||
regs->cp0reg[MIPS_CP0_TLB_CONTEXT][0] = kvm_read_c0_guest_context(cop0);
|
||||
regs->cp0reg[MIPS_CP0_BAD_VADDR][0] = kvm_read_c0_guest_badvaddr(cop0);
|
||||
regs->cp0reg[MIPS_CP0_TLB_HI][0] = kvm_read_c0_guest_entryhi(cop0);
|
||||
regs->cp0reg[MIPS_CP0_EXC_PC][0] = kvm_read_c0_guest_epc(cop0);
|
||||
|
||||
regs->cp0reg[MIPS_CP0_STATUS][0] = kvm_read_c0_guest_status(cop0);
|
||||
regs->cp0reg[MIPS_CP0_CAUSE][0] = kvm_read_c0_guest_cause(cop0);
|
||||
regs->cp0reg[MIPS_CP0_TLB_PG_MASK][0] =
|
||||
kvm_read_c0_guest_pagemask(cop0);
|
||||
regs->cp0reg[MIPS_CP0_TLB_WIRED][0] = kvm_read_c0_guest_wired(cop0);
|
||||
regs->cp0reg[MIPS_CP0_ERROR_PC][0] = kvm_read_c0_guest_errorepc(cop0);
|
||||
|
||||
regs->cp0reg[MIPS_CP0_CONFIG][0] = kvm_read_c0_guest_config(cop0);
|
||||
regs->cp0reg[MIPS_CP0_CONFIG][1] = kvm_read_c0_guest_config1(cop0);
|
||||
regs->cp0reg[MIPS_CP0_CONFIG][2] = kvm_read_c0_guest_config2(cop0);
|
||||
regs->cp0reg[MIPS_CP0_CONFIG][3] = kvm_read_c0_guest_config3(cop0);
|
||||
regs->cp0reg[MIPS_CP0_CONFIG][7] = kvm_read_c0_guest_config7(cop0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int kvm_trap_emul_vm_init(struct kvm *kvm)
|
||||
{
|
||||
return 0;
|
||||
|
|
@ -471,8 +423,6 @@ static struct kvm_mips_callbacks kvm_trap_emul_callbacks = {
|
|||
.dequeue_io_int = kvm_mips_dequeue_io_int_cb,
|
||||
.irq_deliver = kvm_mips_irq_deliver_cb,
|
||||
.irq_clear = kvm_mips_irq_clear_cb,
|
||||
.vcpu_ioctl_get_regs = kvm_trap_emul_ioctl_get_regs,
|
||||
.vcpu_ioctl_set_regs = kvm_trap_emul_ioctl_set_regs,
|
||||
};
|
||||
|
||||
int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks)
|
||||
|
|
|
|||
Loading…
Reference in a new issue