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[MIPS] Fix Cobalt PCI cache line sizes

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Peter Horton 2006-01-29 21:33:48 +00:00 committed by Ralf Baechle
parent c315a2b5fe
commit 52378445da
1 changed files with 2 additions and 2 deletions
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4
arch/mips/pci/fixup-cobalt.c
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@ -52,7 +52,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
if (lt < 64)
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
@ -69,7 +69,7 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
* host bridge.
*/
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
/*
* The code described by the comment below has been removed