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clk: qcom: clock-cpu-8939: Re-org cpu clock code for spm pll management 

To support SPM pll management cpu ops are required to be added which needs
re-organization of the code.

SPM child node probe is required for the spm event management to be handled
for the SR2/HF PLL of C0/C1/CCI.

Also make the corresponding device tree changes for the clock name changes
which are added to accommodate the new clock code.

Change-Id: I08e7a7ff367c0ae8ae71f954f2c91858b1e9c386
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2015-07-23 18:01:59 +05:30 committed by Gerrit - the friendly Code Review server
parent 5379cba703
commit 526012c282
8 changed files with 265 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/msm/clock-controller.txt
View File

@ -18,6 +18,7 @@ Required properties:
"qcom,gcc-8994"
"qcom,gcc-8994v2"
"qcom,gcc-8952"
"qcom,gcc-spm-8952"
"qcom,gcc-8976"
"qcom,gcc-fsm9010"
"qcom,rpmcc-8994"

18
arch/arm/boot/dts/qcom/msm8939-pm.dtsi
View File

@ -563,15 +563,15 @@
"cpu0_clk", "cpu1_clk", "cpu2_clk",
"cpu3_clk", "cpu4_clk", "cpu5_clk",
"cpu6_clk", "cpu7_clk", "l2_clk";
clocks = <&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_lc>,
<&clock_cpu clk_a53ssmux_lc>,
<&clock_cpu clk_a53ssmux_lc>,
<&clock_cpu clk_a53ssmux_lc>,
<&clock_cpu clk_a53ssmux_cci>;
clocks = <&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_cci_clk>;
qcom,tz-flushes-cache;
};

20
arch/arm/boot/dts/qcom/msm8939.dtsi
View File

@ -219,7 +219,7 @@
cci_cache: qcom,cci {
compatible = "devfreq-simple-dev";
clock-names = "devfreq_clk";
clocks = <&clock_cpu clk_a53ssmux_cci>;
clocks = <&clock_cpu clk_cci_clk>;
governor = "cpufreq";
freq-tbl-khz =
< 200000 >,
@ -330,15 +330,15 @@
clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",
"cpu3_clk", "cpu4_clk", "cpu5_clk",
"cpu6_clk", "cpu7_clk";
clocks = <&clock_cpu clk_a53ssmux_cci>,
<&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_lc>,
<&clock_cpu clk_a53ssmux_lc>,
<&clock_cpu clk_a53ssmux_lc>,
<&clock_cpu clk_a53ssmux_lc>;
clocks = <&clock_cpu clk_cci_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>;
qcom,governor-per-policy;

20
arch/arm/boot/dts/qcom/msm8952.dtsi
View File

@ -301,7 +301,7 @@
cci_cache: qcom,cci {
compatible = "devfreq-simple-dev";
clock-names = "devfreq_clk";
clocks = <&clock_cpu clk_a53ssmux_cci>;
clocks = <&clock_cpu clk_cci_clk>;
governor = "cpufreq";
freq-tbl-khz =
< 200000 >,
@ -397,15 +397,15 @@
clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",
"cpu3_clk", "cpu4_clk", "cpu5_clk",
"cpu6_clk", "cpu7_clk";
clocks = <&clock_cpu clk_a53ssmux_cci>,
<&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_bc>,
<&clock_cpu clk_a53ssmux_lc>,
<&clock_cpu clk_a53ssmux_lc>,
<&clock_cpu clk_a53ssmux_lc>,
<&clock_cpu clk_a53ssmux_lc>;
clocks = <&clock_cpu clk_cci_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>;
qcom,governor-per-policy;

156
drivers/clk/qcom/clock-cpu-8939.c
View File

@ -24,6 +24,7 @@
#include <linux/msm-bus.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/pm_qos.h>
#include <linux/regulator/consumer.h>
#include <linux/of.h>
#include <linux/clk/msm-clock-generic.h>
@ -46,6 +47,14 @@ enum {
const char *mux_names[] = { "c1", "c0", "cci"};
struct cpu_clk_8939 {
u32 cpu_reg_mask;
cpumask_t cpumask;
bool hw_low_power_ctrl;
struct pm_qos_request req;
struct clk c;
};
static struct mux_div_clk a53ssmux_bc = {
.ops = &rcg_mux_div_ops,
.safe_freq = 400000000,
@ -57,7 +66,6 @@ static struct mux_div_clk a53ssmux_bc = {
.c = {
.dbg_name = "a53ssmux_bc",
.ops = &clk_ops_mux_div_clk,
.vdd_class = &vdd_cpu_bc,
CLK_INIT(a53ssmux_bc.c),
},
.parents = (struct clk_src[8]) {},
@ -77,7 +85,6 @@ static struct mux_div_clk a53ssmux_lc = {
.c = {
.dbg_name = "a53ssmux_lc",
.ops = &clk_ops_mux_div_clk,
.vdd_class = &vdd_cpu_lc,
CLK_INIT(a53ssmux_lc.c),
},
.parents = (struct clk_src[8]) {},
@ -97,7 +104,6 @@ static struct mux_div_clk a53ssmux_cci = {
.c = {
.dbg_name = "a53ssmux_cci",
.ops = &clk_ops_mux_div_clk,
.vdd_class = &vdd_cpu_cci,
CLK_INIT(a53ssmux_cci.c),
},
.parents = (struct clk_src[8]) {},
@ -106,14 +112,118 @@ static struct mux_div_clk a53ssmux_cci = {
.src_shift = 8,
};
static void do_nothing(void *unused) { }
#define CPU_LATENCY_NO_L2_PC_US (300)
static inline struct cpu_clk_8939 *to_cpu_clk_8939(struct clk *c)
{
return container_of(c, struct cpu_clk_8939, c);
}
static enum handoff cpu_clk_8939_handoff(struct clk *c)
{
c->rate = clk_get_rate(c->parent);
return HANDOFF_DISABLED_CLK;
}
static long cpu_clk_8939_round_rate(struct clk *c, unsigned long rate)
{
return clk_round_rate(c->parent, rate);
}
static int cpu_clk_8939_set_rate(struct clk *c, unsigned long rate)
{
int ret = 0;
struct cpu_clk_8939 *cpuclk = to_cpu_clk_8939(c);
bool hw_low_power_ctrl = cpuclk->hw_low_power_ctrl;
if (hw_low_power_ctrl) {
memset(&cpuclk->req, 0, sizeof(cpuclk->req));
cpumask_copy(&cpuclk->req.cpus_affine,
(const struct cpumask *)&cpuclk->cpumask);
cpuclk->req.type = PM_QOS_REQ_AFFINE_CORES;
pm_qos_add_request(&cpuclk->req, PM_QOS_CPU_DMA_LATENCY,
CPU_LATENCY_NO_L2_PC_US);
smp_call_function_any(&cpuclk->cpumask, do_nothing,
NULL, 1);
}
ret = clk_set_rate(c->parent, rate);
if (hw_low_power_ctrl)
pm_qos_remove_request(&cpuclk->req);
return ret;
}
static struct clk_ops clk_ops_cpu = {
.set_rate = cpu_clk_8939_set_rate,
.round_rate = cpu_clk_8939_round_rate,
.handoff = cpu_clk_8939_handoff,
};
static struct cpu_clk_8939 a53_bc_clk = {
.cpu_reg_mask = 0x3,
.c = {
.parent = &a53ssmux_bc.c,
.ops = &clk_ops_cpu,
.vdd_class = &vdd_cpu_bc,
.dbg_name = "a53_bc_clk",
CLK_INIT(a53_bc_clk.c),
},
};
static struct cpu_clk_8939 a53_lc_clk = {
.cpu_reg_mask = 0x103,
.c = {
.parent = &a53ssmux_lc.c,
.ops = &clk_ops_cpu,
.vdd_class = &vdd_cpu_lc,
.dbg_name = "a53_lc_clk",
CLK_INIT(a53_lc_clk.c),
},
};
static struct cpu_clk_8939 cci_clk = {
.c = {
.parent = &a53ssmux_cci.c,
.ops = &clk_ops_cpu,
.vdd_class = &vdd_cpu_cci,
.dbg_name = "cci_clk",
CLK_INIT(cci_clk.c),
},
};
static struct clk_lookup cpu_clocks_8939[] = {
CLK_LIST(a53ssmux_lc),
CLK_LIST(a53ssmux_bc),
CLK_LIST(a53ssmux_cci),
CLK_LIST(a53_bc_clk),
CLK_LIST(a53_lc_clk),
CLK_LIST(cci_clk),
};
static struct mux_div_clk *a53ssmux[] = {&a53ssmux_bc,
&a53ssmux_lc, &a53ssmux_cci};
static struct cpu_clk_8939 *cpuclk[] = { &a53_bc_clk, &a53_lc_clk, &cci_clk};
static struct clk *logical_cpu_to_clk(int cpu)
{
struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
u32 reg;
/* CPU 0/1/2/3 --> a53_bc_clk and mask = 0x103
* CPU 4/5/6/7 --> a53_lc_clk and mask = 0x3
*/
if (cpu_node && !of_property_read_u32(cpu_node, "reg", &reg)) {
if ((reg | a53_bc_clk.cpu_reg_mask) == a53_bc_clk.cpu_reg_mask)
return &a53_lc_clk.c;
if ((reg | a53_lc_clk.cpu_reg_mask) == a53_lc_clk.cpu_reg_mask)
return &a53_bc_clk.c;
}
return NULL;
}
static int of_get_fmax_vdd_class(struct platform_device *pdev, struct clk *c,
char *prop_name)
@ -357,7 +467,7 @@ static int cpu_parse_devicetree(struct platform_device *pdev, int mux_id)
dev_err(&pdev->dev, "unable to get regulator\n");
return PTR_ERR(regulator);
}
a53ssmux[mux_id]->c.vdd_class->regulator[0] = regulator;
cpuclk[mux_id]->c.vdd_class->regulator[0] = regulator;
rc = of_get_clk_src(pdev, a53ssmux[mux_id]->parents, mux_id);
if (IS_ERR_VALUE(rc))
@ -391,15 +501,15 @@ static int clock_8939_pm_event(struct notifier_block *this,
switch (event) {
case PM_POST_HIBERNATION:
case PM_POST_SUSPEND:
clk_unprepare(&a53ssmux_lc.c);
clk_unprepare(&a53ssmux_bc.c);
clk_unprepare(&a53ssmux_cci.c);
clk_unprepare(&a53_lc_clk.c);
clk_unprepare(&a53_bc_clk.c);
clk_unprepare(&cci_clk.c);
break;
case PM_HIBERNATION_PREPARE:
case PM_SUSPEND_PREPARE:
clk_prepare(&a53ssmux_lc.c);
clk_prepare(&a53ssmux_bc.c);
clk_prepare(&a53ssmux_cci.c);
clk_prepare(&a53_lc_clk.c);
clk_prepare(&a53_bc_clk.c);
clk_prepare(&cci_clk.c);
break;
default:
break;
@ -427,7 +537,7 @@ static int clock_a53_probe(struct platform_device *pdev)
"qcom,speed%d-bin-v%d-%s",
speed_bin, version, mux_names[mux_id]);
rc = of_get_fmax_vdd_class(pdev, &a53ssmux[mux_id]->c,
rc = of_get_fmax_vdd_class(pdev, &cpuclk[mux_id]->c,
prop_name);
if (rc) {
/* Fall back to most conservative PVS table */
@ -436,7 +546,7 @@ static int clock_a53_probe(struct platform_device *pdev)
snprintf(prop_name, ARRAY_SIZE(prop_name),
"qcom,speed0-bin-v0-%s", mux_names[mux_id]);
rc = of_get_fmax_vdd_class(pdev, &a53ssmux[mux_id]->c,
rc = of_get_fmax_vdd_class(pdev, &cpuclk[mux_id]->c,
prop_name);
if (rc) {
dev_err(&pdev->dev,
@ -454,14 +564,13 @@ static int clock_a53_probe(struct platform_device *pdev)
return rc;
}
rate = clk_get_rate(&a53ssmux[A53SS_MUX_CCI]->c);
clk_set_rate(&a53ssmux[A53SS_MUX_CCI]->c, rate);
rate = clk_get_rate(&cci_clk.c);
clk_set_rate(&cci_clk.c, rate);
for (mux_id = 0; mux_id < A53SS_MUX_CCI; mux_id++) {
/* Force a PLL reconfiguration */
config_pll(mux_id);
}
/*
* We don't want the CPU clocks to be turned off at late init
* if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
@ -471,15 +580,26 @@ static int clock_a53_probe(struct platform_device *pdev)
*/
get_online_cpus();
for_each_online_cpu(cpu) {
WARN(clk_prepare_enable(&a53ssmux[cpu/4]->c),
WARN(clk_prepare_enable(&cpuclk[cpu/4]->c),
"Unable to turn on CPU clock");
clk_prepare_enable(&a53ssmux_cci.c);
clk_prepare_enable(&cci_clk.c);
}
put_online_cpus();
register_pm_notifier(&clock_8939_pm_notifier);
cpu_clock_8939_dev = pdev;
for_each_possible_cpu(cpu) {
if (logical_cpu_to_clk(cpu) == &a53_bc_clk.c)
cpumask_set_cpu(cpu, &a53_bc_clk.cpumask);
if (logical_cpu_to_clk(cpu) == &a53_lc_clk.c)
cpumask_set_cpu(cpu, &a53_lc_clk.cpumask);
}
a53_lc_clk.hw_low_power_ctrl = true;
a53_bc_clk.hw_low_power_ctrl = true;
register_pm_notifier(&clock_8939_pm_notifier);
return 0;
}

88
drivers/clk/qcom/clock-gcc-8952.c
View File

@ -20,6 +20,7 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <soc/qcom/clock-local2.h>
#include <soc/qcom/clock-pll.h>
#include <soc/qcom/clock-alpha-pll.h>
@ -265,6 +266,10 @@ static struct pll_clk a53ss_cci_pll = {
.main_output_mask = BIT(0),
},
.base = &virt_bases[APCS_CCI_PLL_BASE],
.spm_ctrl = {
.offset = 0x40,
.event_bit = 0x0,
},
.c = {
.parent = &xo_a_clk_src.c,
.dbg_name = "a53ss_cci_pll",
@ -311,6 +316,10 @@ static struct pll_clk a53ss_c0_pll = {
.main_output_mask = BIT(0),
},
.base = &virt_bases[APCS_C0_PLL_BASE],
.spm_ctrl = {
.offset = 0x50,
.event_bit = 0x4,
},
.c = {
.parent = &xo_a_clk_src.c,
.dbg_name = "a53ss_c0_pll",
@ -366,6 +375,10 @@ static struct pll_clk a53ss_c1_pll = {
.main_output_mask = BIT(0),
},
.base = &virt_bases[APCS_C1_PLL_BASE],
.spm_ctrl = {
.offset = 0x50,
.event_bit = 0x4,
},
.c = {
.parent = &xo_a_clk_src.c,
.dbg_name = "a53ss_c1_pll",
@ -3569,6 +3582,10 @@ static int msm_gcc_probe(struct platform_device *pdev)
regval |= CLKFLAG_SLEEP_CYCLES << 4;
writel_relaxed(regval, GCC_REG_BASE(OXILI_GMEM_CBCR));
ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
if (ret)
return ret;
dev_info(&pdev->dev, "Registered GCC clocks\n");
return 0;
@ -3588,9 +3605,78 @@ static struct platform_driver msm_clock_gcc_driver = {
},
};
static int msm_gcc_spm_probe(struct platform_device *pdev)
{
struct resource *res = NULL;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c0_base");
if (!res) {
dev_err(&pdev->dev, "SPM register base not defined for c0\n");
return -ENOMEM;
}
a53ss_c0_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!a53ss_c0_pll.spm_ctrl.spm_base) {
dev_err(&pdev->dev, "Failed to ioremap c0 spm registers\n");
return -ENOMEM;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c1_base");
if (!res) {
dev_err(&pdev->dev, "SPM register base not defined for c1\n");
return -ENOMEM;
}
a53ss_c1_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!a53ss_c1_pll.spm_ctrl.spm_base) {
dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");
return -ENOMEM;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"spm_cci_base");
if (!res) {
dev_err(&pdev->dev, "SPM register base not defined for cci\n");
return -ENOMEM;
}
a53ss_cci_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!a53ss_cci_pll.spm_ctrl.spm_base) {
dev_err(&pdev->dev, "Failed to ioremap cci spm registers\n");
return -ENOMEM;
}
dev_info(&pdev->dev, "Registered GCC SPM clocks\n");
return 0;
}
static struct of_device_id msm_clock_spm_match_table[] = {
{ .compatible = "qcom,gcc-spm-8952" },
{}
};
static struct platform_driver msm_clock_spm_driver = {
.probe = msm_gcc_spm_probe,
.driver = {
.name = "qcom,gcc-spm-8952",
.of_match_table = msm_clock_spm_match_table,
.owner = THIS_MODULE,
},
};
static int __init msm_gcc_init(void)
{
return platform_driver_register(&msm_clock_gcc_driver);
int ret;
ret = platform_driver_register(&msm_clock_gcc_driver);
if (!ret)
ret = platform_driver_register(&msm_clock_spm_driver);
return ret;
}
static struct clk_lookup msm_clocks_measure[] = {

3
include/dt-bindings/clock/msm-clocks-8952.h
View File

@ -299,8 +299,11 @@
#define clk_cci_m_clk 0xec7e8afc
#define clk_a53ssmux_lc 0x71a9377b
#define clk_a53_lc_clk 0xc69f0878
#define clk_a53ssmux_bc 0xb5983c42
#define clk_a53_bc_clk 0xcf28e63a
#define clk_a53ssmux_cci 0x15560bd5
#define clk_cci_clk 0x96854074
#define clk_audio_ap_clk 0x312ac429
#define clk_audio_pmi_clk 0xb7ba2274

11
include/dt-bindings/clock/msm-cpu-clocks-8939.h
View File

@ -1,5 +1,5 @@
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -14,8 +14,11 @@
#ifndef __MSM_CLOCK_CPU_8939_H
#define __MSM_CLOCK_CPU_8939_H
#define clk_a53ssmux_lc 0x71a9377b
#define clk_a53ssmux_bc 0xb5983c42
#define clk_a53ssmux_cci 0x15560bd5
#define clk_a53ssmux_lc 0x71a9377b
#define clk_a53_lc_clk 0xc69f0878
#define clk_a53ssmux_bc 0xb5983c42
#define clk_a53_bc_clk 0xcf28e63a
#define clk_a53ssmux_cci 0x15560bd5
#define clk_cci_clk 0x96854074
#endif