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[POWERPC] Improve robustness of the UIC cascade handler

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At present the cascade interrupt handler for the UIC (interrupt
controller on 4xx embedded chips) will misbehave badly if it is called
spuriously - that is if the handler is invoked when no interrupts are
asserted in the child UIC.

Although spurious interrupts shouldn't happen, it's good to behave
robustly if they do.  This patch does so by checking for and ignoring
spurious interrupts.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
David Gibson 2007-08-14 13:52:42 +10:00 committed by Paul Mackerras
parent 868afce21f
commit 553fdff633
1 changed files with 3 additions and 0 deletions
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3
arch/powerpc/sysdev/uic.c
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@ -266,6 +266,9 @@ irqreturn_t uic_cascade(int virq, void *data)
int subvirq;
msr = mfdcr(uic->dcrbase + UIC_MSR);
if (!msr) /* spurious interrupt */
return IRQ_HANDLED;
src = 32 - ffs(msr);
subvirq = irq_linear_revmap(uic->irqhost, src);