Piteball/android_kernel_samsung_msm8976
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Merge branch 'next/cleanup-samsung' into next/cleanup-samsung-2

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This commit is contained in:
Kukjin Kim 2012-11-07 08:11:21 +09:00
commit 55b85967f4
8 changed files with 6 additions and 63 deletions
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5
arch/arm/mach-exynos/clock-exynos4.c
View file

@ -611,11 +611,6 @@ static struct clk exynos4_init_clocks_off[] = {
.devname = "exynos4210-spi.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "iis",
.devname = "samsung-i2s.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "iis",
.devname = "samsung-i2s.1",

31
arch/arm/mach-exynos/common.c
View file

@ -63,7 +63,7 @@ static void exynos4_map_io(void);
static void exynos5_map_io(void);
static void exynos4_init_clocks(int xtal);
static void exynos5_init_clocks(int xtal);
static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
static int exynos_init(void);
static struct cpu_table cpu_ids[] __initdata = {
@ -72,7 +72,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos_init_uarts,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4210,
}, {
@ -80,7 +80,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos_init_uarts,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4212,
}, {
@ -88,7 +88,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos_init_uarts,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4412,
}, {
@ -96,7 +96,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
.init_clocks = exynos5_init_clocks,
.init_uarts = exynos_init_uarts,
.init = exynos_init,
.name = name_exynos5250,
},
@ -256,26 +255,11 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(EXYNOS5_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_CPU,
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
.length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_DIST,
.pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
@ -727,7 +711,7 @@ static int __init exynos_init(void)
/* uart registration process */
static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
struct s3c2410_uartcfg *tcfg = cfg;
u32 ucnt;
@ -735,10 +719,7 @@ static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
tcfg->has_fracval = 1;
if (soc_is_exynos5250())
s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
else
s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
}
static void __iomem *exynos_eint_base;

24
arch/arm/mach-exynos/dev-uart.c
View file

@ -52,27 +52,3 @@ struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
.nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
},
};
EXYNOS_UART_RESOURCE(5, 0)
EXYNOS_UART_RESOURCE(5, 1)
EXYNOS_UART_RESOURCE(5, 2)
EXYNOS_UART_RESOURCE(5, 3)
struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
[0] = {
.resources = exynos5_uart0_resource,
.nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
},
[1] = {
.resources = exynos5_uart1_resource,
.nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
},
[2] = {
.resources = exynos5_uart2_resource,
.nr_resources = ARRAY_SIZE(exynos5_uart2_resource),
},
[3] = {
.resources = exynos5_uart3_resource,
.nr_resources = ARRAY_SIZE(exynos5_uart3_resource),
},
};

5
arch/arm/mach-exynos/include/mach/irqs.h
View file

@ -259,11 +259,6 @@
#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
#define EXYNOS5_IRQ_UART0 IRQ_SPI(51)
#define EXYNOS5_IRQ_UART1 IRQ_SPI(52)
#define EXYNOS5_IRQ_UART2 IRQ_SPI(53)
#define EXYNOS5_IRQ_UART3 IRQ_SPI(54)
#define EXYNOS5_IRQ_UART4 IRQ_SPI(55)
#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)

1
arch/arm/mach-exynos/include/mach/map.h
View file

@ -279,7 +279,6 @@
#define EXYNOS5_PA_UART1 0x12C10000
#define EXYNOS5_PA_UART2 0x12C20000
#define EXYNOS5_PA_UART3 0x12C30000
#define EXYNOS5_SZ_UART SZ_256
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))

1
arch/arm/mach-exynos/mach-nuri.c
View file

@ -113,7 +113,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_ERASE),
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
};

1
arch/arm/mach-exynos/mach-universal_c210.c
View file

@ -754,7 +754,6 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
.max_width = 8,
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
};

1
arch/arm/mach-s5pv210/mach-goni.c
View file

@ -774,7 +774,6 @@ static void __init goni_pmic_init(void)
/* MoviNAND */
static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
.max_width = 4,
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
};