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clk: qcom: 8976: Add new compatible string to support MSM8976 v1.1 

Clock changes for MSM8976 v1.1 supports new frequency table for SDCC clock
and PCLK1/BYTE1 clock.

Change-Id: If16533206511c64db4a7b7d5388e3a98f1a80677
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2015-09-04 14:40:12 +05:30
parent c184d99501
commit 5b433bc48e
4 changed files with 161 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/msm/clock-controller.txt
View File

@ -20,6 +20,7 @@ Required properties:
"qcom,gcc-8952"
"qcom,gcc-spm-8952"
"qcom,gcc-8976"
"qcom,gcc-8976-v1"
"qcom,gcc-fsm9010"
"qcom,rpmcc-8994"
"qcom,rpmcc-8992"
@ -39,6 +40,7 @@ Required properties:
"qcom,gcc-mdss-8916"
"qcom,gcc-mdss-8952"
"qcom,gcc-mdss-8976"
"qcom,gcc-mdss-8976-v1"
"qcom,mmsscc-8994v2"
"qcom,mmsscc-8994"
"qcom,mmsscc-8992"

194
drivers/clk/qcom/clock-gcc-8976.c
View File

@ -227,6 +227,7 @@ DEFINE_EXT_CLK(gpll0_out_m_clk_src, &gpll0_clk_src.c);
DEFINE_EXT_CLK(gpll0_out_mdp_clk_src, &gpll0_clk_src.c);
DEFINE_EXT_CLK(gpll2_aux_clk_src, &gpll2_clk_src.c);
DEFINE_EXT_CLK(gpll2_gfx3d_clk_src, &gpll2_clk_src.c);
DEFINE_EXT_CLK(gpll2_out_clk_src, &gpll2_clk_src.c);
DEFINE_EXT_CLK(gpll3_aux_clk_src, &gpll3_clk_src.c);
DEFINE_EXT_CLK(gpll4_aux_clk_src, &gpll4_clk_src.c);
DEFINE_EXT_CLK(gpll4_gfx3d_clk_src, &gpll4_clk_src.c);
@ -1070,38 +1071,76 @@ static struct rcg_clk gp3_clk_src = {
},
};
DEFINE_EXT_CLK(ext_byte0_clk_src, NULL);
DEFINE_EXT_CLK(ext_byte1_clk_src, NULL);
static struct clk_freq_tbl ftbl_byte0_clk_src[] = {
{
.div_src_val = BVAL(10, 8, dsi0_phypll_mm_source_val),
.div_src_val = BVAL(10, 8, dsi0_phypll_mm_source_val),
.src_clk = &ext_byte0_clk_src.c,
.freq_hz = 0,
},
F_END
};
static struct rcg_clk byte0_clk_src = {
.cmd_rcgr_reg = BYTE0_CMD_RCGR,
.set_rate = set_rate_hid,
.current_freq = ftbl_byte0_clk_src,
.freq_tbl = ftbl_byte0_clk_src,
.base = &virt_bases[MDSS_BASE],
.c = {
.dbg_name = "byte0_clk_src",
.ops = &clk_ops_byte,
.ops = &clk_ops_byte_multiparent,
.flags = CLKFLAG_NO_RATE_CACHE,
VDD_DIG_FMAX_MAP3(LOWER, 125000000, LOW, 161250000,
NOMINAL, 187500000),
NOMINAL, 187500000),
CLK_INIT(byte0_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_byte1_clk_src[] = {
{
.div_src_val = BVAL(10, 8, dsi1_phypll_mm_source_val),
.div_src_val = BVAL(10, 8, dsi1_phypll_mm_source_val)
| BVAL(4, 0, 0),
.src_clk = &ext_byte1_clk_src.c,
.freq_hz = 0,
},
F_END
};
static struct clk_freq_tbl ftbl_byte1_v1_clk_src[] = {
{
.div_src_val = BVAL(10, 8, xo_source_val)
| BVAL(4, 0, 0),
.src_clk = &xo_clk_src.c,
.freq_hz = 0,
},
{
.div_src_val = BVAL(10, 8, dsi1_phypll_mm_source_val)
| BVAL(4, 0, 0),
.src_clk = &ext_byte1_clk_src.c,
.freq_hz = 0,
},
{
.div_src_val = BVAL(10, 8, dsi0_phypll_clk_mm_source_val),
.src_clk = &ext_byte0_clk_src.c,
.freq_hz = 0,
},
F_END
};
static struct rcg_clk byte1_clk_src = {
.cmd_rcgr_reg = BYTE1_CMD_RCGR,
.current_freq = ftbl_byte1_clk_src,
.base = &virt_bases[MDSS_BASE],
.cmd_rcgr_reg = BYTE1_CMD_RCGR,
.set_rate = set_rate_hid,
.current_freq = ftbl_byte1_clk_src,
.freq_tbl = ftbl_byte1_clk_src,
.base = &virt_bases[MDSS_BASE],
.c = {
.dbg_name = "byte1_clk_src",
.ops = &clk_ops_byte,
.ops = &clk_ops_byte_multiparent,
.flags = CLKFLAG_NO_RATE_CACHE,
VDD_DIG_FMAX_MAP3(LOWER, 125000000, LOW, 161250000,
NOMINAL, 187500000),
NOMINAL, 187500000),
CLK_INIT(byte1_clk_src.c),
},
};
@ -1173,38 +1212,78 @@ static struct rcg_clk mdp_clk_src = {
},
};
DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);
DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL);
static struct clk_freq_tbl ftbl_pclk0_clk_src[] = {
{
.div_src_val = BVAL(10, 8, dsi0_phypll_mm_source_val),
},
.div_src_val = BVAL(10, 8, dsi0_phypll_mm_source_val)
| BVAL(4, 0, 0),
.src_clk = &ext_pclk0_clk_src.c,
.freq_hz = 0,
},
F_END
};
static struct rcg_clk pclk0_clk_src = {
.cmd_rcgr_reg = PCLK0_CMD_RCGR,
.set_rate = set_rate_mnd,
.current_freq = ftbl_pclk0_clk_src,
.freq_tbl = ftbl_pclk0_clk_src,
.base = &virt_bases[MDSS_BASE],
.c = {
.dbg_name = "pclk0_clk_src",
.ops = &clk_ops_byte,
.ops = &clk_ops_pixel_multiparent,
.flags = CLKFLAG_NO_RATE_CACHE,
VDD_DIG_FMAX_MAP3(LOWER, 166670000, LOW, 215000000,
NOMINAL, 250000000),
NOMINAL, 250000000),
CLK_INIT(pclk0_clk_src.c),
},
};
static struct clk_freq_tbl ftbl_pclk1_clk_src[] = {
{
.div_src_val = BVAL(10, 8, dsi1_phypll_mm_source_val),
},
.div_src_val = BVAL(10, 8, dsi1_phypll_mm_source_val)
| BVAL(4, 0, 0),
.src_clk = &ext_pclk1_clk_src.c,
.freq_hz = 0,
},
F_END
};
static struct clk_freq_tbl ftbl_pclk1_v1_clk_src[] = {
{
.div_src_val = BVAL(10, 8, xo_source_val)
| BVAL(4, 0, 0),
.src_clk = &xo_clk_src.c,
.freq_hz = 0,
},
{
.div_src_val = BVAL(10, 8, dsi1_phypll_mm_source_val)
| BVAL(4, 0, 0),
.src_clk = &ext_pclk1_clk_src.c,
.freq_hz = 0,
},
{
.div_src_val = BVAL(10, 8, dsi0_phypll_clk_mm_source_val)
| BVAL(4, 0, 0),
.src_clk = &ext_pclk0_clk_src.c,
.freq_hz = 0,
},
F_END
};
static struct rcg_clk pclk1_clk_src = {
.cmd_rcgr_reg = PCLK1_CMD_RCGR,
.set_rate = set_rate_mnd,
.current_freq = ftbl_pclk1_clk_src,
.freq_tbl = ftbl_pclk1_clk_src,
.base = &virt_bases[MDSS_BASE],
.c = {
.dbg_name = "pclk1_clk_src",
.ops = &clk_ops_byte,
.ops = &clk_ops_pixel_multiparent,
.flags = CLKFLAG_NO_RATE_CACHE,
VDD_DIG_FMAX_MAP3(LOWER, 166670000, LOW, 215000000,
NOMINAL, 250000000),
NOMINAL, 250000000),
CLK_INIT(pclk1_clk_src.c),
},
};
@ -1315,6 +1394,20 @@ static struct clk_freq_tbl ftbl_sdcc1_apps_clk_src[] = {
F_END
};
static struct clk_freq_tbl ftbl_sdcc1_v1_apps_clk_src[] = {
F( 144000, xo, 16, 3, 25),
F( 400000, xo, 12, 1, 4),
F( 20000000, gpll0, 10, 1, 4),
F( 25000000, gpll0, 16, 1, 2),
F( 50000000, gpll0, 16, 0, 0),
F( 100000000, gpll0, 8, 0, 0),
F( 177777778, gpll0, 4.5, 0, 0),
F( 200000000, gpll0, 4, 0, 0),
F( 186400000, gpll2_out, 5, 0, 0),
F( 372800000, gpll2_out, 2.5, 0, 0),
F_END
};
static struct rcg_clk sdcc1_apps_clk_src = {
.cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
.set_rate = set_rate_mnd,
@ -2358,6 +2451,7 @@ static struct branch_clk gcc_mdss_byte0_clk = {
.dbg_name = "gcc_mdss_byte0_clk",
.parent = &byte0_clk_src.c,
.ops = &clk_ops_branch,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(gcc_mdss_byte0_clk.c),
},
};
@ -2370,6 +2464,7 @@ static struct branch_clk gcc_mdss_byte1_clk = {
.dbg_name = "gcc_mdss_byte1_clk",
.parent = &byte1_clk_src.c,
.ops = &clk_ops_branch,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(gcc_mdss_byte1_clk.c),
},
};
@ -2418,6 +2513,7 @@ static struct branch_clk gcc_mdss_pclk0_clk = {
.dbg_name = "gcc_mdss_pclk0_clk",
.parent = &pclk0_clk_src.c,
.ops = &clk_ops_branch,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(gcc_mdss_pclk0_clk.c),
},
};
@ -2430,6 +2526,7 @@ static struct branch_clk gcc_mdss_pclk1_clk = {
.dbg_name = "gcc_mdss_pclk1_clk",
.parent = &pclk1_clk_src.c,
.ops = &clk_ops_branch,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(gcc_mdss_pclk1_clk.c),
},
};
@ -3531,11 +3628,15 @@ static int msm_gcc_probe(struct platform_device *pdev)
struct resource *res;
int ret;
u32 regval;
bool compat_bin = false;
ret = vote_bimc(&bimc_clk, INT_MAX);
if (ret < 0)
return ret;
compat_bin = of_device_is_compatible(pdev->dev.of_node,
"qcom,gcc-8976-v1");
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
if (!res) {
dev_err(&pdev->dev, "Register base not defined\n");
@ -3562,6 +3663,9 @@ static int msm_gcc_probe(struct platform_device *pdev)
regval |= BIT(0);
writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
if (compat_bin)
sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_v1_apps_clk_src;
ret = of_msm_clock_register(pdev->dev.of_node,
msm_clocks_lookup,
ARRAY_SIZE(msm_clocks_lookup));
@ -3607,6 +3711,7 @@ static int msm_gcc_probe(struct platform_device *pdev)
static struct of_device_id msm_clock_gcc_match_table[] = {
{ .compatible = "qcom,gcc-8976" },
{ .compatible = "qcom,gcc-8976-v1" },
{},
};
@ -3676,6 +3781,10 @@ late_initcall(msm_clock_debug_init);
/* MDSS DSI_PHY_PLL */
static struct clk_lookup msm_clocks_gcc_mdss[] = {
CLK_LIST(ext_byte0_clk_src),
CLK_LIST(ext_byte1_clk_src),
CLK_LIST(ext_pclk0_clk_src),
CLK_LIST(ext_pclk1_clk_src),
CLK_LIST(byte0_clk_src),
CLK_LIST(byte1_clk_src),
CLK_LIST(pclk0_clk_src),
@ -3688,9 +3797,13 @@ static struct clk_lookup msm_clocks_gcc_mdss[] = {
static int msm_gcc_mdss_probe(struct platform_device *pdev)
{
int counter = 0, ret = 0;
int ret = 0;
struct clk *curr_p;
struct resource *res;
bool compat_bin = false;
compat_bin = of_device_is_compatible(pdev->dev.of_node,
"qcom,gcc-mdss-8976-v1");
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
if (!res) {
@ -3705,48 +3818,46 @@ static int msm_gcc_mdss_probe(struct platform_device *pdev)
return -ENOMEM;
}
curr_p = pclk0_clk_src.c.parent = devm_clk_get(&pdev->dev, "pclk0_src");
if (compat_bin) {
pclk1_clk_src.freq_tbl = ftbl_pclk1_v1_clk_src;
byte1_clk_src.freq_tbl = ftbl_byte1_v1_clk_src;
}
curr_p = ext_pclk0_clk_src.c.parent = devm_clk_get(&pdev->dev,
"pclk0_src");
if (IS_ERR(curr_p)) {
dev_err(&pdev->dev, "Failed to get pclk0 source.\n");
return PTR_ERR(curr_p);
}
for (counter = 0; counter < (sizeof(ftbl_pclk0_clk_src)/
sizeof(struct clk_freq_tbl)); counter++)
ftbl_pclk0_clk_src[counter].src_clk = curr_p;
curr_p = pclk1_clk_src.c.parent = devm_clk_get(&pdev->dev, "pclk1_src");
curr_p = ext_pclk1_clk_src.c.parent = devm_clk_get(&pdev->dev,
"pclk1_src");
if (IS_ERR(curr_p)) {
dev_err(&pdev->dev, "Failed to get pclk1 source.\n");
ret = PTR_ERR(curr_p);
goto pclk1_fail;
}
for (counter = 0; counter < (sizeof(ftbl_pclk1_clk_src)/
sizeof(struct clk_freq_tbl)); counter++)
ftbl_pclk1_clk_src[counter].src_clk = curr_p;
curr_p = byte0_clk_src.c.parent = devm_clk_get(&pdev->dev, "byte0_src");
curr_p = ext_byte0_clk_src.c.parent = devm_clk_get(&pdev->dev,
"byte0_src");
if (IS_ERR(curr_p)) {
dev_err(&pdev->dev, "Failed to get byte0 source.\n");
ret = PTR_ERR(curr_p);
goto byte0_fail;
}
for (counter = 0; counter < (sizeof(ftbl_byte0_clk_src)/
sizeof(struct clk_freq_tbl)); counter++)
ftbl_byte0_clk_src[counter].src_clk = curr_p;
curr_p = byte1_clk_src.c.parent = devm_clk_get(&pdev->dev, "byte1_src");
curr_p = ext_byte1_clk_src.c.parent = devm_clk_get(&pdev->dev,
"byte1_src");
if (IS_ERR(curr_p)) {
dev_err(&pdev->dev, "Failed to get byte1 source.\n");
ret = PTR_ERR(curr_p);
goto byte1_fail;
}
for (counter = 0; counter < (sizeof(ftbl_byte1_clk_src)/
sizeof(struct clk_freq_tbl)); counter++)
ftbl_byte1_clk_src[counter].src_clk = curr_p;
ext_pclk0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
ext_pclk1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
ext_byte0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
ext_byte1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_gcc_mdss,
ARRAY_SIZE(msm_clocks_gcc_mdss));
@ -3757,18 +3868,19 @@ static int msm_gcc_mdss_probe(struct platform_device *pdev)
return ret;
fail:
devm_clk_put(&pdev->dev, byte1_clk_src.c.parent);
devm_clk_put(&pdev->dev, ext_byte1_clk_src.c.parent);
byte1_fail:
devm_clk_put(&pdev->dev, byte0_clk_src.c.parent);
devm_clk_put(&pdev->dev, ext_byte0_clk_src.c.parent);
byte0_fail:
devm_clk_put(&pdev->dev, pclk1_clk_src.c.parent);
devm_clk_put(&pdev->dev, ext_pclk1_clk_src.c.parent);
pclk1_fail:
devm_clk_put(&pdev->dev, pclk0_clk_src.c.parent);
devm_clk_put(&pdev->dev, ext_pclk0_clk_src.c.parent);
return ret;
}
static struct of_device_id msm_clock_mdss_match_table[] = {
{ .compatible = "qcom,gcc-mdss-8976" },
{ .compatible = "qcom,gcc-mdss-8976-v1" },
{}
};

4
include/dt-bindings/clock/msm-clocks-8976.h
View File

@ -240,7 +240,9 @@
#define clk_gp2_clk_src 0xfb1f0065
#define clk_gp3_clk_src 0x63b693d6
#define clk_byte0_clk_src 0x75cc885b
#define clk_ext_byte0_clk_src 0xfb32f31e
#define clk_byte1_clk_src 0x63c2c955
#define clk_ext_byte1_clk_src 0x585ef6d4
#define clk_esc0_clk_src 0xb41d7c38
#define clk_esc1_clk_src 0x3b0afa42
#define clk_dsi_pll0_byte_clk_src 0x44539836
@ -249,7 +251,9 @@
#define clk_dsi_pll1_pixel_clk_src 0xce233fcf
#define clk_mdp_clk_src 0x6dc1f8f1
#define clk_pclk0_clk_src 0xccac1f35
#define clk_ext_pclk0_clk_src 0x087c1612
#define clk_pclk1_clk_src 0x090f68ac
#define clk_ext_pclk1_clk_src 0x8067c5a3
#define clk_vsync_clk_src 0xecb43940
#define clk_gfx3d_clk_src 0x917f76ef
#define clk_pdm2_clk_src 0x31e494fd

2
include/dt-bindings/clock/msm-clocks-hwio-8976.h
View File

@ -285,6 +285,7 @@
/* cpp_clk_src */
#define gpll2_source_val 2
#define gpll2_out_source_val 4
#define gpll4_aux_source_val 3
#define gpll6_out_m_source_val 5
@ -316,6 +317,7 @@
#define dsi0_phypll_mm_source_val 1
#define dsi1_phypll_mm_source_val 1
#define dsi0_phypll_clk_mm_source_val 3
#define F(f, s, div, m, n) \
{ \