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crypto: Change format specifier %p to %pK 

Format specifier %p can leak kernel addresses while not valuing the
kptr_restrict system settings. When kptr_restrict is set to (1), kernel
pointers printed using the %pK format specifier will be replaced with 0's.

Change-Id: Iff8d82b12e958b938fc767bf3e8c3a3c8fc65c2a
Signed-off-by: mohamed sunfeer <msunfeer@codeaurora.org>
This commit is contained in:
mohamed sunfeer 2017-06-29 15:13:34 +05:30 committed by Gerrit - the friendly Code Review server
parent d07da7cf99
commit 67f133de2a
5 changed files with 37 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
drivers/crypto/msm/ice.c
View File

@ -361,7 +361,7 @@ static void qcom_ice_enable(struct ice_device *ice_dev)
(ICE_REV(ice_dev->ice_hw_version, MINOR) >= 1))) {
reg = qcom_ice_readl(ice_dev, QCOM_ICE_REGS_BYPASS_STATUS);
if ((reg & 0x80000000) != 0x0) {
pr_err("%s: Bypass failed for ice = %p",
pr_err("%s: Bypass failed for ice = %pK",
__func__, (void *)ice_dev);
BUG();
}
@ -386,7 +386,7 @@ static int qcom_ice_verify_ice(struct ice_device *ice_dev)
}
ice_dev->ice_hw_version = rev;
dev_info(ice_dev->pdev, "QC ICE %d.%d.%d device found @0x%p\n",
dev_info(ice_dev->pdev, "QC ICE %d.%d.%d device found @0x%pK\n",
maj_rev, min_rev, step_rev,
ice_dev->mmio);
@ -1211,7 +1211,7 @@ static void qcom_ice_debug(struct platform_device *pdev)
if (!ice_dev->is_ice_enabled)
pr_err("%s: ICE device is not enabled\n", __func__);
pr_err("%s: =========== REGISTER DUMP (%p)===========\n",
pr_err("%s: =========== REGISTER DUMP (%pK)===========\n",
ice_dev->ice_instance_type, ice_dev);
pr_err("%s: ICE Control: 0x%08x | ICE Reset: 0x%08x\n",
@ -1503,7 +1503,7 @@ struct platform_device *qcom_ice_get_pdevice(struct device_node *node)
struct ice_device *ice_dev = NULL;
if (!node) {
pr_err("%s: invalid node %p", __func__, node);
pr_err("%s: invalid node %pK", __func__, node);
goto out;
}
@ -1521,13 +1521,14 @@ struct platform_device *qcom_ice_get_pdevice(struct device_node *node)
list_for_each_entry(ice_dev, &ice_devices, list) {
if (ice_dev->pdev->of_node == node) {
pr_info("%s: found ice device %p\n", __func__, ice_dev);
pr_info("%s: found ice device %pK\n", __func__,
ice_dev);
break;
}
}
ice_pdev = to_platform_device(ice_dev->pdev);
pr_info("%s: matching platform device %p\n", __func__, ice_pdev);
pr_info("%s: matching platform device %pK\n", __func__, ice_pdev);
out:
return ice_pdev;
}
@ -1566,7 +1567,7 @@ static int enable_ice_setup(struct ice_device *ice_dev)
}
ret = regulator_enable(ice_dev->reg);
if (ret) {
pr_err("%s:%p: Could not enable regulator\n",
pr_err("%s:%pK: Could not enable regulator\n",
__func__, ice_dev);
goto out;
}
@ -1574,7 +1575,7 @@ static int enable_ice_setup(struct ice_device *ice_dev)
/* Setup Clocks */
if (qcom_ice_enable_clocks(ice_dev, true)) {
pr_err("%s:%p:%s Could not enable clocks\n", __func__,
pr_err("%s:%pK:%s Could not enable clocks\n", __func__,
ice_dev, ice_dev->ice_instance_type);
goto out_reg;
}
@ -1586,7 +1587,7 @@ static int enable_ice_setup(struct ice_device *ice_dev)
ret = qcom_ice_set_bus_vote(ice_dev, vote);
if (ret) {
pr_err("%s:%p: failed %d\n", __func__, ice_dev, ret);
pr_err("%s:%pK: failed %d\n", __func__, ice_dev, ret);
goto out_clocks;
}
@ -1618,19 +1619,19 @@ static int disable_ice_setup(struct ice_device *ice_dev)
/* Setup Bus Vote */
vote = qcom_ice_get_bus_vote(ice_dev, "MIN");
if (vote < 0) {
pr_err("%s:%p: Unable to get bus vote\n", __func__, ice_dev);
pr_err("%s:%pK: Unable to get bus vote\n", __func__, ice_dev);
goto out_disable_clocks;
}
ret = qcom_ice_set_bus_vote(ice_dev, vote);
if (ret)
pr_err("%s:%p: failed %d\n", __func__, ice_dev, ret);
pr_err("%s:%pK: failed %d\n", __func__, ice_dev, ret);
out_disable_clocks:
/* Setup Clocks */
if (qcom_ice_enable_clocks(ice_dev, false))
pr_err("%s:%p:%s Could not disable clocks\n", __func__,
pr_err("%s:%pK:%s Could not disable clocks\n", __func__,
ice_dev, ice_dev->ice_instance_type);
/* Setup Regulator */
@ -1641,7 +1642,7 @@ out_disable_clocks:
}
ret = regulator_disable(ice_dev->reg);
if (ret) {
pr_err("%s:%p: Could not disable regulator\n",
pr_err("%s:%pK: Could not disable regulator\n",
__func__, ice_dev);
goto out;
}

4
drivers/crypto/msm/ota_crypto.c
View File

@ -172,7 +172,7 @@ static int qcota_release(struct inode *inode, struct file *file)
podev = file->private_data;
if (podev != NULL && podev->magic != OTA_MAGIC) {
pr_err("%s: invalid handle %p\n",
pr_err("%s: invalid handle %pK\n",
__func__, podev);
}
@ -441,7 +441,7 @@ static long qcota_ioctl(struct file *file,
podev = file->private_data;
if (podev == NULL || podev->magic != OTA_MAGIC) {
pr_err("%s: invalid handle %p\n",
pr_err("%s: invalid handle %pK\n",
__func__, podev);
return -ENOENT;
}

18
drivers/crypto/msm/qce50.c
View File

@ -1,6 +1,6 @@
/* Qualcomm Crypto Engine driver.
*
* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2015, 2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -235,11 +235,11 @@ static int _probe_ce_engine(struct qce_device *pce_dev)
pce_dev->ce_sps.ce_burst_size = MAX_CE_BAM_BURST_SIZE;
dev_info(pce_dev->pdev,
"CE device = 0x%x\n, "
"IO base, CE = 0x%p\n, "
"CE device = 0x%x\n"
"IO base, CE = 0x%pK\n"
"Consumer (IN) PIPE %d, "
"Producer (OUT) PIPE %d\n"
"IO base BAM = 0x%p\n"
"IO base BAM = 0x%pK\n"
"BAM IRQ %d\n"
"Engines Availability = 0x%x\n",
pce_dev->ce_sps.ce_device,
@ -1092,7 +1092,7 @@ static void _qce_dump_descr_fifos_dbg(struct qce_device *pce_dev)
#define QCE_WRITE_REG(val, addr) \
{ \
pr_info(" [0x%p] 0x%x\n", addr, (uint32_t)val); \
pr_info(" [0x%pK] 0x%x\n", addr, (uint32_t)val); \
writel_relaxed(val, addr); \
}
@ -2510,7 +2510,7 @@ static int qce_sps_init_ep_conn(struct qce_device *pce_dev,
sps_event->xfer_done = NULL;
sps_event->user = (void *)pce_dev;
pr_debug("success, %s : pipe_handle=0x%lx, desc fifo base (phy) = 0x%p\n",
pr_debug("success, %s : pipe_handle=0x%lx, desc fifo base (phy) = 0x%pK\n",
is_producer ? "PRODUCER(RX/OUT)" : "CONSUMER(TX/IN)",
(uintptr_t)sps_pipe_info, &sps_connect_info->desc.phys_base);
goto out;
@ -2674,7 +2674,7 @@ static int qce_sps_get_bam(struct qce_device *pce_dev)
bam.ee = pce_dev->ce_sps.bam_ee;
pr_debug("bam physical base=0x%lx\n", (uintptr_t)bam.phys_addr);
pr_debug("bam virtual base=0x%p\n", bam.virt_addr);
pr_debug("bam virtual base=0x%pK\n", bam.virt_addr);
/* Register CE Peripheral BAM device to SPS driver */
rc = sps_register_bam_device(&bam, &pbam->handle);
@ -2761,9 +2761,9 @@ static void qce_sps_exit(struct qce_device *pce_dev)
static void print_notify_debug(struct sps_event_notify *notify)
{
phys_addr_t addr = DESC_FULL_ADDR(notify->data.transfer.iovec.flags,
phys_addr_t addr = DESC_FULL_ADDR(notify->data.transfer.iovec.flags,
notify->data.transfer.iovec.addr);
pr_debug("sps ev_id=%d, addr=0x%pa, size=0x%x, flags=0x%x user=0x%p\n",
pr_debug("sps ev_id=%d, addr=0x%pa, size=0x%x, flags=0x%x user=0x%pK\n",
notify->event_id, &addr,
notify->data.transfer.iovec.size,
notify->data.transfer.iovec.flags,

4
drivers/crypto/msm/qcedev.c
View File

@ -228,7 +228,7 @@ static int qcedev_release(struct inode *inode, struct file *file)
handle = file->private_data;
podev = handle->cntl;
if (podev != NULL && podev->magic != QCEDEV_MAGIC) {
pr_err("%s: invalid handle %p\n",
pr_err("%s: invalid handle %pK\n",
__func__, podev);
}
kzfree(handle);
@ -1632,7 +1632,7 @@ long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg)
podev = handle->cntl;
qcedev_areq.handle = handle;
if (podev == NULL || podev->magic != QCEDEV_MAGIC) {
pr_err("%s: invalid handle %p\n",
pr_err("%s: invalid handle %pK\n",
__func__, podev);
return -ENOENT;
}

20
drivers/crypto/msm/qcrypto.c
View File

@ -1433,7 +1433,7 @@ static void _qce_ahash_complete(void *cookie, unsigned char *digest,
pengine = rctx->pengine;
#ifdef QCRYPTO_DEBUG
dev_info(&pengine->pdev->dev, "_qce_ahash_complete: %p ret %d\n",
dev_info(&pengine->pdev->dev, "_qce_ahash_complete: %pK ret %d\n",
areq, ret);
#endif
if (digest) {
@ -1481,7 +1481,7 @@ static void _qce_ablk_cipher_complete(void *cookie, unsigned char *icb,
rctx = ablkcipher_request_ctx(areq);
pengine = rctx->pengine;
#ifdef QCRYPTO_DEBUG
dev_info(&pengine->pdev->dev, "_qce_ablk_cipher_complete: %p ret %d\n",
dev_info(&pengine->pdev->dev, "_qce_ablk_cipher_complete: %pK ret %d\n",
areq, ret);
#endif
if (iv)
@ -2299,7 +2299,7 @@ static int _qcrypto_enc_aes_ecb(struct ablkcipher_request *req)
BUG_ON(crypto_tfm_alg_type(req->base.tfm) !=
CRYPTO_ALG_TYPE_ABLKCIPHER);
#ifdef QCRYPTO_DEBUG
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ecb: %p\n", req);
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ecb: %pK\n", req);
#endif
if ((ctx->enc_key_len == AES_KEYSIZE_192) &&
@ -2329,7 +2329,7 @@ static int _qcrypto_enc_aes_cbc(struct ablkcipher_request *req)
BUG_ON(crypto_tfm_alg_type(req->base.tfm) !=
CRYPTO_ALG_TYPE_ABLKCIPHER);
#ifdef QCRYPTO_DEBUG
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_cbc: %p\n", req);
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_cbc: %pK\n", req);
#endif
if ((ctx->enc_key_len == AES_KEYSIZE_192) &&
@ -2359,7 +2359,7 @@ static int _qcrypto_enc_aes_ctr(struct ablkcipher_request *req)
BUG_ON(crypto_tfm_alg_type(req->base.tfm) !=
CRYPTO_ALG_TYPE_ABLKCIPHER);
#ifdef QCRYPTO_DEBUG
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ctr: %p\n", req);
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ctr: %pK\n", req);
#endif
if ((ctx->enc_key_len == AES_KEYSIZE_192) &&
@ -2543,7 +2543,7 @@ static int _qcrypto_dec_aes_ecb(struct ablkcipher_request *req)
BUG_ON(crypto_tfm_alg_type(req->base.tfm) !=
CRYPTO_ALG_TYPE_ABLKCIPHER);
#ifdef QCRYPTO_DEBUG
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ecb: %p\n", req);
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ecb: %pK\n", req);
#endif
if ((ctx->enc_key_len == AES_KEYSIZE_192) &&
@ -2573,7 +2573,7 @@ static int _qcrypto_dec_aes_cbc(struct ablkcipher_request *req)
BUG_ON(crypto_tfm_alg_type(req->base.tfm) !=
CRYPTO_ALG_TYPE_ABLKCIPHER);
#ifdef QCRYPTO_DEBUG
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_cbc: %p\n", req);
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_cbc: %pK\n", req);
#endif
if ((ctx->enc_key_len == AES_KEYSIZE_192) &&
@ -2603,7 +2603,7 @@ static int _qcrypto_dec_aes_ctr(struct ablkcipher_request *req)
BUG_ON(crypto_tfm_alg_type(req->base.tfm) !=
CRYPTO_ALG_TYPE_ABLKCIPHER);
#ifdef QCRYPTO_DEBUG
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ctr: %p\n", req);
dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ctr: %pK\n", req);
#endif
if ((ctx->enc_key_len == AES_KEYSIZE_192) &&
@ -2915,7 +2915,7 @@ static int _qcrypto_aead_encrypt_aes_cbc(struct aead_request *req)
#ifdef QCRYPTO_DEBUG
dev_info(&ctx->pengine->pdev->dev,
"_qcrypto_aead_encrypt_aes_cbc: %p\n", req);
"_qcrypto_aead_encrypt_aes_cbc: %pK\n", req);
#endif
rctx = aead_request_ctx(req);
@ -2942,7 +2942,7 @@ static int _qcrypto_aead_decrypt_aes_cbc(struct aead_request *req)
#ifdef QCRYPTO_DEBUG
dev_info(&ctx->pengine->pdev->dev,
"_qcrypto_aead_decrypt_aes_cbc: %p\n", req);
"_qcrypto_aead_decrypt_aes_cbc: %pK\n", req);
#endif
rctx = aead_request_ctx(req);
rctx->aead = 1;