From 6bfb6aa91f61f2a7c526a6353c8c50676ca528da Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 13 Aug 2010 20:08:55 +0100 Subject: [PATCH] ASoC: Automatically manage WM8580 DAC OSR The DAC OSR should be selected based on the sample clock ratio. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/codecs/wm8580.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index 834cf141ea2f..d66db4bf11e4 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c @@ -94,6 +94,8 @@ #define WM8580_MAX_REGISTER 0x35 +#define WM8580_DACOSR 0x40 + /* PLLB4 (register 7h) */ #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60 #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20 @@ -481,7 +483,7 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream, struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); u16 paifa = 0; u16 paifb = 0; - int i, ratio; + int i, ratio, osr; /* bit size */ switch (params_format(params)) { @@ -518,6 +520,22 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream, dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n", wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + switch (ratio) { + case 128: + case 192: + osr = WM8580_DACOSR; + dev_dbg(codec->dev, "Selecting 64x OSR\n"); + break; + default: + osr = 0; + dev_dbg(codec->dev, "Selecting 128x OSR\n"); + break; + } + + snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr); + } + snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id, WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK, paifa);