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ARM: dts: msm: Modify frequencies from APSS PLL for MSM8952

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The clusters/cci which could go to low power mode with gpll frequencies
leaves a hw vote always on irrespective of APSS active or in-active. Move
the frequencies to be derived out of APSS/CCI PLL and SPM could take care
of turning the PLLs off when APSS is in-active.

Change-Id: Id43434c5560dee98fe84d11e2685376e1b8f56c8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2015-10-01 15:27:08 +05:30 committed by Gerrit - the friendly Code Review server
parent 6d674cdc15
commit 7949d56ae2
3 changed files with 22 additions and 19 deletions
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2
arch/arm/boot/dts/qcom/msm8952-regulator.dtsi
View file

@ -403,7 +403,7 @@
qcom,cpr-corner-map = <1 2 2 2 2 3 3 3>;
qcom,cpr-corner-frequency-map =
<1 499200000>,
<2 800000000>,
<2 806400000>,
<3 960000000>,
<4 1094400000>,
<5 1344000000>,

36
arch/arm/boot/dts/qcom/msm8952.dtsi
View file

@ -212,8 +212,8 @@
qcom,cpu-pcnoc-vote;
qcom,speed0-bin-v0-c0 =
< 0 0>,
< 400000000 1>,
< 800000000 4>,
< 403200000 1>,
< 806400000 4>,
< 998400000 5>,
< 1094400000 6>,
< 1209600000 7>;
@ -221,7 +221,7 @@
qcom,speed0-bin-v0-c1 =
< 0 0>,
< 499200000 1>,
< 800000000 2>,
< 806400000 2>,
< 960000000 3>,
< 1094400000 4>,
< 1344000000 5>,
@ -232,13 +232,13 @@
< 0 0>,
< 200000000 1>,
< 307200000 2>,
< 400000000 4>,
< 403200000 4>,
< 600000000 6>;
qcom,speed1-bin-v0-c0 =
< 0 0>,
< 400000000 1>,
< 800000000 4>,
< 403200000 1>,
< 806400000 4>,
< 998400000 5>,
< 1094400000 6>,
< 1209600000 7>;
@ -246,7 +246,7 @@
qcom,speed1-bin-v0-c1 =
< 0 0>,
< 499200000 1>,
< 800000000 2>,
< 806400000 2>,
< 960000000 3>,
< 1094400000 4>,
< 1344000000 5>,
@ -257,13 +257,13 @@
< 0 0>,
< 200000000 1>,
< 307200000 2>,
< 400000000 4>,
< 403200000 4>,
< 600000000 6>;
qcom,speed2-bin-v0-c0 =
< 0 0>,
< 400000000 1>,
< 800000000 4>,
< 403200000 1>,
< 806400000 4>,
< 998400000 5>,
< 1094400000 6>,
< 1209600000 8>;
@ -271,7 +271,7 @@
qcom,speed2-bin-v0-c1 =
< 0 0>,
< 499200000 1>,
< 800000000 2>,
< 806400000 2>,
< 960000000 3>,
< 1094400000 4>,
< 1344000000 5>,
@ -283,7 +283,7 @@
< 0 0>,
< 200000000 1>,
< 307200000 2>,
< 400000000 4>,
< 403200000 4>,
< 600000000 6>;
#clock-cells = <1>;
};
@ -317,7 +317,7 @@
freq-tbl-khz =
< 200000 >,
< 307200 >,
< 400000 >,
< 403200 >,
< 600000 >;
};
@ -369,7 +369,7 @@
< 1440000 6152 >, /* NOM+ */
< 1651200 7031 >; /* TURBO */
cpu-to-dev-map-4 =
< 800000 5346 >, /* SVS+ */
< 806400 5346 >, /* SVS+ */
< 998400 5712 >, /* NOM */
< 1094400 6152 >, /* NOM+ */
< 1209600 7031 >; /* TURBO */
@ -389,11 +389,11 @@
target-dev = <&cci_cache>;
cpu-to-dev-map-0 =
< 960000 307200 >,
< 1344000 400000 >,
< 1344000 403200 >,
< 1651200 600000 >;
cpu-to-dev-map-4 =
< 800000 307200 >,
< 998400 400000 >,
< 806400 307200 >,
< 998400 403200 >,
< 1209600 600000 >;
};
};
@ -424,7 +424,7 @@
< 1516800 >,
< 1651200 >;
qcom,cpufreq-table-4 =
< 800000 >,
< 806400 >,
< 998400 >,
< 1094400 >,
< 1209600 >;

3
drivers/clk/qcom/clock-gcc-8952.c
View file

@ -247,6 +247,7 @@ static DEFINE_VDD_REGULATORS(vdd_hf_pll, VDD_HF_PLL_NUM, 2,
static struct pll_freq_tbl apcs_cci_pll_freq[] = {
F_APCS_PLL(307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL(403200000, 21, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL(600000000, 31, 0x1, 0x4, 0x0, 0x0, 0x0),
};
@ -289,10 +290,12 @@ static struct pll_freq_tbl apcs_c0_pll_freq[] = {
F_APCS_PLL( 307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL( 403200000, 21, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL( 460800000, 24, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL( 518400000, 27, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL( 921600000, 48, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),