mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-11-07 04:09:21 +00:00
ARM: use clockevents_config_and_register() where possible
The clockevent core is able to figure out the best mult and shift, calculate min_delta_ns and max_delta_ns, with the necessary info passed into clockevents_config_and_register(). Use this combined configure and register function where possible to make the codes less error prone and gain some positive diff stat. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Reviewed-by: Anton Vorontsov <cbouatmailru@gmail.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Tested-by: Roland Stigge <stigge@antcom.de> Acked-by: Eric Miao <eric.y.miao@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Cc: David Brown <davidb@codeaurora.org> Tested-by: Tony Lindgren <tony@atomide.com> Acked-by: Barry Song <baohua.song@csr.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tony Prisk <linux@prisktech.co.nz> Cc: Lennert Buytenhek <buytenh@wantstofly.org> Cc: Wan ZongShun <mcuos.com@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Shawn Guo
Olof Johansson
parent
c35ef95c27
commit
838a2ae80a
25 changed files with 53 additions and 209 deletions
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@ -174,7 +174,6 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
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static struct clock_event_device clkevt = {
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.name = "at91_tick",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.rating = 150,
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.set_next_event = clkevt32k_next_event,
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.set_mode = clkevt32k_mode,
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@ -265,11 +264,9 @@ void __init at91rm9200_timer_init(void)
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at91_st_write(AT91_ST_RTMR, 1);
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/* Setup timer clockevent, with minimum of two ticks (important!!) */
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clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
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clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
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clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
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clkevt.cpumask = cpumask_of(0);
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clockevents_register_device(&clkevt);
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clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
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2, AT91_ST_ALMV);
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/* register clocksource */
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clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
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@ -134,7 +134,6 @@ static int cns3xxx_timer_set_next_event(unsigned long evt,
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static struct clock_event_device cns3xxx_tmr1_clockevent = {
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.name = "cns3xxx timer1",
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.shift = 8,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = cns3xxx_timer_set_mode,
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.set_next_event = cns3xxx_timer_set_next_event,
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@ -145,15 +144,9 @@ static struct clock_event_device cns3xxx_tmr1_clockevent = {
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static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
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{
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cns3xxx_tmr1_clockevent.irq = timer_irq;
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cns3xxx_tmr1_clockevent.mult =
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div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC,
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cns3xxx_tmr1_clockevent.shift);
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cns3xxx_tmr1_clockevent.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent);
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cns3xxx_tmr1_clockevent.min_delta_ns =
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clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent);
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clockevents_register_device(&cns3xxx_tmr1_clockevent);
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clockevents_config_and_register(&cns3xxx_tmr1_clockevent,
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(cns3xxx_cpu_clock() >> 3) * 1000000,
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0xf, 0xffffffff);
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}
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/*
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@ -255,13 +255,9 @@ static struct irqaction mct_comp_event_irq = {
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static void exynos4_clockevent_init(void)
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{
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clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
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mct_comp_device.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &mct_comp_device);
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mct_comp_device.min_delta_ns =
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clockevent_delta2ns(0xf, &mct_comp_device);
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mct_comp_device.cpumask = cpumask_of(0);
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clockevents_register_device(&mct_comp_device);
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clockevents_config_and_register(&mct_comp_device, clk_rate,
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0xf, 0xffffffff);
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if (soc_is_exynos5250())
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setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
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@ -404,14 +400,8 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
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evt->set_mode = exynos4_tick_set_mode;
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evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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evt->rating = 450;
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clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5);
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evt->max_delta_ns =
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clockevent_delta2ns(0x7fffffff, evt);
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evt->min_delta_ns =
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clockevent_delta2ns(0xf, evt);
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clockevents_register_device(evt);
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clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
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0xf, 0x7fffffff);
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exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
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@ -101,12 +101,8 @@ static void __init footbridge_timer_init(void)
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setup_irq(ce->irq, &footbridge_timer_irq);
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clockevents_calc_mult_shift(ce, mem_fclk_21285, 5);
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ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce);
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ce->min_delta_ns = clockevent_delta2ns(0x000004, ce);
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ce->cpumask = cpumask_of(smp_processor_id());
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clockevents_register_device(ce);
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clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff);
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}
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struct sys_timer footbridge_timer = {
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@ -178,7 +178,6 @@ static struct irqaction epit_timer_irq = {
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static struct clock_event_device clockevent_epit = {
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.name = "epit",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_mode = epit_set_mode,
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.set_next_event = epit_set_next_event,
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.rating = 200,
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@ -186,18 +185,10 @@ static struct clock_event_device clockevent_epit = {
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static int __init epit_clockevent_init(struct clk *timer_clk)
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{
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unsigned int c = clk_get_rate(timer_clk);
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clockevent_epit.mult = div_sc(c, NSEC_PER_SEC,
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clockevent_epit.shift);
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clockevent_epit.max_delta_ns =
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clockevent_delta2ns(0xfffffffe, &clockevent_epit);
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clockevent_epit.min_delta_ns =
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clockevent_delta2ns(0x800, &clockevent_epit);
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clockevent_epit.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_epit);
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clockevents_config_and_register(&clockevent_epit,
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clk_get_rate(timer_clk),
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0x800, 0xfffffffe);
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return 0;
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}
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@ -256,7 +256,6 @@ static struct irqaction mxc_timer_irq = {
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static struct clock_event_device clockevent_mxc = {
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.name = "mxc_timer1",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_mode = mxc_set_mode,
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.set_next_event = mx1_2_set_next_event,
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.rating = 200,
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@ -264,21 +263,13 @@ static struct clock_event_device clockevent_mxc = {
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static int __init mxc_clockevent_init(struct clk *timer_clk)
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{
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unsigned int c = clk_get_rate(timer_clk);
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if (timer_is_v2())
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clockevent_mxc.set_next_event = v2_set_next_event;
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clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
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clockevent_mxc.shift);
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clockevent_mxc.max_delta_ns =
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clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
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clockevent_mxc.min_delta_ns =
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clockevent_delta2ns(0xff, &clockevent_mxc);
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clockevent_mxc.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_mxc);
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clockevents_config_and_register(&clockevent_mxc,
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clk_get_rate(timer_clk),
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0xff, 0xfffffffe);
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return 0;
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}
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@ -523,22 +523,15 @@ static struct clock_event_device clockevent_ixp4xx = {
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.name = "ixp4xx timer1",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.shift = 24,
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.set_mode = ixp4xx_set_mode,
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.set_next_event = ixp4xx_set_next_event,
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};
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static void __init ixp4xx_clockevent_init(void)
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{
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clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
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clockevent_ixp4xx.shift);
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clockevent_ixp4xx.max_delta_ns =
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clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
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clockevent_ixp4xx.min_delta_ns =
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clockevent_delta2ns(0xf, &clockevent_ixp4xx);
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clockevent_ixp4xx.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_ixp4xx);
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clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
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0xf, 0xfffffffe);
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}
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void ixp4xx_restart(char mode, const char *cmd)
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@ -70,7 +70,6 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
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static struct clock_event_device lpc32xx_clkevt = {
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.name = "lpc32xx_clkevt",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.rating = 300,
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.set_next_event = lpc32xx_clkevt_next_event,
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.set_mode = lpc32xx_clkevt_mode,
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@ -141,14 +140,8 @@ static void __init lpc32xx_timer_init(void)
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setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
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/* Setup the clockevent structure. */
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lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
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lpc32xx_clkevt.shift);
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lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1,
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&lpc32xx_clkevt);
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lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1,
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&lpc32xx_clkevt) + 1;
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lpc32xx_clkevt.cpumask = cpumask_of(0);
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clockevents_register_device(&lpc32xx_clkevt);
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clockevents_config_and_register(&lpc32xx_clkevt, clkrate, 1, -1);
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/* Use timer1 as clock source. */
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__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
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@ -141,7 +141,6 @@ static void timer_set_mode(enum clock_event_mode mode,
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static struct clock_event_device ckevt = {
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.name = "clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.rating = 200,
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.set_next_event = timer_set_next_event,
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.set_mode = timer_set_mode,
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@ -198,15 +197,13 @@ void __init timer_init(int irq)
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setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
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ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
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ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
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ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
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ckevt.cpumask = cpumask_of(0);
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setup_irq(irq, &timer_irq);
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clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
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clockevents_register_device(&ckevt);
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clockevents_config_and_register(&ckevt, CLOCK_TICK_RATE,
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MIN_DELTA, MAX_DELTA);
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}
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#ifdef CONFIG_OF
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@ -144,13 +144,9 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
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evt->rating = msm_clockevent.rating;
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evt->set_mode = msm_timer_set_mode;
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evt->set_next_event = msm_timer_set_next_event;
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evt->shift = msm_clockevent.shift;
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evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
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evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
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evt->min_delta_ns = clockevent_delta2ns(4, evt);
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*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
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clockevents_register_device(evt);
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clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
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enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
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return 0;
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}
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@ -195,7 +195,6 @@ static void mxs_set_mode(enum clock_event_mode mode,
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static struct clock_event_device mxs_clockevent_device = {
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.name = "mxs_timrot",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_mode = mxs_set_mode,
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.set_next_event = timrotv2_set_next_event,
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.rating = 200,
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@ -203,25 +202,12 @@ static struct clock_event_device mxs_clockevent_device = {
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static int __init mxs_clockevent_init(struct clk *timer_clk)
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{
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unsigned int c = clk_get_rate(timer_clk);
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mxs_clockevent_device.mult =
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div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift);
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mxs_clockevent_device.cpumask = cpumask_of(0);
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if (timrot_is_v1()) {
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if (timrot_is_v1())
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mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
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mxs_clockevent_device.max_delta_ns =
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clockevent_delta2ns(0xfffe, &mxs_clockevent_device);
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mxs_clockevent_device.min_delta_ns =
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clockevent_delta2ns(0xf, &mxs_clockevent_device);
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} else {
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mxs_clockevent_device.max_delta_ns =
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clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device);
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mxs_clockevent_device.min_delta_ns =
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clockevent_delta2ns(0xf, &mxs_clockevent_device);
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}
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clockevents_register_device(&mxs_clockevent_device);
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mxs_clockevent_device.cpumask = cpumask_of(0);
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clockevents_config_and_register(&mxs_clockevent_device,
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clk_get_rate(timer_clk), 0xf,
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timrot_is_v1() ? 0xfffe : 0xfffffffe);
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return 0;
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}
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@ -76,7 +76,6 @@ static int netx_set_next_event(unsigned long evt,
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static struct clock_event_device netx_clockevent = {
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.name = "netx-timer" __stringify(TIMER_CLOCKEVENT),
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = netx_set_next_event,
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.set_mode = netx_set_mode,
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@ -140,16 +139,11 @@ static void __init netx_timer_init(void)
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clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
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"netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up);
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netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
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netx_clockevent.shift);
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netx_clockevent.max_delta_ns =
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clockevent_delta2ns(0xfffffffe, &netx_clockevent);
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/* with max_delta_ns >= delta2ns(0x800) the system currently runs fine.
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* Adding some safety ... */
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netx_clockevent.min_delta_ns =
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clockevent_delta2ns(0xa00, &netx_clockevent);
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netx_clockevent.cpumask = cpumask_of(0);
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clockevents_register_device(&netx_clockevent);
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clockevents_config_and_register(&netx_clockevent, CLOCK_TICK_RATE,
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0xa00, 0xfffffffe);
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}
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struct sys_timer netx_timer = {
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@ -145,7 +145,6 @@ static void omap_mpu_set_mode(enum clock_event_mode mode,
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static struct clock_event_device clockevent_mpu_timer1 = {
|
||||
.name = "mpu_timer1",
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.shift = 32,
|
||||
.set_next_event = omap_mpu_set_next_event,
|
||||
.set_mode = omap_mpu_set_mode,
|
||||
};
|
||||
|
|
@ -170,15 +169,9 @@ static __init void omap_init_mpu_timer(unsigned long rate)
|
|||
setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
|
||||
omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
|
||||
|
||||
clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
|
||||
clockevent_mpu_timer1.shift);
|
||||
clockevent_mpu_timer1.max_delta_ns =
|
||||
clockevent_delta2ns(-1, &clockevent_mpu_timer1);
|
||||
clockevent_mpu_timer1.min_delta_ns =
|
||||
clockevent_delta2ns(1, &clockevent_mpu_timer1);
|
||||
|
||||
clockevent_mpu_timer1.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&clockevent_mpu_timer1);
|
||||
clockevents_config_and_register(&clockevent_mpu_timer1, rate,
|
||||
1, -1);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -140,7 +140,6 @@ static void omap_32k_timer_set_mode(enum clock_event_mode mode,
|
|||
static struct clock_event_device clockevent_32k_timer = {
|
||||
.name = "32k-timer",
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.shift = 32,
|
||||
.set_next_event = omap_32k_timer_set_next_event,
|
||||
.set_mode = omap_32k_timer_set_mode,
|
||||
};
|
||||
|
|
@ -165,16 +164,9 @@ static __init void omap_init_32k_timer(void)
|
|||
{
|
||||
setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
|
||||
|
||||
clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
|
||||
NSEC_PER_SEC,
|
||||
clockevent_32k_timer.shift);
|
||||
clockevent_32k_timer.max_delta_ns =
|
||||
clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
|
||||
clockevent_32k_timer.min_delta_ns =
|
||||
clockevent_delta2ns(1, &clockevent_32k_timer);
|
||||
|
||||
clockevent_32k_timer.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&clockevent_32k_timer);
|
||||
clockevents_config_and_register(&clockevent_32k_timer,
|
||||
OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -131,7 +131,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
|
|||
static struct clock_event_device clockevent_gpt = {
|
||||
.name = "gp_timer",
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.shift = 32,
|
||||
.rating = 300,
|
||||
.set_next_event = omap2_gp_timer_set_next_event,
|
||||
.set_mode = omap2_gp_timer_set_mode,
|
||||
|
|
@ -340,17 +339,11 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
|
|||
|
||||
__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
|
||||
|
||||
clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
|
||||
clockevent_gpt.shift);
|
||||
clockevent_gpt.max_delta_ns =
|
||||
clockevent_delta2ns(0xffffffff, &clockevent_gpt);
|
||||
clockevent_gpt.min_delta_ns =
|
||||
clockevent_delta2ns(3, &clockevent_gpt);
|
||||
/* Timer internal resynch latency. */
|
||||
|
||||
clockevent_gpt.cpumask = cpu_possible_mask;
|
||||
clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
|
||||
clockevents_register_device(&clockevent_gpt);
|
||||
clockevents_config_and_register(&clockevent_gpt, clkev.rate,
|
||||
3, /* Timer internal resynch latency */
|
||||
0xffffffff);
|
||||
|
||||
pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
|
||||
gptimer_id, clkev.rate);
|
||||
|
|
|
|||
|
|
@ -175,15 +175,9 @@ static u32 notrace sirfsoc_read_sched_clock(void)
|
|||
|
||||
static void __init sirfsoc_clockevent_init(void)
|
||||
{
|
||||
clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
|
||||
|
||||
sirfsoc_clockevent.max_delta_ns =
|
||||
clockevent_delta2ns(-2, &sirfsoc_clockevent);
|
||||
sirfsoc_clockevent.min_delta_ns =
|
||||
clockevent_delta2ns(2, &sirfsoc_clockevent);
|
||||
|
||||
sirfsoc_clockevent.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&sirfsoc_clockevent);
|
||||
clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE,
|
||||
2, -2);
|
||||
}
|
||||
|
||||
/* initialize the kernel jiffy timer source */
|
||||
|
|
|
|||
|
|
@ -113,18 +113,14 @@ static void __init pxa_timer_init(void)
|
|||
|
||||
setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
|
||||
|
||||
clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
|
||||
ckevt_pxa_osmr0.max_delta_ns =
|
||||
clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
|
||||
ckevt_pxa_osmr0.min_delta_ns =
|
||||
clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
|
||||
ckevt_pxa_osmr0.cpumask = cpumask_of(0);
|
||||
|
||||
setup_irq(IRQ_OST0, &pxa_ost0_irq);
|
||||
|
||||
clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
|
||||
clocksource_mmio_readl_up);
|
||||
clockevents_register_device(&ckevt_pxa_osmr0);
|
||||
clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
|
||||
MIN_OSCR_DELTA * 2, 0x7fffffff);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
|
|||
|
|
@ -91,18 +91,14 @@ static void __init sa1100_timer_init(void)
|
|||
|
||||
setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
|
||||
|
||||
clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4);
|
||||
ckevt_sa1100_osmr0.max_delta_ns =
|
||||
clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
|
||||
ckevt_sa1100_osmr0.min_delta_ns =
|
||||
clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
|
||||
ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
|
||||
|
||||
setup_irq(IRQ_OST0, &sa1100_timer_irq);
|
||||
|
||||
clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
|
||||
clocksource_mmio_readl_up);
|
||||
clockevents_register_device(&ckevt_sa1100_osmr0);
|
||||
clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400,
|
||||
MIN_OSCR_DELTA * 2, 0x7fffffff);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
|
|||
|
|
@ -259,14 +259,10 @@ static void __init tegra_init_timer(void)
|
|||
BUG();
|
||||
}
|
||||
|
||||
clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
|
||||
tegra_clockevent.max_delta_ns =
|
||||
clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
|
||||
tegra_clockevent.min_delta_ns =
|
||||
clockevent_delta2ns(0x1, &tegra_clockevent);
|
||||
tegra_clockevent.cpumask = cpu_all_mask;
|
||||
tegra_clockevent.irq = tegra_timer_irq.irq;
|
||||
clockevents_register_device(&tegra_clockevent);
|
||||
clockevents_config_and_register(&tegra_clockevent, 1000000,
|
||||
0x1, 0x1fffffff);
|
||||
#ifdef CONFIG_HAVE_ARM_TWD
|
||||
twd_local_timer_of_register();
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -168,17 +168,12 @@ void __init vt8500_timer_init(void)
|
|||
pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
|
||||
__func__, clocksource.name);
|
||||
|
||||
clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
|
||||
|
||||
/* copy-pasted from mach-msm; no idea */
|
||||
clockevent.max_delta_ns =
|
||||
clockevent_delta2ns(0xf0000000, &clockevent);
|
||||
clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
|
||||
clockevent.cpumask = cpumask_of(0);
|
||||
|
||||
if (setup_irq(timer_irq, &irq))
|
||||
pr_err("%s: setup_irq failed for %s\n", __func__,
|
||||
clockevent.name);
|
||||
clockevents_register_device(&clockevent);
|
||||
clockevents_config_and_register(&clockevent, VT8500_TIMER_HZ,
|
||||
4, 0xf0000000);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -91,7 +91,6 @@ static int nuc900_clockevent_setnextevent(unsigned long evt,
|
|||
|
||||
static struct clock_event_device nuc900_clockevent_device = {
|
||||
.name = "nuc900-timer0",
|
||||
.shift = 32,
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_mode = nuc900_clockevent_setmode,
|
||||
.set_next_event = nuc900_clockevent_setnextevent,
|
||||
|
|
@ -133,15 +132,10 @@ static void __init nuc900_clockevents_init(void)
|
|||
__raw_writel(RESETINT, REG_TISR);
|
||||
setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
|
||||
|
||||
nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
|
||||
nuc900_clockevent_device.shift);
|
||||
nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
|
||||
&nuc900_clockevent_device);
|
||||
nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
|
||||
&nuc900_clockevent_device);
|
||||
nuc900_clockevent_device.cpumask = cpumask_of(0);
|
||||
|
||||
clockevents_register_device(&nuc900_clockevent_device);
|
||||
clockevents_config_and_register(&nuc900_clockevent_device, rate,
|
||||
0xf, 0xffffffff);
|
||||
}
|
||||
|
||||
static void __init nuc900_clocksource_init(void)
|
||||
|
|
|
|||
|
|
@ -156,14 +156,9 @@ void __init iop_init_time(unsigned long tick_rate)
|
|||
write_tmr0(timer_ctl & ~IOP_TMR_EN);
|
||||
write_tisr(1);
|
||||
setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
|
||||
clockevents_calc_mult_shift(&iop_clockevent,
|
||||
tick_rate, IOP_MIN_RANGE);
|
||||
iop_clockevent.max_delta_ns =
|
||||
clockevent_delta2ns(0xfffffffe, &iop_clockevent);
|
||||
iop_clockevent.min_delta_ns =
|
||||
clockevent_delta2ns(0xf, &iop_clockevent);
|
||||
iop_clockevent.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&iop_clockevent);
|
||||
clockevents_config_and_register(&iop_clockevent, tick_rate,
|
||||
0xf, 0xfffffffe);
|
||||
|
||||
/*
|
||||
* Set up free-running clocksource timer 1.
|
||||
|
|
|
|||
|
|
@ -156,7 +156,6 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
|
|||
static struct clock_event_device orion_clkevt = {
|
||||
.name = "orion_tick",
|
||||
.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
|
||||
.shift = 32,
|
||||
.rating = 300,
|
||||
.set_next_event = orion_clkevt_next_event,
|
||||
.set_mode = orion_clkevt_mode,
|
||||
|
|
@ -221,9 +220,6 @@ orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
|
|||
* Setup clockevent timer (interrupt-driven).
|
||||
*/
|
||||
setup_irq(irq, &orion_timer_irq);
|
||||
orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
|
||||
orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
|
||||
orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
|
||||
orion_clkevt.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&orion_clkevt);
|
||||
clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -274,15 +274,8 @@ static void __init s5p_clockevent_init(void)
|
|||
clock_rate = clk_get_rate(tin_event);
|
||||
clock_count_per_tick = clock_rate / HZ;
|
||||
|
||||
clockevents_calc_mult_shift(&time_event_device,
|
||||
clock_rate, S5PTIMER_MIN_RANGE);
|
||||
time_event_device.max_delta_ns =
|
||||
clockevent_delta2ns(-1, &time_event_device);
|
||||
time_event_device.min_delta_ns =
|
||||
clockevent_delta2ns(1, &time_event_device);
|
||||
|
||||
time_event_device.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&time_event_device);
|
||||
clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);
|
||||
|
||||
irq_number = timer_source.event_id + IRQ_TIMER0;
|
||||
setup_irq(irq_number, &s5p_clock_event_irq);
|
||||
|
|
|
|||
|
|
@ -186,15 +186,9 @@ static void __init spear_clockevent_init(int irq)
|
|||
tick_rate = clk_get_rate(gpt_clk);
|
||||
tick_rate >>= CTRL_PRESCALER16;
|
||||
|
||||
clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE);
|
||||
|
||||
clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
|
||||
&clkevt);
|
||||
clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt);
|
||||
|
||||
clkevt.cpumask = cpumask_of(0);
|
||||
|
||||
clockevents_register_device(&clkevt);
|
||||
clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
|
||||
|
||||
setup_irq(irq, &spear_timer_irq);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue