i7core_edac: Get more info about the memory DIMMs
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
7dd6953c5f
commit
854d334997
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@ -109,14 +109,14 @@
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#define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
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#define DIMM_PRESENT_MASK (1 << 9)
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#define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
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#define NUMBANK_MASK ((1 << 8) | (1 << 7))
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#define NUMBANK(x) (((x) & NUMBANK_MASK) >> 7)
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#define NUMRANK_MASK ((1 << 6) | (1 << 5))
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#define NUMRANK(x) (((x) & NUMRANK_MASK) >> 5)
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#define NUMROW_MASK ((1 << 4) | (1 << 3))
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#define NUMROW(x) (((x) & NUMROW_MASK) >> 3)
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#define NUMCOL_MASK 3
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#define NUMCOL(x) ((x) & NUMCOL_MASK)
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#define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
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#define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
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#define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
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#define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
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#define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3))
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#define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 3)
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#define MC_DOD_NUMCOL_MASK 3
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#define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
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#define MC_RANK_PRESENT 0x7c
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@ -268,41 +268,41 @@ static struct edac_pci_ctl_info *i7core_pci;
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#define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
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/* MC_MAX_DOD read functions */
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static inline int maxnumdimms(struct i7core_pvt *pvt)
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static inline int numdimms(u32 dimms)
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{
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return (pvt->info.max_dod & 0x3) + 1;
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return (dimms & 0x3) + 1;
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}
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static inline int maxnumrank(struct i7core_pvt *pvt)
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static inline int numrank(u32 rank)
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{
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static int ranks[4] = { 1, 2, 4, -EINVAL };
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return ranks[(pvt->info.max_dod >> 2) & 0x3];
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return ranks[rank & 0x3];
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}
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static inline int maxnumbank(struct i7core_pvt *pvt)
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static inline int numbank(u32 bank)
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{
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static int banks[4] = { 4, 8, 16, -EINVAL };
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return banks[(pvt->info.max_dod >> 4) & 0x3];
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return banks[bank & 0x3];
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}
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static inline int maxnumrow(struct i7core_pvt *pvt)
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static inline int numrow(u32 row)
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{
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static int rows[8] = {
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1 << 12, 1 << 13, 1 << 14, 1 << 15,
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1 << 16, -EINVAL, -EINVAL, -EINVAL,
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};
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return rows[((pvt->info.max_dod >> 6) & 0x7)];
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return rows[row & 0x7];
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}
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static inline int maxnumcol(struct i7core_pvt *pvt)
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static inline int numcol(u32 col)
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{
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static int cols[8] = {
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1 << 10, 1 << 11, 1 << 12, -EINVAL,
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};
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return cols[((pvt->info.max_dod >> 9) & 0x3) << 12];
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return cols[col & 0x3];
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}
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@ -359,10 +359,13 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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struct csrow_info *csr;
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struct pci_dev *pdev = pvt->pci_mcr[0];
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struct pci_dev *pdev;
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int i, j, csrow = 0;
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enum edac_type mode;
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enum mem_type mtype;
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/* Get data from the MC register, function 0 */
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pdev = pvt->pci_mcr[0];
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if (!pdev)
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return -ENODEV;
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@ -388,15 +391,18 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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}
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/* FIXME: need to handle the error codes */
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debugf0("DOD Maximum limits: DIMMS: %d, %d-ranked, %d-banked\n",
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maxnumdimms(pvt), maxnumrank(pvt), maxnumbank(pvt));
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debugf0("DOD Maximum rows x colums = 0x%x x 0x%x\n",
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maxnumrow(pvt), maxnumcol(pvt));
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debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked\n",
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numdimms(pvt->info.max_dod),
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numrank(pvt->info.max_dod >> 2),
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numbank(pvt->info.max_dod >> 4));
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debugf0("DOD Max rows x colums = 0x%x x 0x%x\n",
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numrow(pvt->info.max_dod >> 6),
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numcol(pvt->info.max_dod >> 9));
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debugf0("Memory channel configuration:\n");
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for (i = 0; i < NUM_CHANS; i++) {
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u32 data, value[8];
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u32 data, dimm_dod[3], value[8];
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if (!CH_ACTIVE(pvt, i)) {
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debugf0("Channel %i is not active\n", i);
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@ -413,58 +419,96 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT)? 4 : 2;
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if (data & REGISTERED_DIMM)
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mtype = MEM_RDDR3;
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else
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mtype = MEM_DDR3;
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#if 0
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if (data & THREE_DIMMS_PRESENT)
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pvt->channel[i].dimms = 3;
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else if (data & SINGLE_QUAD_RANK_PRESENT)
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pvt->channel[i].dimms = 1;
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else
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pvt->channel[i].dimms = 2;
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#endif
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/* Devices 4-6 function 1 */
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pci_read_config_dword(pvt->pci_ch[i][1],
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MC_DOD_CH_DIMM0, &dimm_dod[0]);
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pci_read_config_dword(pvt->pci_ch[i][1],
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MC_DOD_CH_DIMM1, &dimm_dod[1]);
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pci_read_config_dword(pvt->pci_ch[i][1],
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MC_DOD_CH_DIMM2, &dimm_dod[2]);
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debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
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"%d ranks, %d %cDIMMs, offset = %d\n\t"
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"present: %i, numbank: %#x, numrank: %#x, "
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"numrow: %#x, numcol: %#x\n",
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"%d ranks, %cDIMMs\n",
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i,
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RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
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data,
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pvt->channel[i].ranks, pvt->channel[i].dimms,
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(data & REGISTERED_DIMM)? 'R' : 'U',
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RANKOFFSET(data),
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DIMM_PRESENT(data),
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NUMBANK(data), NUMRANK(data),
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NUMROW(data), NUMCOL(data));
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pvt->channel[i].ranks,
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(data & REGISTERED_DIMM)? 'R' : 'U');
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pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
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pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
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pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
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pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
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pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
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pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
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pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
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pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
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printk("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
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for (j = 0; j < 8; j++)
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printk("\t\t%#x\t%#x\t%#x\n",
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(value[j] >> 27) & 0x1,
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(value[j] >> 24) & 0x7,
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(value[j] && ((1 << 24) - 1)));
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for (j = 0; j < 3; j++) {
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u32 banks, ranks, rows, cols;
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csr = &mci->csrows[csrow];
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csr->first_page = 0;
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csr->last_page = 0;
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csr->page_mask = 0;
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csr->nr_pages = 0;
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csr->grain = 0;
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csr->csrow_idx = csrow;
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csr->dtype = DEV_X8; /* FIXME: check this */
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if (!DIMM_PRESENT(dimm_dod[j]))
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continue;
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if (data & REGISTERED_DIMM)
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csr->mtype = MEM_RDDR3;
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else
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csr->mtype = MEM_DDR3;
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csr->edac_mode = mode;
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banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
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ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
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rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
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cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
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csrow++;
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pvt->channel[i].dimms++;
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debugf0("\tdimm %d offset: %x, numbank: %#x, "
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"numrank: %#x, numrow: %#x, numcol: %#x\n",
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j,
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RANKOFFSET(dimm_dod[j]),
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banks, ranks, rows, cols);
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csr = &mci->csrows[csrow];
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csr->first_page = 0;
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csr->last_page = 0;
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csr->page_mask = 0;
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csr->nr_pages = 0;
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csr->grain = 0;
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csr->csrow_idx = csrow;
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switch (banks) {
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case 4:
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csr->dtype = DEV_X4;
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break;
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case 8:
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csr->dtype = DEV_X8;
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break;
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case 16:
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csr->dtype = DEV_X16;
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break;
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default:
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csr->dtype = DEV_UNKNOWN;
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}
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csr->edac_mode = mode;
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csr->mtype = mtype;
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csrow++;
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}
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pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
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pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
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pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
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pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
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pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
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pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
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pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
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pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
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printk("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
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for (j = 0; j < 8; j++)
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printk("\t\t%#x\t%#x\t%#x\n",
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(value[j] >> 27) & 0x1,
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(value[j] >> 24) & 0x7,
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(value[j] && ((1 << 24) - 1)));
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}
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return 0;
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