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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
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PCI: Add accessors for PCI Express Capability
The PCI Express Capability (PCIe spec r3.0, sec 7.8) comes in two versions, v1 and v2. In v1 Capability structures (PCIe spec r1.0 and r1.1), some fields are optional, so the structure size depends on the device type. This patch adds functions to access this capability so drivers don't have to be aware of the differences between v1 and v2. Note that these new functions apply only to the "PCI Express Capability," not to any of the other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) Function pcie_capability_read_word/dword() reads the PCIe Capabilities register and returns the value in the reference parameter "val". If the PCIe Capabilities register is not implemented on the PCIe device, "val" is set to 0. Function pcie_capability_write_word/dword() writes the value to the specified PCIe Capability register. Function pcie_capability_clear_and_set_word/dword() sets and/or clears bits of a PCIe Capability register. [bhelgaas: changelog, drop "pci_" prefixes, don't export pcie_capability_reg_implemented()] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Jiang Liu
Bjorn Helgaas
parent
b2ef39be57
commit
8c0d3a02c1
3 changed files with 236 additions and 0 deletions
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@ -469,3 +469,205 @@ void pci_cfg_access_unlock(struct pci_dev *dev)
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raw_spin_unlock_irqrestore(&pci_lock, flags);
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}
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EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
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static inline int pcie_cap_version(const struct pci_dev *dev)
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{
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return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS;
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}
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static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
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{
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return true;
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}
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static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return pcie_cap_version(dev) > 1 ||
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type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_ENDPOINT ||
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type == PCI_EXP_TYPE_LEG_END;
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}
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static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return pcie_cap_version(dev) > 1 ||
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type == PCI_EXP_TYPE_ROOT_PORT ||
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(type == PCI_EXP_TYPE_DOWNSTREAM &&
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dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT);
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}
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static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return pcie_cap_version(dev) > 1 ||
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type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_RC_EC;
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}
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static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
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{
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if (!pci_is_pcie(dev))
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return false;
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switch (pos) {
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case PCI_EXP_FLAGS_TYPE:
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return true;
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case PCI_EXP_DEVCAP:
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case PCI_EXP_DEVCTL:
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case PCI_EXP_DEVSTA:
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return pcie_cap_has_devctl(dev);
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case PCI_EXP_LNKCAP:
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case PCI_EXP_LNKCTL:
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case PCI_EXP_LNKSTA:
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return pcie_cap_has_lnkctl(dev);
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case PCI_EXP_SLTCAP:
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case PCI_EXP_SLTCTL:
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case PCI_EXP_SLTSTA:
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return pcie_cap_has_sltctl(dev);
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case PCI_EXP_RTCTL:
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case PCI_EXP_RTCAP:
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case PCI_EXP_RTSTA:
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return pcie_cap_has_rtctl(dev);
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case PCI_EXP_DEVCAP2:
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case PCI_EXP_DEVCTL2:
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case PCI_EXP_LNKCAP2:
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case PCI_EXP_LNKCTL2:
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case PCI_EXP_LNKSTA2:
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return pcie_cap_version(dev) > 1;
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default:
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return false;
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}
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}
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/*
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* Note that these accessor functions are only for the "PCI Express
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* Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
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* other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
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*/
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int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
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{
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int ret;
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*val = 0;
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if (pos & 1)
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return -EINVAL;
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if (pcie_capability_reg_implemented(dev, pos)) {
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ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
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/*
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* Reset *val to 0 if pci_read_config_word() fails, it may
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* have been written as 0xFFFF if hardware error happens
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* during pci_read_config_word().
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*/
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if (ret)
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*val = 0;
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return ret;
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}
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/*
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* For Functions that do not implement the Slot Capabilities,
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* Slot Status, and Slot Control registers, these spaces must
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* be hardwired to 0b, with the exception of the Presence Detect
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* State bit in the Slot Status register of Downstream Ports,
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* which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
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*/
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if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
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pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
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*val = PCI_EXP_SLTSTA_PDS;
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}
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return 0;
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}
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EXPORT_SYMBOL(pcie_capability_read_word);
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int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
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{
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int ret;
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*val = 0;
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if (pos & 3)
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return -EINVAL;
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if (pcie_capability_reg_implemented(dev, pos)) {
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ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
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/*
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* Reset *val to 0 if pci_read_config_dword() fails, it may
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* have been written as 0xFFFFFFFF if hardware error happens
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* during pci_read_config_dword().
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*/
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if (ret)
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*val = 0;
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return ret;
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}
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if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
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pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
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*val = PCI_EXP_SLTSTA_PDS;
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}
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return 0;
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}
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EXPORT_SYMBOL(pcie_capability_read_dword);
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int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
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{
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if (pos & 1)
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return -EINVAL;
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if (!pcie_capability_reg_implemented(dev, pos))
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return 0;
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return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
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}
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EXPORT_SYMBOL(pcie_capability_write_word);
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int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
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{
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if (pos & 3)
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return -EINVAL;
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if (!pcie_capability_reg_implemented(dev, pos))
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return 0;
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return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
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}
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EXPORT_SYMBOL(pcie_capability_write_dword);
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int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
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u16 clear, u16 set)
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{
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int ret;
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u16 val;
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ret = pcie_capability_read_word(dev, pos, &val);
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if (!ret) {
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val &= ~clear;
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val |= set;
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ret = pcie_capability_write_word(dev, pos, val);
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}
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return ret;
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}
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EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
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int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
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u32 clear, u32 set)
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{
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int ret;
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u32 val;
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ret = pcie_capability_read_dword(dev, pos, &val);
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if (!ret) {
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val &= ~clear;
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val |= set;
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ret = pcie_capability_write_dword(dev, pos, val);
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}
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return ret;
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}
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EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
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@ -816,6 +816,39 @@ static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
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return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
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}
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int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
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int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
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int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
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int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
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int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
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u16 clear, u16 set);
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int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
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u32 clear, u32 set);
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static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
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u16 set)
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{
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return pcie_capability_clear_and_set_word(dev, pos, 0, set);
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}
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static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
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u32 set)
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{
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return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
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}
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static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
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u16 clear)
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{
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return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
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}
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static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
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u32 clear)
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{
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return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
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}
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/* user-space driven config access */
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int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
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int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
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@ -549,6 +549,7 @@
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#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */
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#define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
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#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
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#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
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#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
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/* Extended Capabilities (PCI-X 2.0 and Express) */
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