From 925b16ff72901403384f26fd6974910f6271b40e Mon Sep 17 00:00:00 2001 From: Asutosh Das Date: Tue, 6 Oct 2015 09:53:33 +0530 Subject: [PATCH] mmc: cmdq: decrease the QSR polling period Configure the controller to send the QSR at 1 clock period. This would send SQS(CMD13) when no data transfer is in progress. This decrease in the polling period increases the performance of the device. CRs-fixed: 891366 Change-Id: Ic2807c6334a778b5f0c89fb605c6923a44f7624a Signed-off-by: Asutosh Das Signed-off-by: Sahitya Tummala --- drivers/mmc/host/cmdq_hci.c | 3 +-- drivers/mmc/host/cmdq_hci.h | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/cmdq_hci.c b/drivers/mmc/host/cmdq_hci.c index 929f6d0ef43c..5ccfd5bce732 100644 --- a/drivers/mmc/host/cmdq_hci.c +++ b/drivers/mmc/host/cmdq_hci.c @@ -356,8 +356,7 @@ static int cmdq_enable(struct mmc_host *mmc) cmdq_writel(cq_host, mmc->card->rca, CQSSC2); /* send QSR at lesser intervals than the default */ - cmdq_writel(cq_host, cmdq_readl(cq_host, CQSSC1) | SEND_QSR_INTERVAL, - CQSSC1); + cmdq_writel(cq_host, SEND_QSR_INTERVAL, CQSSC1); /* ensure the writes are done before enabling CQE */ mb(); diff --git a/drivers/mmc/host/cmdq_hci.h b/drivers/mmc/host/cmdq_hci.h index 7eb8a828fec8..4185bf9e859c 100644 --- a/drivers/mmc/host/cmdq_hci.h +++ b/drivers/mmc/host/cmdq_hci.h @@ -78,7 +78,7 @@ * Value n means CQE would send CMD13 during the transfer of data block * BLOCK_CNT-n */ -#define SEND_QSR_INTERVAL 0x70000 +#define SEND_QSR_INTERVAL 0x70001 /* send status config 2 */ #define CQSSC2 0x44