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Merge "ARM: dts: msm: define scaling-lower-bus-speed-mode property for 8956/8976"

This commit is contained in:
Linux Build Service Account 2015-08-17 00:44:20 -07:00 committed by Gerrit - the friendly Code Review server
parent b228eabd88 e3601ff192
commit 98eda27f30
4 changed files with 16 additions and 4 deletions
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3
arch/arm/boot/dts/qcom/msm8952.dtsi
View File

@ -1331,7 +1331,7 @@
<78 512 52286 160000>, /* 20 MB/s */
<78 512 65360 200000>, /* 25 MB/s */
<78 512 130718 400000>, /* 50 MB/s */
<78 512 261438 800000>, /* 100 MB/s */
<78 512 130718 400000>, /* 100 MB/s */
<78 512 261438 800000>, /* 200 MB/s */
<78 512 261438 800000>, /* 400 MB/s */
<78 512 1338562 4096000>; /* Max. bandwidth */
@ -1346,6 +1346,7 @@
qcom,clk-rates = <400000 25000000 50000000 100000000 192000000 384000000>;
qcom,ice-clk-rates = <200000000 100000000>;
qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
qcom,scaling-lower-bus-speed-mode = "DDR52";
status = "disabled";
};

3
arch/arm/boot/dts/qcom/msm8956.dtsi
View File

@ -840,7 +840,7 @@
<78 512 52286 160000>, /* 20 MB/s */
<78 512 65360 200000>, /* 25 MB/s */
<78 512 130718 400000>, /* 50 MB/s */
<78 512 261438 800000>, /* 100 MB/s */
<78 512 130718 400000>, /* 100 MB/s */
<78 512 261438 800000>, /* 200 MB/s */
<78 512 261438 800000>, /* 400 MB/s */
<78 512 1338562 4096000>; /* Max. bandwidth */
@ -852,6 +852,7 @@
<&clock_gcc clk_gcc_sdcc1_ice_core_clk>;
clock-names = "iface_clk", "core_clk", "ice_core_clk";
qcom,ice-clk-rates = <200000000 100000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
status = "disabled";
};

3
arch/arm/boot/dts/qcom/msm8976.dtsi
View File

@ -844,7 +844,7 @@
<78 512 52286 160000>, /* 20 MB/s */
<78 512 65360 200000>, /* 25 MB/s */
<78 512 130718 400000>, /* 50 MB/s */
<78 512 261438 800000>, /* 100 MB/s */
<78 512 130718 400000>, /* 100 MB/s */
<78 512 261438 800000>, /* 200 MB/s */
<78 512 261438 800000>, /* 400 MB/s */
<78 512 1338562 4096000>; /* Max. bandwidth */
@ -856,6 +856,7 @@
<&clock_gcc clk_gcc_sdcc1_ice_core_clk>;
clock-names = "iface_clk", "core_clk", "ice_core_clk";
qcom,ice-clk-rates = <200000000 100000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
status = "disabled";
};

11
drivers/mmc/core/mmc.c
View File

@ -1212,6 +1212,7 @@ out:
int mmc_set_clock_bus_speed(struct mmc_card *card, unsigned long freq)
{
int err;
struct mmc_host *host = card->host;
if (freq < MMC_HS400_MAX_DTR) {
/*
@ -1221,8 +1222,16 @@ int mmc_set_clock_bus_speed(struct mmc_card *card, unsigned long freq)
mmc_set_timing(card->host, MMC_TIMING_LEGACY);
mmc_set_clock(card->host, MMC_HIGH_26_MAX_DTR);
err = mmc_select_hs(card, card->cached_ext_csd);
if (host->clk_scaling.lower_bus_speed_mode &
MMC_SCALING_LOWER_DDR52_MODE)
err = mmc_select_hsddr(card, card->cached_ext_csd);
else
err = mmc_select_hs(card, card->cached_ext_csd);
} else {
if (mmc_card_ddr_mode(card)) {
mmc_set_timing(card->host, MMC_TIMING_LEGACY);
mmc_set_clock(card->host, MMC_HIGH_26_MAX_DTR);
}
err = mmc_select_hs400(card, card->cached_ext_csd);
}