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msm: kgsl: Force GPU fault on GPC error 

GPC error is typically the result of mistake SW programming.
Force GPU fault for this interrupt so that we can debug it
with help of register dump.

Change-Id: I7e893fd44f26def752587ac511603ad52e82659d
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
This commit is contained in:
Prakash Kamliya 2015-10-01 22:09:06 +05:30 committed by Gerrit - the friendly Code Review server
parent 0dcd2def74
commit 9b56c06129
4 changed files with 26 additions and 18 deletions
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3
drivers/gpu/msm/adreno.c
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@ -634,7 +634,8 @@ void adreno_hang_int_callback(struct adreno_device *adreno_dev, int bit)
adreno_irqctrl(adreno_dev, 0);
/* Trigger a fault in the dispatcher - this will effect a restart */
adreno_dispatcher_irq_fault(device);
adreno_set_gpu_fault(ADRENO_DEVICE(device), ADRENO_HARD_FAULT);
adreno_dispatcher_schedule(device);
}
/*

28
drivers/gpu/msm/adreno_a5xx.c
View File

@ -2238,9 +2238,6 @@ void a5xx_err_callback(struct adreno_device *adreno_dev, int bit)
case A5XX_INT_RBBM_ATB_ASYNC_OVERFLOW:
KGSL_DRV_CRIT_RATELIMIT(device, "RBBM: ATB ASYNC overflow\n");
break;
case A5XX_INT_RBBM_GPC_ERROR:
KGSL_DRV_CRIT_RATELIMIT(device, "RBBM: GPC error\n");
break;
case A5XX_INT_RBBM_ATB_BUS_OVERFLOW:
KGSL_DRV_CRIT_RATELIMIT(device, "RBBM: ATB bus overflow\n");
break;
@ -2255,6 +2252,29 @@ void a5xx_err_callback(struct adreno_device *adreno_dev, int bit)
}
}
/*
* a5x_gpc_err_int_callback() - Isr for GPC error interrupts
* @adreno_dev: Pointer to device
* @bit: Interrupt bit
*/
void a5x_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)
{
struct kgsl_device *device = &adreno_dev->dev;
/*
* GPC error is typically the result of mistake SW programming.
* Force GPU fault for this interrupt so that we can debug it
* with help of register dump.
*/
KGSL_DRV_CRIT(device, "RBBM: GPC error\n");
adreno_irqctrl(adreno_dev, 0);
/* Trigger a fault in the dispatcher - this will effect a restart */
adreno_set_gpu_fault(ADRENO_DEVICE(device), ADRENO_SOFT_FAULT);
adreno_dispatcher_schedule(device);
}
#define A5XX_INT_MASK \
((1 << A5XX_INT_RBBM_AHB_ERROR) | \
(1 << A5XX_INT_RBBM_TRANSFER_TIMEOUT) | \
@ -2284,7 +2304,7 @@ static struct adreno_irq_funcs a5xx_irq_funcs[] = {
ADRENO_IRQ_CALLBACK(a5xx_err_callback),
/* 6 - RBBM_ATB_ASYNC_OVERFLOW */
ADRENO_IRQ_CALLBACK(a5xx_err_callback),
ADRENO_IRQ_CALLBACK(a5xx_err_callback), /* 7 - GPC_ERR */
ADRENO_IRQ_CALLBACK(a5x_gpc_err_int_callback), /* 7 - GPC_ERR */
ADRENO_IRQ_CALLBACK(NULL), /* 8 - CP_SW */
ADRENO_IRQ_CALLBACK(a5xx_cp_hw_err_callback), /* 9 - CP_HW_ERROR */
/* 10 - CP_CCU_FLUSH_DEPTH_TS */

12
drivers/gpu/msm/adreno_dispatch.c
View File

@ -2630,18 +2630,6 @@ static void adreno_dispatcher_timer(unsigned long data)
adreno_dispatcher_schedule(device);
}
/**
* adreno_dispatcher_irq_fault() - Trigger a fault in the dispatcher
* @device: Pointer to the KGSL device
*
* Called from an interrupt context this will trigger a fault in the
* dispatcher for the oldest pending command batch
*/
void adreno_dispatcher_irq_fault(struct kgsl_device *device)
{
adreno_set_gpu_fault(ADRENO_DEVICE(device), ADRENO_HARD_FAULT);
adreno_dispatcher_schedule(device);
}
/**
* adreno_dispatcher_start() - activate the dispatcher

1
drivers/gpu/msm/adreno_dispatch.h
View File

@ -131,7 +131,6 @@ void adreno_dispatcher_start(struct kgsl_device *device);
int adreno_dispatcher_init(struct adreno_device *adreno_dev);
void adreno_dispatcher_close(struct adreno_device *adreno_dev);
int adreno_dispatcher_idle(struct adreno_device *adreno_dev);
void adreno_dispatcher_irq_fault(struct kgsl_device *device);
void adreno_dispatcher_stop(struct adreno_device *adreno_dev);
int adreno_dispatcher_queue_cmd(struct adreno_device *adreno_dev,