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arm: Invalidate icache on prefetch abort outside of user mapping on Cortex-A57/72. 

In order to prevent aliasing attacks on the branch predictor,
invalidate the icache on Cortex-A57/72, which has the side effect
of invalidating the BTB. This requires ACTLR[0] to be set to 1
(secure operation).

Change-Id: Ief15d6693d2bff9111e127ea486a6e864f6b35ef
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Signed-off-by: Rajshekar Eashwarappa <reashw@codeaurora.org>
This commit is contained in:
Neeraj Upadhyay 2018-01-16 14:41:20 +05:30 committed by syphyr
parent 3a49aad871
commit 9d0f39c3a1
3 changed files with 8 additions and 0 deletions
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1
arch/arm/include/asm/cp15.h
View File

@ -59,6 +59,7 @@
#define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v)))
#define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__)
#define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
#define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
extern unsigned long cr_alignment; /* defined in entry-armv.S */

2
arch/arm/include/asm/cputype.h
View File

@ -53,6 +53,8 @@
#define ARM_CPU_PART_CORTEX_A5 0xC050
#define ARM_CPU_PART_CORTEX_A15 0xC0F0
#define ARM_CPU_PART_CORTEX_A7 0xC070
#define ARM_CPU_PART_CORTEX_A57 0xd070
#define ARM_CPU_PART_CORTEX_A72 0xd080
#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
#define ARM_CPU_XSCALE_ARCH_V1 0x2000

5
arch/arm/mm/fault.c
View File

@ -421,6 +421,11 @@ do_pabt_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
case ARM_CPU_PART_CORTEX_A8:
write_sysreg(0, BPIALL);
break;
case ARM_CPU_PART_CORTEX_A57:
case ARM_CPU_PART_CORTEX_A72:
write_sysreg(0, ICIALLU);
break;
}
}