msm: devfreq_cpubw: Add devfreq driver for CPU to DDR bandwidth voting
This driver registers itself as a devfreq device that allows devfreq governors to make CPU to DDR IB/AB bandwidth votes. This driver allows the governors to be agnostic of the bandwidth voting APIs, the number of CPU master ports or DDR slave ports, the actual port numbers, the system topology, the available DDR frequencies, etc. Change-Id: If055ddd580afd41f9668b111e6c09a047488b2e0 Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
This commit is contained in:
Saravana Kannan
parent
f0f3dd3bb3
commit
a2dd9de8c7
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@ -0,0 +1,30 @@
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MSM CPU bandwidth device
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cpubw is a device that represents the CPU subsystem master ports in a MSM SoC
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and the related info that is needed to make CPU to DDR bandwidth votes.
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Required properties:
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- compatible: Must be "qcom,cpubw"
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- qcom,cpu-mem-ports: A list of tuples where each tuple consists of a bus
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master (CPU subsystem) port number and a bus slave
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(memory) port number.
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- qcom,bw-tbl: A list of meaningful instantaneous bandwidth values
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(in MB/s) that can be requested from the CPU
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subsystem to DDR. The list of values depend on the
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supported DDR frequencies and the bus widths.
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Example:
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qcom,cpubw {
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compatible = "qcom,cpubw";
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qcom,cpu-mem-ports = <1 512>, <2 512>;
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qcom,bw-tbl =
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< 572 /* 75 MHz */ >,
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< 1144 /* 150 MHz */ >,
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< 1525 /* 200 MHz */ >,
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< 2342 /* 307 MHz */ >,
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< 3509 /* 460 MHz */ >,
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< 4684 /* 614 MHz */ >,
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< 6103 /* 800 MHz */ >,
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< 7102 /* 931 MHz */ >;
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};
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@ -11,6 +11,8 @@ config ARCH_MSM8974
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select MSM_SCM
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select MSM_GPIOMUX
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select MSM_MULTIMEDIA_USE_ION
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select PM_DEVFREQ
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select MSM_DEVFREQ_CPUBW
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select MSM_PIL
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select MSM_SPM_V2
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select MSM_L2_SPM
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@ -66,6 +68,8 @@ config ARCH_APQ8084
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select MSM_RPM_LOG
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select USB_ARCH_HAS_XHCI
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select KRAIT_REGULATOR
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select PM_DEVFREQ
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select MSM_DEVFREQ_CPUBW
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select MSM_PIL
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select ENABLE_VMALLOC_SAVINGS
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select MSM_ULTRASOUND_B
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@ -75,6 +79,8 @@ config ARCH_MPQ8092
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bool "MPQ8092"
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select REGULATOR
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select ARCH_MSM_KRAITMP
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select PM_DEVFREQ
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select MSM_DEVFREQ_CPUBW
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select GPIO_MSM_V3
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select ARM_GIC
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select HAVE_ARM_ARCH_TIMER
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@ -103,6 +109,8 @@ config ARCH_FSM9900
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select MSM_SCM
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select HAVE_ARM_ARCH_TIMER
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select MSM_GPIOMUX
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select PM_DEVFREQ
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select MSM_DEVFREQ_CPUBW
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select MSM_PIL
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select MSM_NATIVE_RESTART
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select REGULATOR
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@ -133,6 +141,8 @@ config ARCH_MSMKRYPTON
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select QMI_ENCDEC
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select MSM_JTAG_MM if CORESIGHT_ETM
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select MSM_CORTEX_A7
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select PM_DEVFREQ
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select MSM_DEVFREQ_CPUBW
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config ARCH_MSM8610
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bool "MSM8610"
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@ -159,6 +169,8 @@ config ARCH_MSM8610
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select MSM_CORTEX_A7
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select CPU_FREQ_MSM
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select CPU_FREQ
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select PM_DEVFREQ
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select MSM_DEVFREQ_CPUBW
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select MSM_PIL
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select MSM_RUN_QUEUE_STATS
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select ARM_HAS_SG_CHAIN
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@ -200,6 +212,8 @@ config ARCH_MSM8226
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select MSM_CORTEX_A7
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select CPU_FREQ_MSM
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select CPU_FREQ
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select PM_DEVFREQ
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select MSM_DEVFREQ_CPUBW
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select MSM_PIL
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select MSM_RUN_QUEUE_STATS
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select ARM_HAS_SG_CHAIN
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@ -224,6 +238,8 @@ config ARCH_MSMSAMARIUM
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select CPU_V7
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select HAVE_ARM_ARCH_TIMER
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select MSM_SCM
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select PM_DEVFREQ
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select MSM_DEVFREQ_CPUBW
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select MSM_PIL
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select MSM_GPIOMUX
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select MSM_SPM_V2
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@ -807,6 +823,19 @@ config MSM_CPU_FREQ_MIN
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endif # CPU_FREQ_MSM
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config MSM_DEVFREQ_CPUBW
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bool "Devfreq device for CPU<->DDR IB/AB BW voting"
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depends on PM_DEVFREQ
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select DEVFREQ_GOV_PERFORMANCE
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select DEVFREQ_GOV_POWERSAVE
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select DEVFREQ_GOV_USERSPACE
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default n
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help
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Different devfreq governors use this devfreq device to make CPU to
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DDR IB/AB bandwidth votes. This driver provides a SoC topology
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agnostic interface to so that some of the devfreq governors can be
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shared across SoCs.
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config MSM_AVS_HW
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bool "Enable Adaptive Voltage Scaling (AVS)"
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default n
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@ -173,6 +173,7 @@ obj-$(CONFIG_MSM_SMCMOD) += smcmod.o
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obj-$(CONFIG_ARCH_MSM8974) += msm_mpmctr.o
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obj-$(CONFIG_MSM_CPR_REGULATOR) += cpr-regulator.o
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obj-$(CONFIG_CPU_FREQ_MSM) += cpufreq.o
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obj-$(CONFIG_MSM_DEVFREQ_CPUBW) += devfreq_cpubw.o
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obj-$(CONFIG_ARCH_RANDOM) += early_random.o
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@ -0,0 +1,218 @@
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/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "cpubw: " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/ktime.h>
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#include <linux/time.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/mutex.h>
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#include <linux/interrupt.h>
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#include <linux/devfreq.h>
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#include <linux/of.h>
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#include <trace/events/power.h>
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#include <mach/msm_bus.h>
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#include <mach/msm_bus_board.h>
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/* Has to be ULL to prevent overflow where this macro is used. */
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#define MBYTE (1ULL << 20)
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#define MAX_PATHS 2
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static struct msm_bus_vectors vectors[MAX_PATHS * 2];
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static struct msm_bus_paths bw_levels[] = {
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{ .vectors = &vectors[0] },
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{ .vectors = &vectors[MAX_PATHS] },
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};
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static struct msm_bus_scale_pdata bw_data = {
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.usecase = bw_levels,
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.num_usecases = ARRAY_SIZE(bw_levels),
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.name = "devfreq_cpubw",
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.active_only = 1,
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};
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static int num_paths;
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static u32 bus_client;
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static int set_bw(int new_ib, int new_ab)
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{
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static int cur_idx, cur_ab, cur_ib;
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int i, ret;
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if (cur_ib == new_ib && cur_ab == new_ab)
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return 0;
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i = (cur_idx + 1) % ARRAY_SIZE(bw_levels);
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bw_levels[i].vectors[0].ib = new_ib * MBYTE;
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bw_levels[i].vectors[0].ab = new_ab / num_paths * MBYTE;
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bw_levels[i].vectors[1].ib = new_ib * MBYTE;
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bw_levels[i].vectors[1].ab = new_ab / num_paths * MBYTE;
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pr_debug("BW MBps: AB: %d IB: %d\n", new_ab, new_ib);
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ret = msm_bus_scale_client_update_request(bus_client, i);
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if (ret) {
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pr_err("bandwidth request failed (%d)\n", ret);
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} else {
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cur_idx = i;
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cur_ib = new_ib;
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cur_ab = new_ab;
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}
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return ret;
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}
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static void find_freq(struct devfreq_dev_profile *p, unsigned long *freq,
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u32 flags)
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{
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int i;
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unsigned long atmost, atleast, f;
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atmost = p->freq_table[0];
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atleast = p->freq_table[p->max_state-1];
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for (i = 0; i < p->max_state; i++) {
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f = p->freq_table[i];
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if (f <= *freq)
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atmost = max(f, atmost);
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if (f >= *freq)
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atleast = min(f, atleast);
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}
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if (flags & DEVFREQ_FLAG_LEAST_UPPER_BOUND)
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*freq = atmost;
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else
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*freq = atleast;
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}
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struct devfreq_dev_profile cpubw_profile;
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static long gov_ab;
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int cpubw_target(struct device *dev, unsigned long *freq, u32 flags)
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{
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find_freq(&cpubw_profile, freq, flags);
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return set_bw(*freq, gov_ab);
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}
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static struct devfreq_governor_data gov_data[] = {
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{ .name = "performance" },
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{ .name = "powersave" },
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{ .name = "userspace" },
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};
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struct devfreq_dev_profile cpubw_profile = {
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.polling_ms = 50,
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.target = cpubw_target,
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.governor_data = gov_data,
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.num_governor_data = ARRAY_SIZE(gov_data),
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};
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#define PROP_PORTS "qcom,cpu-mem-ports"
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#define PROP_TBL "qcom,bw-tbl"
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static int __init cpubw_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct devfreq_dev_profile *p = &cpubw_profile;
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struct devfreq *df;
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u32 *data, ports[MAX_PATHS * 2];
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int ret, len, i;
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if (of_find_property(dev->of_node, PROP_PORTS, &len)) {
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len /= sizeof(ports[0]);
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if (len % 2 || len > ARRAY_SIZE(ports)) {
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dev_err(dev, "Unexpected number of ports\n");
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return -EINVAL;
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}
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ret = of_property_read_u32_array(dev->of_node, PROP_PORTS,
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ports, len);
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if (ret)
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return ret;
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num_paths = len / 2;
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} else {
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return -EINVAL;
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}
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for (i = 0; i < num_paths; i++) {
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bw_levels[0].vectors[i].src = ports[2 * i];
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bw_levels[0].vectors[i].dst = ports[2 * i + 1];
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bw_levels[1].vectors[i].src = ports[2 * i];
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bw_levels[1].vectors[i].dst = ports[2 * i + 1];
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}
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bw_levels[0].num_paths = num_paths;
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bw_levels[1].num_paths = num_paths;
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if (of_find_property(dev->of_node, PROP_TBL, &len)) {
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len /= sizeof(*data);
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data = devm_kzalloc(dev, len * sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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p->freq_table = devm_kzalloc(dev,
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len * sizeof(*p->freq_table),
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GFP_KERNEL);
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if (!p->freq_table)
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return -ENOMEM;
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ret = of_property_read_u32_array(dev->of_node, PROP_TBL,
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data, len);
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if (ret)
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return ret;
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for (i = 0; i < len; i++)
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p->freq_table[i] = data[i];
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p->max_state = len;
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}
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bus_client = msm_bus_scale_register_client(&bw_data);
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if (!bus_client) {
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dev_err(dev, "Unable to register bus client\n");
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return -ENODEV;
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}
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df = devfreq_add_device(dev, &cpubw_profile, "powersave", NULL);
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if (IS_ERR(df)) {
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msm_bus_scale_unregister_client(bus_client);
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return PTR_ERR(df);
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}
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return 0;
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}
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static struct of_device_id match_table[] = {
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{ .compatible = "qcom,cpubw" },
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{}
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};
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static struct platform_driver cpubw_driver = {
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.driver = {
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.name = "cpubw",
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.of_match_table = match_table,
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.owner = THIS_MODULE,
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},
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};
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static int __init cpubw_init(void)
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{
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platform_driver_probe(&cpubw_driver, cpubw_probe);
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return 0;
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}
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device_initcall(cpubw_init);
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MODULE_DESCRIPTION("CPU DDR bandwidth voting driver MSM CPUs");
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MODULE_LICENSE("GPL v2");
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