edac: cortex_arm64: Use device tree property for CTI PMU Workaround

The CTI PMU workaround is enabled by default. Use a device tree property
to decide if the workaround needs to be applied or not.

Change-Id: Iaa847b7309d204d41c0ca53984964f3b238e0427
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>

Documentation/devicetree/bindings/cache/arm64_cache_erp.txt

@@ -21,6 +21,7 @@ Required properties:
 Optional properties:
 - reg: Should contain physical address of the CCI register space
 - reg-names: Should contain 'cci'. Must be present if 'reg' property is present
+- qcom,apply-cti-pmu-wa: Indicates if the driver needs to apply the CTI PMU Workaround. Relevant for 8994V1.
 
 Example:
 	cpu_cache_erp {

arch/arm/boot/dts/qcom/msm8994-v1.dtsi

@@ -22,4 +22,26 @@
 	model = "Qualcomm Technologies, Inc. MSM 8994";
 	compatible = "qcom,msm8994";
 	qcom,msm-id = <207 0x10000>;
+
+};
+
+&soc {
+	arm64-cpu-erp@f9100000 {
+		compatible = "arm,arm64-cpu-erp";
+		reg = <0xf9100000 0x1000>;
+		reg-names = "cci";
+		interrupts = <0 328 0>,
+			     <0 329 0>,
+			     <0 330 0>,
+			     <0 331 0>,
+			     <0 22 0>,
+			     <1 14 0>;
+		interrupt-names = "pri-dbe-irq",
+				  "sec-dbe-irq",
+				  "pri-ext-irq",
+				  "sec-ext-irq",
+				  "cci-irq",
+				  "sbe-irq";
+		qcom,apply-cti-pmu-wa;
+	};
 };

arch/arm/boot/dts/qcom/msm8994-v2.dtsi

@@ -24,6 +24,26 @@
 	qcom,msm-id = <207 0x20000>;
 };
 
+&soc {
+	arm64-cpu-erp@f9100000 {
+		compatible = "arm,arm64-cpu-erp";
+		reg = <0xf9100000 0x1000>;
+		reg-names = "cci";
+		interrupts = <0 328 0>,
+			     <0 329 0>,
+			     <0 330 0>,
+			     <0 331 0>,
+			     <0 22 0>,
+			     <1 7 0>;
+		interrupt-names = "pri-dbe-irq",
+				  "sec-dbe-irq",
+				  "pri-ext-irq",
+				  "sec-ext-irq",
+				  "cci-irq",
+				  "sbe-irq";
+	};
+};
+
 /* GPU overrides */
 &msm_gpu {
 	/* Updated chip ID */

arch/arm/boot/dts/qcom/msm8994.dtsi

@@ -264,24 +264,6 @@
 	ranges = <0 0 0 0xffffffff>;
 	compatible = "simple-bus";
 
-	arm64-cpu-erp@f9100000 {
-		compatible = "arm,arm64-cpu-erp";
-		reg = <0xf9100000 0x1000>;
-		reg-names = "cci";
-		interrupts = <0 328 0>,
-			     <0 329 0>,
-			     <0 330 0>,
-			     <0 331 0>,
-			     <0 22 0>,
-			     <1 14 0>;
-		interrupt-names = "pri-dbe-irq",
-				  "sec-dbe-irq",
-				  "pri-ext-irq",
-				  "sec-ext-irq",
-				  "cci-irq",
-				  "sbe-irq";
-	};
-
 	acc0:clock-controller@f908b004 {
 		compatible = "qcom,arm-cortex-acc";
 		reg = <0xf9070000 0x1000>,

drivers/edac/cortex_arm64_edac.c

@@ -114,6 +114,7 @@ struct erp_drvdata {
 	struct notifier_block nb_pm;
 	struct notifier_block nb_cpu;
 	struct work_struct work;
+	int apply_cti_pmu_wa;
 };
 
 static struct erp_drvdata *abort_handler_drvdata;
@@ -670,9 +671,11 @@ static irqreturn_t arm64_sbe_handler(int irq, void *drvdata)
 	int overflow = 0, ret = IRQ_HANDLED;
 	int cpu = raw_smp_processor_id();
 
-	msm_cti_pmu_irq_ack(cpu);
-
 	errdata.drv = *((struct erp_drvdata **)drvdata);
+
+	if (errdata.drv->apply_cti_pmu_wa)
+		msm_cti_pmu_irq_ack(cpu);
+
 	cntr = errdata.drv->mem_perf_counter;
 	arm64_pmu_lock(NULL, &flags);
 	pmovsr = arm64pmu_getreset_flags(cntr);
@@ -868,14 +871,19 @@ static int arm64_cpu_erp_probe(struct platform_device *pdev)
 		goto out_irq;
 	}
 
+	drv->apply_cti_pmu_wa = of_property_read_bool(pdev->dev.of_node,
+						"qcom,apply-cti-pmu-wa");
+
 	drv->nb_pm.notifier_call = arm64_pmu_cpu_pm_notify;
 	drv->mem_perf_counter = arm64_pmu_get_last_counter();
 	cpu_pm_register_notifier(&(drv->nb_pm));
 	drv->nb_cpu.notifier_call = msm_cti_pmu_wa_cpu_notify;
 	register_cpu_notifier(&drv->nb_cpu);
 	arm64_pmu_irq_handled_externally();
-	schedule_on_each_cpu(msm_enable_cti_pmu_workaround);
-	INIT_WORK(&drv->work, msm_enable_cti_pmu_workaround);
+	if (drv->apply_cti_pmu_wa) {
+		schedule_on_each_cpu(msm_enable_cti_pmu_workaround);
+		INIT_WORK(&drv->work, msm_enable_cti_pmu_workaround);
+	}
 	on_each_cpu(sbe_enable_event, drv, 1);
 	on_each_cpu(arm64_enable_pmu_irq, &sbe_irq, 1);