drm/radeon/kms: make atombios_dig_transmitter_setup() version based
Use the table version to determine which params to use. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
58cdcb8bbe
commit
a3b0829454
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@ -772,6 +772,11 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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igp_lane_info = dig_connector->igp_lane_info;
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}
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if (encoder->crtc) {
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
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pll_id = radeon_crtc->pll_id;
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}
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/* no dig encoder assigned */
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if (dig_encoder == -1)
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return;
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@ -798,44 +803,202 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
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return;
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args.v1.ucAction = action;
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if (action == ATOM_TRANSMITTER_ACTION_INIT) {
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args.v1.usInitInfo = cpu_to_le16(connector_object_id);
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} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
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args.v1.asMode.ucLaneSel = lane_num;
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args.v1.asMode.ucLaneSet = lane_set;
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} else {
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if (is_dp)
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args.v1.usPixelClock =
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cpu_to_le16(dp_clock / 10);
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else if (radeon_encoder->pixel_clock > 165000)
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args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
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else
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args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
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}
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if (ASIC_IS_DCE4(rdev)) {
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if (is_dp)
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args.v3.ucLaneNum = dp_lane_count;
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else if (radeon_encoder->pixel_clock > 165000)
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args.v3.ucLaneNum = 8;
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else
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args.v3.ucLaneNum = 4;
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switch (frev) {
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case 1:
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switch (crev) {
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case 1:
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args.v1.ucAction = action;
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if (action == ATOM_TRANSMITTER_ACTION_INIT) {
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args.v1.usInitInfo = cpu_to_le16(connector_object_id);
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} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
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args.v1.asMode.ucLaneSel = lane_num;
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args.v1.asMode.ucLaneSet = lane_set;
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} else {
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if (is_dp)
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args.v1.usPixelClock =
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cpu_to_le16(dp_clock / 10);
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else if (radeon_encoder->pixel_clock > 165000)
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args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
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else
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args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
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}
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if (dig->linkb)
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args.v3.acConfig.ucLinkSel = 1;
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if (dig_encoder & 1)
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args.v3.acConfig.ucEncoderSel = 1;
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args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
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/* Select the PLL for the PHY
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* DP PHY should be clocked from external src if there is
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* one.
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*/
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if (encoder->crtc) {
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
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pll_id = radeon_crtc->pll_id;
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}
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if (dig_encoder)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
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else
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
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if (ASIC_IS_DCE5(rdev)) {
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if ((rdev->flags & RADEON_IS_IGP) &&
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(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
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if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
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if (igp_lane_info & 0x1)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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else if (igp_lane_info & 0x2)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
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else if (igp_lane_info & 0x4)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
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else if (igp_lane_info & 0x8)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
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} else {
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if (igp_lane_info & 0x3)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
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else if (igp_lane_info & 0xc)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
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}
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}
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if (dig->linkb)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
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else
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
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if (is_dp)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
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else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
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if (dig->coherent_mode)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
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if (radeon_encoder->pixel_clock > 165000)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
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}
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break;
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case 2:
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args.v2.ucAction = action;
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if (action == ATOM_TRANSMITTER_ACTION_INIT) {
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args.v2.usInitInfo = cpu_to_le16(connector_object_id);
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} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
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args.v2.asMode.ucLaneSel = lane_num;
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args.v2.asMode.ucLaneSet = lane_set;
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} else {
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if (is_dp)
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args.v2.usPixelClock =
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cpu_to_le16(dp_clock / 10);
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else if (radeon_encoder->pixel_clock > 165000)
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args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
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else
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args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
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}
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args.v2.acConfig.ucEncoderSel = dig_encoder;
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if (dig->linkb)
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args.v2.acConfig.ucLinkSel = 1;
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v2.acConfig.ucTransmitterSel = 0;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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args.v2.acConfig.ucTransmitterSel = 1;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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args.v2.acConfig.ucTransmitterSel = 2;
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break;
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}
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if (is_dp) {
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args.v2.acConfig.fCoherentMode = 1;
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args.v2.acConfig.fDPConnector = 1;
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} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
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if (dig->coherent_mode)
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args.v2.acConfig.fCoherentMode = 1;
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if (radeon_encoder->pixel_clock > 165000)
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args.v2.acConfig.fDualLinkConnector = 1;
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}
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break;
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case 3:
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args.v3.ucAction = action;
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if (action == ATOM_TRANSMITTER_ACTION_INIT) {
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args.v3.usInitInfo = cpu_to_le16(connector_object_id);
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} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
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args.v3.asMode.ucLaneSel = lane_num;
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args.v3.asMode.ucLaneSet = lane_set;
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} else {
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if (is_dp)
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args.v3.usPixelClock =
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cpu_to_le16(dp_clock / 10);
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else if (radeon_encoder->pixel_clock > 165000)
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args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
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else
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args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
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}
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if (is_dp)
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args.v3.ucLaneNum = dp_lane_count;
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else if (radeon_encoder->pixel_clock > 165000)
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args.v3.ucLaneNum = 8;
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else
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args.v3.ucLaneNum = 4;
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if (dig->linkb)
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args.v3.acConfig.ucLinkSel = 1;
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if (dig_encoder & 1)
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args.v3.acConfig.ucEncoderSel = 1;
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/* Select the PLL for the PHY
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* DP PHY should be clocked from external src if there is
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* one.
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*/
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/* On DCE4, if there is an external clock, it generates the DP ref clock */
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if (is_dp && rdev->clock.dp_extclk)
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args.v3.acConfig.ucRefClkSource = 2; /* external src */
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else
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args.v3.acConfig.ucRefClkSource = pll_id;
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v3.acConfig.ucTransmitterSel = 0;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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args.v3.acConfig.ucTransmitterSel = 1;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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args.v3.acConfig.ucTransmitterSel = 2;
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break;
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}
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if (is_dp)
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args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
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else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
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if (dig->coherent_mode)
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args.v3.acConfig.fCoherentMode = 1;
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if (radeon_encoder->pixel_clock > 165000)
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args.v3.acConfig.fDualLinkConnector = 1;
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}
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break;
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case 4:
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args.v4.ucAction = action;
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if (action == ATOM_TRANSMITTER_ACTION_INIT) {
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args.v4.usInitInfo = cpu_to_le16(connector_object_id);
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} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
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args.v4.asMode.ucLaneSel = lane_num;
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args.v4.asMode.ucLaneSet = lane_set;
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} else {
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if (is_dp)
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args.v4.usPixelClock =
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cpu_to_le16(dp_clock / 10);
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else if (radeon_encoder->pixel_clock > 165000)
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args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
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else
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args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
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}
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if (is_dp)
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args.v4.ucLaneNum = dp_lane_count;
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else if (radeon_encoder->pixel_clock > 165000)
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args.v4.ucLaneNum = 8;
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else
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args.v4.ucLaneNum = 4;
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if (dig->linkb)
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args.v4.acConfig.ucLinkSel = 1;
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if (dig_encoder & 1)
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args.v4.acConfig.ucEncoderSel = 1;
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/* Select the PLL for the PHY
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* DP PHY should be clocked from external src if there is
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* one.
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*/
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/* On DCE5 DCPLL usually generates the DP ref clock */
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if (is_dp) {
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if (rdev->clock.dp_extclk)
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@ -844,100 +1007,36 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
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} else
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args.v4.acConfig.ucRefClkSource = pll_id;
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} else {
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/* On DCE4, if there is an external clock, it generates the DP ref clock */
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if (is_dp && rdev->clock.dp_extclk)
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args.v3.acConfig.ucRefClkSource = 2; /* external src */
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else
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args.v3.acConfig.ucRefClkSource = pll_id;
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}
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v3.acConfig.ucTransmitterSel = 0;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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args.v3.acConfig.ucTransmitterSel = 1;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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args.v3.acConfig.ucTransmitterSel = 2;
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break;
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}
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if (is_dp)
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args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
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else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
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if (dig->coherent_mode)
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args.v3.acConfig.fCoherentMode = 1;
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if (radeon_encoder->pixel_clock > 165000)
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args.v3.acConfig.fDualLinkConnector = 1;
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}
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} else if (ASIC_IS_DCE32(rdev)) {
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args.v2.acConfig.ucEncoderSel = dig_encoder;
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if (dig->linkb)
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args.v2.acConfig.ucLinkSel = 1;
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v2.acConfig.ucTransmitterSel = 0;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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args.v2.acConfig.ucTransmitterSel = 1;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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args.v2.acConfig.ucTransmitterSel = 2;
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break;
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}
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if (is_dp) {
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args.v2.acConfig.fCoherentMode = 1;
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args.v2.acConfig.fDPConnector = 1;
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} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
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if (dig->coherent_mode)
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args.v2.acConfig.fCoherentMode = 1;
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if (radeon_encoder->pixel_clock > 165000)
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args.v2.acConfig.fDualLinkConnector = 1;
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}
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} else {
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args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
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if (dig_encoder)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
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else
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
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if ((rdev->flags & RADEON_IS_IGP) &&
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(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
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if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
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if (igp_lane_info & 0x1)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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else if (igp_lane_info & 0x2)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
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else if (igp_lane_info & 0x4)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
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else if (igp_lane_info & 0x8)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
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} else {
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if (igp_lane_info & 0x3)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
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else if (igp_lane_info & 0xc)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v4.acConfig.ucTransmitterSel = 0;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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args.v4.acConfig.ucTransmitterSel = 1;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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args.v4.acConfig.ucTransmitterSel = 2;
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break;
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}
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}
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if (dig->linkb)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
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else
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
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if (is_dp)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
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else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
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if (dig->coherent_mode)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
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if (radeon_encoder->pixel_clock > 165000)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
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if (is_dp)
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args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
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else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
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if (dig->coherent_mode)
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args.v4.acConfig.fCoherentMode = 1;
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if (radeon_encoder->pixel_clock > 165000)
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args.v4.acConfig.fDualLinkConnector = 1;
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}
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break;
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default:
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DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
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break;
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}
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break;
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default:
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DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
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break;
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}
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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