mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-09-22 04:15:02 +00:00
ARM: dts: msm: Merge RPM clocks with GCC clock controller on MDM9640
In HW, the rpm clocks reside in the GCC clock controller. The separation of rpm and gcc clocks is from SW perspective. However, this separation is not required for the clock definition. So merge the rpm clocks with the GCC clock controller. Change-Id: I0be67855fc67c9d4016cdd8f11c174018855d14d Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
This commit is contained in:
Tianyi Gou
parent
9267628939
commit
a4108d42a2
7 changed files with 89 additions and 104 deletions
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@ -1,4 +1,4 @@
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -30,8 +30,8 @@
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qcom,bus-type = <2>;
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qcom,bypass-qos-prg;
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clock-names = "bus_clk", "bus_a_clk";
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clocks = <&clock_rpm clk_bimc_msmbus_clk>,
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<&clock_rpm clk_bimc_msmbus_a_clk>;
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clocks = <&clock_gcc clk_bimc_msmbus_clk>,
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<&clock_gcc clk_bimc_msmbus_a_clk>;
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coresight-id = <55>;
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coresight-name = "coresight-bimc";
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@ -51,8 +51,8 @@
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qcom,base-offset = <0x7000>;
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qcom,qos-delta = <0x1000>;
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clock-names = "bus_clk", "bus_a_clk";
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clocks = <&clock_rpm clk_snoc_msmbus_clk>,
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<&clock_rpm clk_snoc_msmbus_a_clk>;
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clocks = <&clock_gcc clk_snoc_msmbus_clk>,
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<&clock_gcc clk_snoc_msmbus_a_clk>;
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};
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fab_snoc: fab-snoc {
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@ -65,8 +65,8 @@
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qcom,base-offset = <0x7000>;
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qcom,qos-off = <0x1000>;
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clock-names = "bus_clk", "bus_a_clk";
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clocks = <&clock_rpm clk_pcnoc_msmbus_clk>,
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<&clock_rpm clk_pcnoc_msmbus_a_clk>;
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clocks = <&clock_gcc clk_pcnoc_msmbus_clk>,
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<&clock_gcc clk_pcnoc_msmbus_a_clk>;
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coresight-id = <50>;
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coresight-name = "coresight-snoc";
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@ -14,13 +14,6 @@
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#include <dt-bindings/clock/msm-clocks-hwio-9640.h>
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&soc {
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clock_rpm: qcom,rpmcc@1800000 {
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compatible = "qcom,msm-clock-controller";
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reg = <0x1800000 0x80000>;
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reg-names = "cc-base";
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#clock-cells = <1>;
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};
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clock_a7pll: qcom,a7pll@0xB008018 {
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compatible = "qcom,msm-clock-controller";
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reg = <0xB008018 0x9020>;
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@ -28,7 +21,7 @@
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#clock-cells = <1>;
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clock-names = "a7_xo_a";
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clocks = <&clock_rpm clk_xo_a_clk_src>;
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clocks = <&clock_gcc clk_xo_a>;
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qcom,regulator-names = "a7pll_vdd_dig";
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a7pll_vdd_dig-supply = <&pmd9635_s5_corner_ao>;
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@ -49,10 +42,8 @@
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reg = <0x1800000 0x80000>;
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reg-names = "cc-base";
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#clock-cells = <1>;
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clock-names = "xo", "xo_a", "a7_debug_clk";
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clocks = <&clock_rpm clk_xo_clk_src>,
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<&clock_rpm clk_xo_a_clk_src>,
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<&clock_a7pll clk_a7_debug_mux>;
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clock-names = "a7_debug_clk";
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clocks = <&clock_a7pll clk_a7_debug_mux>;
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qcom,regulator-names = "gcc_vdd_dig";
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gcc_vdd_dig-supply = <&pmd9635_s5_corner>;
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@ -70,22 +61,22 @@
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};
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};
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&clock_rpm {
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xo_clk_src: xo_clk_src {
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&clock_gcc {
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xo: xo {
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compatible = "qcom,rpm-branch-clk";
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qcom,res-type = "clk0";
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qcom,res-id = <0>;
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qcom,key = "Enable";
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qcom,rpm-peer = <&xo_a_clk_src>;
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qcom,rpm-peer = <&xo_a>;
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qcom,rcg-init-rate = <19200000>;
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};
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xo_a_clk_src: xo_a_clk_src {
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xo_a: xo_a {
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compatible = "qcom,rpm-branch-a-clk";
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qcom,res-type = "clk0";
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qcom,res-id = <0>;
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qcom,key = "Enable";
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qcom,rpm-peer = <&xo_clk_src>;
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qcom,rpm-peer = <&xo>;
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qcom,rcg-init-rate = <19200000>;
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};
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@ -120,7 +111,7 @@
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cxo_dwc3_clk: cxo_dwc3_clk {
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compatible = "qcom,dummy-clk";
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qcom,parent = <&xo_clk_src>;
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qcom,parent = <&xo>;
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};
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ipa_clk: ipa_clk {
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@ -291,18 +282,6 @@
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qcom,parent = <&ce_clk>;
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qcom,config-rate = <85710000>;
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};
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};
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&clock_gcc {
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xo: xo {
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compatible = "qcom,ext-clk";
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qcom,clock-names = "xo";
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};
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xo_a: xo_a {
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compatible = "qcom,ext-clk";
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qcom,clock-names = "xo_a";
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};
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gcc_a7_debug_clk: gcc_a7_debug_clk {
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compatible = "qcom,ext-clk";
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@ -1215,7 +1194,10 @@
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qcom,en-offset = <GCC_GCC_DEBUG_CLK_CTL>;
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qcom,en-mask = <0x10000>;
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qcom,parents =
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<0x0000 &snoc_clk>,
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<0x0001 &gcc_sys_noc_usb3_axi_clk>,
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<0x0008 &pcnoc_clk>,
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<0x0042 &qdss_clk>,
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<0x0050 &gcc_apss_tcu_clk>,
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<0x005b &gcc_smmu_cfg_clk>,
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<0x0068 &gcc_sdcc1_apps_clk>,
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@ -1237,11 +1219,15 @@
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<0x00d2 &gcc_pdm2_clk>,
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<0x00d8 &gcc_prng_ahb_clk>,
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<0x00f8 &gcc_boot_rom_ahb_clk>,
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<0x0138 &ce_clk>,
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<0x0155 &bimc_clk>,
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<0x016A &gcc_a7_debug_clk>,
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<0x0203 &gcc_usb3_axi_tbu_clk>,
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<0x0204 &gcc_pcie_axi_tbu_clk>,
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<0x0208 &pcie_pipe_clk>,
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<0x0210 &usb3_phy_wrapper_gcc_usb3_pipe_clk>,
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<0x0218 &ipa_clk>,
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<0x0220 &qpic_clk>,
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<0x0230 &gcc_usb30_master_clk>,
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<0x0231 &gcc_usb30_sleep_clk>,
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<0x0232 &gcc_usb30_mock_utmi_clk>,
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@ -1,4 +1,4 @@
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -26,8 +26,8 @@
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coresight-nr-inports = <1>;
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coresight-ctis = <&cti0 &cti8>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -62,8 +62,8 @@
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qcom,vdd-io-voltage-level = <2950000 2950000>;
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qcom,vdd-io-current-level = <200 50000>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -79,8 +79,8 @@
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coresight-child-list = <&tmc_etr &tpiu>;
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coresight-child-ports = <0 0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -98,8 +98,8 @@
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coresight-default-sink;
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coresight-ctis = <&cti0 &cti8>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -115,8 +115,8 @@
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coresight-child-list = <&tmc_etf>;
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coresight-child-ports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -133,8 +133,8 @@
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coresight-child-list = <&funnel_in0>;
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coresight-child-ports = <7>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -150,8 +150,8 @@
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coresight-child-list = <&funnel_in0>;
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coresight-child-ports = <4>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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coresight-etm-cpu = <&CPU0>;
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@ -190,8 +190,8 @@
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qcom,blk-size = <1>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -204,8 +204,8 @@
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coresight-name = "coresight-cti0";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -218,8 +218,8 @@
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coresight-name = "coresight-cti1";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -232,8 +232,8 @@
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coresight-name = "coresight-cti2";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -246,8 +246,8 @@
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coresight-name = "coresight-cti3";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -260,8 +260,8 @@
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coresight-name = "coresight-cti4";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -274,8 +274,8 @@
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coresight-name = "coresight-cti5";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -288,8 +288,8 @@
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coresight-name = "coresight-cti6";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -302,8 +302,8 @@
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coresight-name = "coresight-cti7";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -316,8 +316,8 @@
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coresight-name = "coresight-cti8";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -333,8 +333,8 @@
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qcom,cti-save;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -347,8 +347,8 @@
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coresight-name = "coresight-cti-modem-cpu0";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -361,8 +361,8 @@
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coresight-name = "coresight-cti-rpm-cpu0";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -392,8 +392,8 @@
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coresight-name = "coresight-hwevent";
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coresight-nr-inports = <0>;
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clocks = <&clock_rpm clk_qdss_clk>,
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<&clock_rpm clk_qdss_a_clk>;
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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};
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@ -1,4 +1,4 @@
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
|
||||
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
|
|
@ -30,7 +30,7 @@
|
|||
avdd-supply = <&pmd9635_l12>;
|
||||
|
||||
clock-names = "core_a_clk";
|
||||
clocks = <&clock_rpm clk_qpic_a_clk>;
|
||||
clocks = <&clock_gcc clk_qpic_a_clk>;
|
||||
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -110,7 +110,7 @@
|
|||
<0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
|
||||
reg-names = "vmpm", "ipc";
|
||||
interrupts = <0 171 1>;
|
||||
clocks = <&clock_rpm clk_xo_clk_src>;
|
||||
clocks = <&clock_gcc clk_xo>;
|
||||
clock-names = "xo";
|
||||
|
||||
qcom,ipc-bit-offset = <1>;
|
||||
|
|
|
|||
|
|
@ -282,7 +282,7 @@
|
|||
qcom,ee = <0>;
|
||||
qcom,use-ipa-tethering-bridge;
|
||||
clock-names = "core_clk";
|
||||
clocks = <&clock_rpm clk_ipa_clk>;
|
||||
clocks = <&clock_gcc clk_ipa_clk>;
|
||||
};
|
||||
|
||||
qcom,rmnet-ipa {
|
||||
|
|
@ -448,7 +448,7 @@
|
|||
<45 512 500 800>;
|
||||
|
||||
clocks = <&clock_gcc clk_gcc_pcie_pipe_clk>,
|
||||
<&clock_rpm clk_ln_bb_clk>,
|
||||
<&clock_gcc clk_ln_bb_clk>,
|
||||
<&clock_gcc clk_gcc_pcie_sleep_clk>,
|
||||
<&clock_gcc clk_gcc_pcie_cfg_ahb_clk>,
|
||||
<&clock_gcc clk_gcc_pcie_axi_mstr_clk>,
|
||||
|
|
@ -774,8 +774,8 @@
|
|||
|
||||
qcom,coresight-jtagmm-cpu = <&CPU0>;
|
||||
|
||||
clocks = <&clock_rpm clk_qdss_clk>,
|
||||
<&clock_rpm clk_qdss_a_clk>;
|
||||
clocks = <&clock_gcc clk_qdss_clk>,
|
||||
<&clock_gcc clk_qdss_a_clk>;
|
||||
clock-names = "core_clk", "core_a_clk";
|
||||
};
|
||||
|
||||
|
|
@ -798,7 +798,7 @@
|
|||
<91 512 400000 800000>;
|
||||
|
||||
clock-names = "core_clk";
|
||||
clocks = <&clock_rpm clk_qpic_clk>;
|
||||
clocks = <&clock_gcc clk_qpic_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -858,8 +858,8 @@
|
|||
<&clock_gcc clk_gcc_sys_noc_usb3_axi_clk>,
|
||||
<&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
|
||||
<&clock_gcc clk_gcc_usb30_sleep_clk>,
|
||||
<&clock_rpm clk_ln_bb_clk>,
|
||||
<&clock_rpm clk_cxo_dwc3_clk>;
|
||||
<&clock_gcc clk_ln_bb_clk>,
|
||||
<&clock_gcc clk_cxo_dwc3_clk>;
|
||||
|
||||
clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
|
||||
"ref_clk", "xo";
|
||||
|
|
@ -900,7 +900,7 @@
|
|||
qcom,qusb-tune = <0xa08391d5>;
|
||||
phy_type = "utmi";
|
||||
|
||||
clocks = <&clock_rpm clk_ln_bb_clk>,
|
||||
clocks = <&clock_gcc clk_ln_bb_clk>,
|
||||
<&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>,
|
||||
<&clock_gcc clk_gcc_qusb2a_phy_reset>;
|
||||
|
||||
|
|
@ -1331,10 +1331,10 @@
|
|||
<47 512 0 0>,
|
||||
<47 512 3936000 393600>;
|
||||
clocks =
|
||||
<&clock_rpm clk_qcedev_ce_clk>,
|
||||
<&clock_rpm clk_qcedev_ce_clk>,
|
||||
<&clock_rpm clk_qcedev_ce_clk>,
|
||||
<&clock_rpm clk_qcedev_ce_clk>;
|
||||
<&clock_gcc clk_qcedev_ce_clk>,
|
||||
<&clock_gcc clk_qcedev_ce_clk>,
|
||||
<&clock_gcc clk_qcedev_ce_clk>,
|
||||
<&clock_gcc clk_qcedev_ce_clk>;
|
||||
clock-names = "core_clk", "iface_clk",
|
||||
"bus_clk","core_clk_src";
|
||||
};
|
||||
|
|
@ -1356,10 +1356,10 @@
|
|||
<47 512 0 0>,
|
||||
<47 512 3936000 393600>;
|
||||
clocks =
|
||||
<&clock_rpm clk_qcedev_ce_clk>,
|
||||
<&clock_rpm clk_qcedev_ce_clk>,
|
||||
<&clock_rpm clk_qcedev_ce_clk>,
|
||||
<&clock_rpm clk_qcedev_ce_clk>;
|
||||
<&clock_gcc clk_qcedev_ce_clk>,
|
||||
<&clock_gcc clk_qcedev_ce_clk>,
|
||||
<&clock_gcc clk_qcedev_ce_clk>,
|
||||
<&clock_gcc clk_qcedev_ce_clk>;
|
||||
clock-names = "core_clk", "iface_clk",
|
||||
"bus_clk","core_clk_src";
|
||||
};
|
||||
|
|
@ -1373,7 +1373,7 @@
|
|||
reg-names = "qdsp6_base", "halt_base", "rmb_base",
|
||||
"restart_reg";
|
||||
|
||||
clocks = <&clock_rpm clk_xo_clk_src>,
|
||||
clocks = <&clock_gcc clk_xo>,
|
||||
<&clock_gcc clk_gcc_mss_cfg_ahb_clk>,
|
||||
<&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>,
|
||||
<&clock_gcc clk_gcc_boot_rom_ahb_clk>,
|
||||
|
|
|
|||
|
|
@ -13,9 +13,9 @@
|
|||
#ifndef __MSM_CLOCKS_9640_H
|
||||
#define __MSM_CLOCKS_9640_H
|
||||
|
||||
/* clock_rpm controlled clocks */
|
||||
#define clk_xo_clk_src &xo_clk_src
|
||||
#define clk_xo_a_clk_src &xo_a_clk_src
|
||||
/* clock_gcc controlled clocks */
|
||||
#define clk_xo &xo
|
||||
#define clk_xo_a &xo_a
|
||||
#define clk_bimc_clk &bimc_clk
|
||||
#define clk_bimc_a_clk &bimc_a_clk
|
||||
#define clk_bimc_msmbus_clk &bimc_msmbus_clk
|
||||
|
|
@ -41,7 +41,6 @@
|
|||
#define clk_qcedev_ce_clk &qcedev_ce_clk
|
||||
#define clk_qcrypto_ce_clk &qcrypto_ce_clk
|
||||
|
||||
/* clock_gcc controlled clocks */
|
||||
#define clk_gpll0 &gpll0
|
||||
#define clk_gpll0_ao &gpll0_ao
|
||||
#define clk_gpll0_out_main &gpll0_out_main
|
||||
|
|
|
|||
Loading…
Reference in a new issue