mmc: msm_sdcc: Remove support for legacy msm_sdcc driver
Qualcomm's Secure Digitial Host Controller supports the standard host controller interface (SDHCI). Remove msm_sdcc driver that supports MCI interface. Change-Id: Id6564330cf9a089b08f9c5ecbb5344d5bfc5ee5b Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This commit is contained in:
Venkat Gopalakrishnan
parent
1fb7bef3ea
commit
a9f49f2668
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@ -1029,8 +1029,6 @@ M: Bryan Huntsman <bryanh@codeaurora.org>
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L: linux-arm-msm@vger.kernel.org
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F: arch/arm/mach-msm/
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F: drivers/video/msm/
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F: drivers/mmc/host/msm_sdcc.c
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F: drivers/mmc/host/msm_sdcc.h
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F: drivers/tty/serial/msm_serial.h
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F: drivers/tty/serial/msm_serial.c
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F: drivers/*/pm8???-*
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@ -104,6 +104,19 @@ config MMC_SDHCI_PLTFM
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If unsure, say N.
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config MMC_SDHCI_MSM
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tristate "Qualcomm SDHCI Controller Support"
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depends on ARCH_MSM
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depends on MMC_SDHCI_PLTFM
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help
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This selects the Secure Digital Host Controller Interface (SDHCI)
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support present in MSM SOCs from Qualcomm. The controller
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supports SD/MMC/SDIO devices.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_SDHCI_OF_ESDHC
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tristate "SDHCI OF support for the Freescale eSDHC controller"
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depends on MMC_SDHCI_PLTFM
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@ -311,14 +324,6 @@ config MMC_ATMELMCI
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If unsure, say N.
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config MMC_MSM
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tristate "Qualcomm SDCC Controller Support"
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depends on MMC && ARCH_MSM
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help
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This provides support for the SD/MMC cell found in the
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MSM and QSD SOCs from Qualcomm. The controller also has
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support for SDIO devices.
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config MMC_MXC
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tristate "Freescale i.MX21/27/31 or MPC512x Multimedia Card support"
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depends on ARCH_MXC || PPC_MPC512x
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@ -458,114 +463,6 @@ config MMC_SDRICOH_CS
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config MMC_TMIO_CORE
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tristate
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config MMC_SDHCI_MSM
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tristate "Qualcomm SDHCI Controller Support"
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depends on ARCH_MSM
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depends on MMC_SDHCI_PLTFM
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help
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This selects the Secure Digital Host Controller Interface (SDHCI)
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support present in MSM SOCs from Qualcomm. The controller
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supports SD/MMC/SDIO devices.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_MSM
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tristate "Qualcomm SDCC Controller Support"
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depends on MMC && ARCH_MSM
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help
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This provides support for the SD/MMC cell found in the
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MSM and QSD SOCs from Qualcomm.
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config MMC_MSM_SDC1_SUPPORT
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boolean "Qualcomm SDC1 support"
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depends on MMC_MSM
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default y
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help
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Select Y to enable Slot 1.
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config MMC_MSM_SDC1_8_BIT_SUPPORT
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boolean "Qualcomm SDC1 8bit support"
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depends on MMC_MSM_SDC1_SUPPORT
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default n
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help
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Select Y to enable 8bit support for Slot 1.
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config MMC_MSM_SDC2_SUPPORT
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boolean "Qualcomm SDC2 support"
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depends on MMC_MSM
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default y
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help
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Select Y to enable Slot 2.
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config MMC_MSM_SDC2_8_BIT_SUPPORT
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boolean "Qualcomm SDC2 8bit support"
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depends on MMC_MSM_SDC2_SUPPORT
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default n
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help
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Select Y to enable 8bit support for Slot 2.
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config MMC_MSM_SDC3_SUPPORT
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boolean "Qualcomm SDC3 support"
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depends on MMC_MSM
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default n
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help
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Select Y to enable Slot 3.
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config MMC_MSM_SDC3_POLLING
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boolean "Qualcomm SDC3 support"
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depends on MMC_MSM
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config MMC_MSM_SDC3_8_BIT_SUPPORT
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boolean "Qualcomm SDC3 8bit support"
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depends on MMC_MSM_SDC3_SUPPORT
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default n
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help
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Select Y to enable 8bit support for Slot 3.
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config MMC_MSM_SDC3_WP_SUPPORT
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boolean "Qualcomm SDC3 write protection support"
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depends on MMC_MSM_SDC3_SUPPORT
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default n
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help
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Select Y to enable write protection support for Slot 3.
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config MMC_MSM_SDC4_SUPPORT
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boolean "Qualcomm SDC4 support"
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depends on MMC_MSM
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default n
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help
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Select Y to enable Slot 4.
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config MMC_MSM_SDC4_8_BIT_SUPPORT
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boolean "Qualcomm SDC4 8bit support"
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depends on MMC_MSM_SDC4_SUPPORT
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default n
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help
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Select Y to enable 8bit support for Slot 4.
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config MMC_MSM_SDC5_SUPPORT
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boolean "Qualcomm SDC5 support"
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depends on MMC_MSM
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default n
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help
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Select Y to enable Slot 5.
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config MMC_MSM_SDC5_8_BIT_SUPPORT
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boolean "Qualcomm SDC5 8bit support"
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depends on MMC_MSM_SDC5_SUPPORT
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default n
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help
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Select Y to enable 8bit support for Slot 5.
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config MMC_MSM_SPS_SUPPORT
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bool "Use SPS BAM as data mover"
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depends on MMC_MSM && SPS
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default n
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help
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Select Y to use SPS BAM as data mover
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config MMC_TMIO
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tristate "Toshiba Mobile IO Controller (TMIO) MMC/SD function support"
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depends on MFD_TMIO || MFD_ASIC3
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@ -21,7 +21,6 @@ obj-$(CONFIG_MMC_OMAP) += omap.o
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obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o
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obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
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obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
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obj-$(CONFIG_MMC_MSM) += msm_sdcc.o
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obj-$(CONFIG_MMC_MVSDIO) += mvsdio.o
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obj-$(CONFIG_MMC_DAVINCI) += davinci_mmc.o
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obj-$(CONFIG_MMC_GOLDFISH) += android-goldfish.o
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@ -37,8 +36,6 @@ tmio_mmc_core-y := tmio_mmc_pio.o
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tmio_mmc_core-$(subst m,y,$(CONFIG_MMC_SDHI)) += tmio_mmc_dma.o
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obj-$(CONFIG_MMC_SDHI) += sh_mobile_sdhi.o
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obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
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obj-$(CONFIG_MMC_MSM) += msm_sdcc.o
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obj-$(CONFIG_MMC_MSM_SPS_SUPPORT) += msm_sdcc_dml.o
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obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
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obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o
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obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o
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File diff suppressed because it is too large
Load Diff
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@ -1,543 +0,0 @@
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/*
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* linux/drivers/mmc/host/msmsdcc.h - QCT MSM7K SDC Controller
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*
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* Copyright (C) 2008 Google, All Rights Reserved.
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* Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* - Based on mmci.h
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*/
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#ifndef _MSM_SDCC_H
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#define _MSM_SDCC_H
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/sdio.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/wakelock.h>
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#include <linux/pm_qos.h>
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#include <linux/msm-sps.h>
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#include <asm/sizes.h>
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#include <asm/mach/mmc.h>
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#include <mach/dma.h>
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#define MMCIPOWER 0x000
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#define MCI_PWR_OFF 0x00
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#define MCI_PWR_UP 0x02
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#define MCI_PWR_ON 0x03
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#define MCI_OD (1 << 6)
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#define MCI_SW_RST (1 << 7)
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#define MCI_SW_RST_CFG (1 << 8)
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#define MMCICLOCK 0x004
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#define MCI_CLK_ENABLE (1 << 8)
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#define MCI_CLK_PWRSAVE (1 << 9)
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#define MCI_CLK_WIDEBUS_1 (0 << 10)
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#define MCI_CLK_WIDEBUS_4 (2 << 10)
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#define MCI_CLK_WIDEBUS_8 (3 << 10)
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#define MCI_CLK_FLOWENA (1 << 12)
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#define MCI_CLK_INVERTOUT (1 << 13)
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#define MCI_CLK_SELECTIN (1 << 15)
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#define IO_PAD_PWR_SWITCH (1 << 21)
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#define MMCIARGUMENT 0x008
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#define MMCICOMMAND 0x00c
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#define MCI_CPSM_RESPONSE (1 << 6)
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#define MCI_CPSM_LONGRSP (1 << 7)
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#define MCI_CPSM_INTERRUPT (1 << 8)
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#define MCI_CPSM_PENDING (1 << 9)
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#define MCI_CPSM_ENABLE (1 << 10)
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#define MCI_CPSM_PROGENA (1 << 11)
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#define MCI_CSPM_DATCMD (1 << 12)
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#define MCI_CSPM_MCIABORT (1 << 13)
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#define MCI_CSPM_CCSENABLE (1 << 14)
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#define MCI_CSPM_CCSDISABLE (1 << 15)
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#define MCI_CSPM_AUTO_CMD19 (1 << 16)
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#define MCI_CSPM_AUTO_CMD21 (1 << 21)
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#define MMCIRESPCMD 0x010
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#define MMCIRESPONSE0 0x014
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#define MMCIRESPONSE1 0x018
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#define MMCIRESPONSE2 0x01c
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#define MMCIRESPONSE3 0x020
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#define MMCIDATATIMER 0x024
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#define MMCIDATALENGTH 0x028
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#define MMCIDATACTRL 0x02c
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#define MCI_DPSM_ENABLE (1 << 0)
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#define MCI_DPSM_DIRECTION (1 << 1)
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#define MCI_DPSM_MODE (1 << 2)
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#define MCI_DPSM_DMAENABLE (1 << 3)
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#define MCI_DATA_PEND (1 << 17)
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#define MCI_AUTO_PROG_DONE (1 << 19)
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#define MCI_RX_DATA_PEND (1 << 20)
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#define MMCIDATACNT 0x030
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#define MMCISTATUS 0x034
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#define MCI_CMDCRCFAIL (1 << 0)
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#define MCI_DATACRCFAIL (1 << 1)
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#define MCI_CMDTIMEOUT (1 << 2)
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#define MCI_DATATIMEOUT (1 << 3)
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#define MCI_TXUNDERRUN (1 << 4)
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#define MCI_RXOVERRUN (1 << 5)
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#define MCI_CMDRESPEND (1 << 6)
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#define MCI_CMDSENT (1 << 7)
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#define MCI_DATAEND (1 << 8)
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#define MCI_DATABLOCKEND (1 << 10)
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#define MCI_CMDACTIVE (1 << 11)
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#define MCI_TXACTIVE (1 << 12)
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#define MCI_RXACTIVE (1 << 13)
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#define MCI_TXFIFOHALFEMPTY (1 << 14)
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#define MCI_RXFIFOHALFFULL (1 << 15)
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#define MCI_TXFIFOFULL (1 << 16)
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#define MCI_RXFIFOFULL (1 << 17)
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#define MCI_TXFIFOEMPTY (1 << 18)
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#define MCI_RXFIFOEMPTY (1 << 19)
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#define MCI_TXDATAAVLBL (1 << 20)
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#define MCI_RXDATAAVLBL (1 << 21)
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#define MCI_SDIOINTR (1 << 22)
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#define MCI_PROGDONE (1 << 23)
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#define MCI_ATACMDCOMPL (1 << 24)
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#define MCI_SDIOINTROPE (1 << 25)
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#define MCI_CCSTIMEOUT (1 << 26)
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#define MCI_AUTOCMD19TIMEOUT (1 << 30)
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#define MMCICLEAR 0x038
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#define MCI_CMDCRCFAILCLR (1 << 0)
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#define MCI_DATACRCFAILCLR (1 << 1)
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#define MCI_CMDTIMEOUTCLR (1 << 2)
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#define MCI_DATATIMEOUTCLR (1 << 3)
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#define MCI_TXUNDERRUNCLR (1 << 4)
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#define MCI_RXOVERRUNCLR (1 << 5)
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#define MCI_CMDRESPENDCLR (1 << 6)
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#define MCI_CMDSENTCLR (1 << 7)
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#define MCI_DATAENDCLR (1 << 8)
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#define MCI_STARTBITERRCLR (1 << 9)
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#define MCI_DATABLOCKENDCLR (1 << 10)
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#define MCI_SDIOINTRCLR (1 << 22)
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#define MCI_PROGDONECLR (1 << 23)
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#define MCI_ATACMDCOMPLCLR (1 << 24)
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#define MCI_SDIOINTROPECLR (1 << 25)
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#define MCI_CCSTIMEOUTCLR (1 << 26)
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#define MCI_CLEAR_STATIC_MASK \
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(MCI_CMDCRCFAILCLR|MCI_DATACRCFAILCLR|MCI_CMDTIMEOUTCLR|\
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MCI_DATATIMEOUTCLR|MCI_TXUNDERRUNCLR|MCI_RXOVERRUNCLR| \
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MCI_CMDRESPENDCLR|MCI_CMDSENTCLR|MCI_DATAENDCLR| \
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MCI_STARTBITERRCLR|MCI_DATABLOCKENDCLR|MCI_SDIOINTRCLR| \
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MCI_SDIOINTROPECLR|MCI_PROGDONECLR|MCI_ATACMDCOMPLCLR| \
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MCI_CCSTIMEOUTCLR)
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#define MMCIMASK0 0x03c
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#define MCI_CMDCRCFAILMASK (1 << 0)
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#define MCI_DATACRCFAILMASK (1 << 1)
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#define MCI_CMDTIMEOUTMASK (1 << 2)
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#define MCI_DATATIMEOUTMASK (1 << 3)
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#define MCI_TXUNDERRUNMASK (1 << 4)
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#define MCI_RXOVERRUNMASK (1 << 5)
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#define MCI_CMDRESPENDMASK (1 << 6)
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#define MCI_CMDSENTMASK (1 << 7)
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#define MCI_DATAENDMASK (1 << 8)
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#define MCI_DATABLOCKENDMASK (1 << 10)
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#define MCI_CMDACTIVEMASK (1 << 11)
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#define MCI_TXACTIVEMASK (1 << 12)
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#define MCI_RXACTIVEMASK (1 << 13)
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#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
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#define MCI_RXFIFOHALFFULLMASK (1 << 15)
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#define MCI_TXFIFOFULLMASK (1 << 16)
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#define MCI_RXFIFOFULLMASK (1 << 17)
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#define MCI_TXFIFOEMPTYMASK (1 << 18)
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#define MCI_RXFIFOEMPTYMASK (1 << 19)
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#define MCI_TXDATAAVLBLMASK (1 << 20)
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#define MCI_RXDATAAVLBLMASK (1 << 21)
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#define MCI_SDIOINTMASK (1 << 22)
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#define MCI_PROGDONEMASK (1 << 23)
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#define MCI_ATACMDCOMPLMASK (1 << 24)
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#define MCI_SDIOINTOPERMASK (1 << 25)
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#define MCI_CCSTIMEOUTMASK (1 << 26)
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#define MCI_AUTOCMD19TIMEOUTMASK (1 << 30)
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#define MMCIMASK1 0x040
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#define MMCIFIFOCNT 0x044
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#define MCI_VERSION 0x050
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#define MCICCSTIMER 0x058
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#define MCI_DLL_CONFIG 0x060
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#define MCI_DLL_EN (1 << 16)
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#define MCI_CDR_EN (1 << 17)
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#define MCI_CK_OUT_EN (1 << 18)
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#define MCI_CDR_EXT_EN (1 << 19)
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#define MCI_DLL_PDN (1 << 29)
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#define MCI_DLL_RST (1 << 30)
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#define MCI_DLL_STATUS 0x068
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#define MCI_DLL_LOCK (1 << 7)
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#define MCI_STATUS2 0x06C
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#define MCI_MCLK_REG_WR_ACTIVE (1 << 0)
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#define MMCIFIFO 0x080 /* to 0x0bc */
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#define MCI_TEST_INPUT 0x0D4
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#define MCI_TESTBUS_CONFIG 0x0CC
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#define MCI_TESTBUS_SEL_MASK (0x7)
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#define MAX_TESTBUS 8
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#define MCI_TESTBUS_ENA (1 << 3)
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#define MCI_CORE_HC_MODE 0x78
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#define MCI_SDCC_DEBUG_REG 0x124
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#define MCI_IRQENABLE \
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(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
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MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
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MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATAENDMASK| \
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MCI_PROGDONEMASK|MCI_AUTOCMD19TIMEOUTMASK)
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#define MCI_IRQ_PIO \
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(MCI_RXDATAAVLBLMASK | MCI_TXDATAAVLBLMASK | \
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MCI_RXFIFOEMPTYMASK | MCI_TXFIFOEMPTYMASK | MCI_RXFIFOFULLMASK |\
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MCI_TXFIFOFULLMASK | MCI_RXFIFOHALFFULLMASK | \
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MCI_TXFIFOHALFEMPTYMASK | MCI_RXACTIVEMASK | MCI_TXACTIVEMASK)
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/*
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* The size of the FIFO in bytes.
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*/
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#define MCI_FIFOSIZE (16*4)
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#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
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|
||||
#define NR_SG 128
|
||||
|
||||
#define MSM_MMC_DEFAULT_IDLE_TIMEOUT 5000 /* msecs */
|
||||
#define MSM_MMC_CLK_GATE_DELAY 200 /* msecs */
|
||||
|
||||
/* Set the request timeout to 10secs */
|
||||
#define MSM_MMC_REQ_TIMEOUT 10000 /* msecs */
|
||||
|
||||
/*
|
||||
* Controller HW limitations
|
||||
*/
|
||||
#define MCI_DATALENGTH_BITS 25
|
||||
#define MMC_MAX_REQ_SIZE ((1 << MCI_DATALENGTH_BITS) - 1)
|
||||
/* MCI_DATA_CTL BLOCKSIZE up to 4096 */
|
||||
#define MMC_MAX_BLK_SIZE 4096
|
||||
#define MMC_MIN_BLK_SIZE 512
|
||||
#define MMC_MAX_BLK_CNT (MMC_MAX_REQ_SIZE / MMC_MIN_BLK_SIZE)
|
||||
|
||||
/* 64KiB */
|
||||
#define MAX_SG_SIZE (64 * 1024)
|
||||
#define MAX_NR_SG_DMA_PIO (MMC_MAX_REQ_SIZE / MAX_SG_SIZE)
|
||||
|
||||
/*
|
||||
* BAM limitations
|
||||
*/
|
||||
/* upto 16 bits (64K - 1) */
|
||||
#define SPS_MAX_DESC_FIFO_SIZE 65535
|
||||
/* 16KiB */
|
||||
#define SPS_MAX_DESC_SIZE (16 * 1024)
|
||||
/* Each descriptor is of length 8 bytes */
|
||||
#define SPS_MAX_DESC_LENGTH 8
|
||||
#define SPS_MAX_DESCS (SPS_MAX_DESC_FIFO_SIZE / SPS_MAX_DESC_LENGTH)
|
||||
|
||||
/*
|
||||
* DMA limitations
|
||||
*/
|
||||
/* upto 16 bits (64K - 1) */
|
||||
#define MMC_MAX_DMA_ROWS (64 * 1024 - 1)
|
||||
#define MMC_MAX_DMA_BOX_LENGTH (MMC_MAX_DMA_ROWS * MCI_FIFOSIZE)
|
||||
#define MMC_MAX_DMA_CMDS (MAX_NR_SG_DMA_PIO * (MMC_MAX_REQ_SIZE / \
|
||||
MMC_MAX_DMA_BOX_LENGTH))
|
||||
|
||||
/*
|
||||
* Peripheral bus clock scaling vote rates
|
||||
*/
|
||||
#define MSMSDCC_BUS_VOTE_MAX_RATE 64000000 /* Hz */
|
||||
#define MSMSDCC_BUS_VOTE_MIN_RATE 32000000 /* Hz */
|
||||
|
||||
struct clk;
|
||||
|
||||
struct msmsdcc_nc_dmadata {
|
||||
dmov_box cmd[MMC_MAX_DMA_CMDS];
|
||||
uint32_t cmdptr;
|
||||
};
|
||||
|
||||
struct msmsdcc_dma_data {
|
||||
struct msmsdcc_nc_dmadata *nc;
|
||||
dma_addr_t nc_busaddr;
|
||||
dma_addr_t cmd_busaddr;
|
||||
dma_addr_t cmdptr_busaddr;
|
||||
|
||||
struct msm_dmov_cmd hdr;
|
||||
enum dma_data_direction dir;
|
||||
|
||||
struct scatterlist *sg;
|
||||
int num_ents;
|
||||
|
||||
int channel;
|
||||
int crci;
|
||||
struct msmsdcc_host *host;
|
||||
int busy; /* Set if DM is busy */
|
||||
unsigned int result;
|
||||
struct msm_dmov_errdata err;
|
||||
};
|
||||
|
||||
struct msmsdcc_pio_data {
|
||||
struct sg_mapping_iter sg_miter;
|
||||
char bounce_buf[4];
|
||||
/* valid bytes in bounce_buf */
|
||||
int bounce_buf_len;
|
||||
};
|
||||
|
||||
struct msmsdcc_curr_req {
|
||||
struct mmc_request *mrq;
|
||||
struct mmc_command *cmd;
|
||||
struct mmc_data *data;
|
||||
unsigned int xfer_size; /* Total data size */
|
||||
unsigned int xfer_remain; /* Bytes remaining to send */
|
||||
unsigned int data_xfered; /* Bytes acked by BLKEND irq */
|
||||
int got_dataend;
|
||||
bool wait_for_auto_prog_done;
|
||||
bool got_auto_prog_done;
|
||||
bool use_wr_data_pend;
|
||||
int user_pages;
|
||||
u32 req_tout_ms;
|
||||
};
|
||||
|
||||
struct msmsdcc_sps_ep_conn_data {
|
||||
struct sps_pipe *pipe_handle;
|
||||
struct sps_connect config;
|
||||
struct sps_register_event event;
|
||||
};
|
||||
|
||||
struct msmsdcc_sps_data {
|
||||
struct msmsdcc_sps_ep_conn_data prod;
|
||||
struct msmsdcc_sps_ep_conn_data cons;
|
||||
struct sps_event_notify notify;
|
||||
enum dma_data_direction dir;
|
||||
struct scatterlist *sg;
|
||||
int num_ents;
|
||||
unsigned long bam_handle;
|
||||
unsigned int src_pipe_index;
|
||||
unsigned int dest_pipe_index;
|
||||
unsigned int busy;
|
||||
unsigned int xfer_req_cnt;
|
||||
bool reset_bam;
|
||||
struct tasklet_struct tlet;
|
||||
};
|
||||
|
||||
struct msmsdcc_msm_bus_vote {
|
||||
uint32_t client_handle;
|
||||
uint32_t curr_vote;
|
||||
int min_bw_vote;
|
||||
int max_bw_vote;
|
||||
bool is_max_bw_needed;
|
||||
struct delayed_work vote_work;
|
||||
};
|
||||
|
||||
struct msmsdcc_host {
|
||||
struct resource *core_irqres;
|
||||
struct resource *bam_irqres;
|
||||
struct resource *core_memres;
|
||||
struct resource *bam_memres;
|
||||
struct resource *dml_memres;
|
||||
struct resource *dmares;
|
||||
struct resource *dma_crci_res;
|
||||
void __iomem *base;
|
||||
void __iomem *dml_base;
|
||||
void __iomem *bam_base;
|
||||
|
||||
struct platform_device *pdev;
|
||||
|
||||
struct msmsdcc_curr_req curr;
|
||||
|
||||
struct mmc_host *mmc;
|
||||
struct clk *clk; /* main MMC bus clock */
|
||||
struct clk *pclk; /* SDCC peripheral bus clock */
|
||||
struct clk *bus_clk; /* SDCC bus voter clock */
|
||||
unsigned long bus_clk_rate; /* peripheral bus clk rate */
|
||||
atomic_t clks_on; /* set if clocks are enabled */
|
||||
|
||||
unsigned int eject; /* eject state */
|
||||
|
||||
spinlock_t lock;
|
||||
|
||||
unsigned int clk_rate; /* Current clock rate */
|
||||
unsigned int pclk_rate;
|
||||
|
||||
u32 pwr;
|
||||
struct mmc_platform_data *plat;
|
||||
unsigned int hw_caps;
|
||||
|
||||
unsigned int oldstat;
|
||||
|
||||
struct msmsdcc_dma_data dma;
|
||||
struct msmsdcc_sps_data sps;
|
||||
struct msmsdcc_pio_data pio;
|
||||
|
||||
struct tasklet_struct dma_tlet;
|
||||
|
||||
unsigned int prog_enable;
|
||||
|
||||
/* Command parameters */
|
||||
unsigned int cmd_timeout;
|
||||
unsigned int cmd_pio_irqmask;
|
||||
unsigned int cmd_datactrl;
|
||||
struct mmc_command *cmd_cmd;
|
||||
u32 cmd_c;
|
||||
|
||||
unsigned int mci_irqenable;
|
||||
unsigned int dummy_52_needed;
|
||||
unsigned int dummy_52_sent;
|
||||
|
||||
struct wake_lock sdio_wlock;
|
||||
struct wake_lock sdio_suspend_wlock;
|
||||
struct timer_list req_tout_timer;
|
||||
unsigned long reg_write_delay;
|
||||
bool io_pad_pwr_switch;
|
||||
bool tuning_in_progress;
|
||||
bool tuning_needed;
|
||||
bool tuning_done;
|
||||
bool en_auto_cmd19;
|
||||
bool en_auto_cmd21;
|
||||
bool sdio_gpio_lpm;
|
||||
bool irq_wake_enabled;
|
||||
struct pm_qos_request pm_qos_req_dma;
|
||||
u32 cpu_dma_latency;
|
||||
bool sdcc_suspending;
|
||||
bool sdcc_irq_disabled;
|
||||
bool sdcc_suspended;
|
||||
bool sdio_wakeupirq_disabled;
|
||||
struct mutex clk_mutex;
|
||||
bool pending_resume;
|
||||
unsigned int idle_tout; /* Timeout in msecs */
|
||||
bool enforce_pio_mode;
|
||||
bool print_pm_stats;
|
||||
struct msmsdcc_msm_bus_vote msm_bus_vote;
|
||||
struct device_attribute max_bus_bw;
|
||||
struct device_attribute polling;
|
||||
struct device_attribute idle_timeout;
|
||||
struct device_attribute auto_cmd19_attr;
|
||||
struct device_attribute auto_cmd21_attr;
|
||||
struct dentry *debugfs_host_dir;
|
||||
struct dentry *debugfs_idle_tout;
|
||||
struct dentry *debugfs_pio_mode;
|
||||
struct dentry *debugfs_pm_stats;
|
||||
int saved_tuning_phase;
|
||||
};
|
||||
|
||||
#define MSMSDCC_VERSION_STEP_MASK 0x0000FFFF
|
||||
#define MSMSDCC_VERSION_MINOR_MASK 0x0FFF0000
|
||||
#define MSMSDCC_VERSION_MINOR_SHIFT 16
|
||||
#define MSMSDCC_VERSION_MAJOR_MASK 0xF0000000
|
||||
#define MSMSDCC_VERSION_MAJOR_SHIFT 28
|
||||
#define MSMSDCC_DMA_SUP (1 << 0)
|
||||
#define MSMSDCC_SPS_BAM_SUP (1 << 1)
|
||||
#define MSMSDCC_SOFT_RESET (1 << 2)
|
||||
#define MSMSDCC_AUTO_PROG_DONE (1 << 3)
|
||||
#define MSMSDCC_REG_WR_ACTIVE (1 << 4)
|
||||
#define MSMSDCC_SW_RST (1 << 5)
|
||||
#define MSMSDCC_SW_RST_CFG (1 << 6)
|
||||
#define MSMSDCC_WAIT_FOR_TX_RX (1 << 7)
|
||||
#define MSMSDCC_IO_PAD_PWR_SWITCH (1 << 8)
|
||||
#define MSMSDCC_AUTO_CMD19 (1 << 9)
|
||||
#define MSMSDCC_AUTO_CMD21 (1 << 10)
|
||||
#define MSMSDCC_SW_RST_CFG_BROKEN (1 << 11)
|
||||
#define MSMSDCC_DATA_PEND_FOR_CMD53 (1 << 12)
|
||||
#define MSMSDCC_TESTBUS_DEBUG (1 << 13)
|
||||
#define MSMSDCC_SDHCI_MODE_SUPPORTED (1 << 14)
|
||||
|
||||
#define set_hw_caps(h, val) ((h)->hw_caps |= val)
|
||||
#define is_sps_mode(h) ((h)->hw_caps & MSMSDCC_SPS_BAM_SUP)
|
||||
#define is_dma_mode(h) ((h)->hw_caps & MSMSDCC_DMA_SUP)
|
||||
#define is_soft_reset(h) ((h)->hw_caps & MSMSDCC_SOFT_RESET)
|
||||
#define is_auto_prog_done(h) ((h)->hw_caps & MSMSDCC_AUTO_PROG_DONE)
|
||||
#define is_wait_for_reg_write(h) ((h)->hw_caps & MSMSDCC_REG_WR_ACTIVE)
|
||||
#define is_sw_hard_reset(h) ((h)->hw_caps & MSMSDCC_SW_RST)
|
||||
#define is_sw_reset_save_config(h) ((h)->hw_caps & MSMSDCC_SW_RST_CFG)
|
||||
#define is_wait_for_tx_rx_active(h) ((h)->hw_caps & MSMSDCC_WAIT_FOR_TX_RX)
|
||||
#define is_io_pad_pwr_switch(h) ((h)->hw_caps & MSMSDCC_IO_PAD_PWR_SWITCH)
|
||||
#define is_auto_cmd19(h) ((h)->hw_caps & MSMSDCC_AUTO_CMD19)
|
||||
#define is_auto_cmd21(h) ((h)->hw_caps & MSMSDCC_AUTO_CMD21)
|
||||
#define is_sw_reset_save_config_broken(h) \
|
||||
((h)->hw_caps & MSMSDCC_SW_RST_CFG_BROKEN)
|
||||
#define is_data_pend_for_cmd53(h) ((h)->hw_caps & MSMSDCC_DATA_PEND_FOR_CMD53)
|
||||
#define is_testbus_debug(h) ((h)->hw_caps & MSMSDCC_TESTBUS_DEBUG)
|
||||
#define is_sdhci_supported(h) ((h)->hw_caps & MSMSDCC_SDHCI_MODE_SUPPORTED)
|
||||
|
||||
/* Set controller capabilities based on version */
|
||||
static inline void set_default_hw_caps(struct msmsdcc_host *host)
|
||||
{
|
||||
u32 version;
|
||||
u16 step, minor;
|
||||
|
||||
/*
|
||||
* Lookup the Controller Version, to identify the supported features
|
||||
* Version number read as 0 would indicate SDCC3 or earlier versions.
|
||||
*/
|
||||
version = readl_relaxed(host->base + MCI_VERSION);
|
||||
pr_info("%s: SDCC Version: 0x%.8x\n", mmc_hostname(host->mmc), version);
|
||||
|
||||
if (!version)
|
||||
return;
|
||||
|
||||
step = version & MSMSDCC_VERSION_STEP_MASK;
|
||||
minor = (version & MSMSDCC_VERSION_MINOR_MASK) >>
|
||||
MSMSDCC_VERSION_MINOR_SHIFT;
|
||||
|
||||
if (version) /* SDCC v4 and greater */
|
||||
host->hw_caps |= MSMSDCC_AUTO_PROG_DONE |
|
||||
MSMSDCC_SOFT_RESET | MSMSDCC_REG_WR_ACTIVE
|
||||
| MSMSDCC_WAIT_FOR_TX_RX | MSMSDCC_IO_PAD_PWR_SWITCH
|
||||
| MSMSDCC_AUTO_CMD19;
|
||||
|
||||
if ((step == 0x18) && (minor >= 3)) {
|
||||
host->hw_caps |= MSMSDCC_AUTO_CMD21;
|
||||
/* Version 0x06000018 need hard reset on errors */
|
||||
host->hw_caps &= ~MSMSDCC_SOFT_RESET;
|
||||
}
|
||||
|
||||
if (step >= 0x2b) /* SDCC v4 2.1.0 and greater */
|
||||
host->hw_caps |= MSMSDCC_SW_RST | MSMSDCC_SW_RST_CFG |
|
||||
MSMSDCC_AUTO_CMD21 |
|
||||
MSMSDCC_DATA_PEND_FOR_CMD53 |
|
||||
MSMSDCC_TESTBUS_DEBUG |
|
||||
MSMSDCC_SW_RST_CFG_BROKEN |
|
||||
MSMSDCC_SDHCI_MODE_SUPPORTED;
|
||||
}
|
||||
|
||||
int msmsdcc_set_pwrsave(struct mmc_host *mmc, int pwrsave);
|
||||
int msmsdcc_sdio_al_lpm(struct mmc_host *mmc, bool enable);
|
||||
|
||||
#ifdef CONFIG_MSM_SDIO_AL
|
||||
|
||||
static inline int msmsdcc_lpm_enable(struct mmc_host *mmc)
|
||||
{
|
||||
return msmsdcc_sdio_al_lpm(mmc, true);
|
||||
}
|
||||
|
||||
static inline int msmsdcc_lpm_disable(struct mmc_host *mmc)
|
||||
{
|
||||
struct msmsdcc_host *host = mmc_priv(mmc);
|
||||
int ret;
|
||||
|
||||
ret = msmsdcc_sdio_al_lpm(mmc, false);
|
||||
wake_unlock(&host->sdio_wlock);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,299 +0,0 @@
|
|||
/*
|
||||
* linux/drivers/mmc/host/msm_sdcc_dml.c - Qualcomm MSM SDCC DML Driver
|
||||
*
|
||||
* Copyright (c) 2011, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <mach/msm_iomap.h>
|
||||
|
||||
#include "msm_sdcc_dml.h"
|
||||
|
||||
/*
|
||||
* DML registers definations
|
||||
*/
|
||||
|
||||
/* DML config register defination */
|
||||
#define DML_CONFIG 0x0000
|
||||
#define PRODUCER_CRCI_DIS 0x00
|
||||
#define PRODUCER_CRCI_X_SEL 0x01
|
||||
#define PRODUCER_CRCI_Y_SEL 0x02
|
||||
#define PRODUCER_CRCI_MSK 0x3
|
||||
#define CONSUMER_CRCI_DIS (0x00 << 2)
|
||||
#define CONSUMER_CRCI_X_SEL (0x01 << 2)
|
||||
#define CONSUMER_CRCI_Y_SEL (0x02 << 2)
|
||||
#define CONSUMER_CRCI_MSK (0x3 << 2)
|
||||
#define PRODUCER_TRANS_END_EN (1 << 4)
|
||||
#define BYPASS (1 << 16)
|
||||
#define DIRECT_MODE (1 << 17)
|
||||
#define INFINITE_CONS_TRANS (1 << 18)
|
||||
|
||||
/* DML status register defination */
|
||||
#define DML_STATUS 0x0004
|
||||
#define PRODUCER_IDLE (1 << 0)
|
||||
#define CONSUMER_IDLE (1 << 16)
|
||||
|
||||
/*
|
||||
* DML SW RESET register defination
|
||||
* NOTE: write to this register resets the DML core.
|
||||
* All internal state information will be lost and all
|
||||
* register values will be reset as well
|
||||
*/
|
||||
#define DML_SW_RESET 0x0008
|
||||
|
||||
/*
|
||||
* DML PRODUCER START register defination
|
||||
* NOTE: A write to this register triggers the DML
|
||||
* Producer state machine. No SW register values will be
|
||||
* altered.
|
||||
*/
|
||||
#define DML_PRODUCER_START 0x000C
|
||||
|
||||
/*
|
||||
* DML CONSUMER START register defination
|
||||
* NOTE: A write to this register triggers the DML
|
||||
* Consumer state machine. No SW register values will be
|
||||
* altered.
|
||||
*/
|
||||
#define DML_CONSUMER_START 0x0010
|
||||
|
||||
/*
|
||||
* DML producer pipe logical size register defination
|
||||
* NOTE: This register holds the size of the producer pipe
|
||||
* (in units of bytes) _to_ which the peripheral can
|
||||
* keep writing data to when its the PRODUCER.
|
||||
*/
|
||||
#define DML_PRODUCER_PIPE_LOGICAL_SIZE 0x0014
|
||||
|
||||
/*
|
||||
* DML producer pipe logical size register defination
|
||||
* NOTE: This register holds the size of the consumer pipe
|
||||
* (in units of bytes) _from_ which the peripheral
|
||||
* can keep _reading_ data from when its the CONSUMER.
|
||||
*/
|
||||
#define DML_CONSUMER_PIPE_LOGICAL_SIZE 0x00018
|
||||
|
||||
/*
|
||||
* DML PIPE ID register
|
||||
* This register holds pipe IDs that services
|
||||
* the producer and consumer side of the peripheral
|
||||
*/
|
||||
#define DML_PIPE_ID 0x0001C
|
||||
#define PRODUCER_PIPE_ID_SHFT 0
|
||||
#define PRODUCER_PIPE_ID_MSK 0x1f
|
||||
#define CONSUMER_PIPE_ID_SHFT 16
|
||||
#define CONSUMER_PIPE_ID_MSK (0x1f << 16)
|
||||
|
||||
/*
|
||||
* DML Producer trackers register defination.
|
||||
* This register is for debug purposes only. They reflect
|
||||
* the value of the producer block and transaction counters
|
||||
* when read. The values may be dynamically changing when
|
||||
* a transaction is in progress.
|
||||
*/
|
||||
#define DML_PRODUCER_TRACKERS 0x00020
|
||||
#define PROD_BLOCK_CNT_SHFT 0
|
||||
#define PROD_BLOCK_CNT_MSK 0xffff
|
||||
#define PROD_TRANS_CNT_SHFT 16
|
||||
#define PROD_TRANS_CNT_MSK (0xffff << 16)
|
||||
|
||||
/*
|
||||
* DML Producer BAM block size register defination.
|
||||
* This regsiter holds the block size, in units of bytes,
|
||||
* associated with the Producer BAM. The DML asserts the
|
||||
* block_end side band signal to the BAM whenever the producer
|
||||
* side of the peripheral has generated the said amount of data.
|
||||
* This register value should be an integral multiple of the
|
||||
* Producer CRCI Block Size.
|
||||
*/
|
||||
#define DML_PRODUCER_BAM_BLOCK_SIZE 0x00024
|
||||
|
||||
/*
|
||||
* DML Producer BAM Transaction size defination.
|
||||
* This regsiter holds the transaction size, in units of bytes,
|
||||
* associated with the Producer BAM. The DML asserts the transaction_end
|
||||
* side band signal to the BAM whenever the producer side of the peripheral
|
||||
* has generated the said amount of data.
|
||||
*/
|
||||
#define DML_PRODUCER_BAM_TRANS_SIZE 0x00028
|
||||
|
||||
/*
|
||||
* DML Direct mode base address defination
|
||||
* This register is used whenever the DIRECT_MODE bit
|
||||
* in config register is set.
|
||||
*/
|
||||
#define DML_DIRECT_MODE_BASE_ADDR 0x002C
|
||||
#define PRODUCER_BASE_ADDR_BSHFT 0
|
||||
#define PRODUCER_BASE_ADDR_BMSK 0xffff
|
||||
#define CONSUMER_BASE_ADDR_BSHFT 16
|
||||
#define CONSUMER_BASE_ADDR_BMSK (0xffff << 16)
|
||||
|
||||
/*
|
||||
* DMA Debug and status register defination.
|
||||
* These are the read-only registers useful debugging.
|
||||
*/
|
||||
#define DML_DEBUG 0x0030
|
||||
#define DML_BAM_SIDE_STATUS_1 0x0034
|
||||
#define DML_BAM_SIDE_STATUS_2 0x0038
|
||||
|
||||
/* other definations */
|
||||
#define PRODUCER_PIPE_LOGICAL_SIZE 4096
|
||||
#define CONSUMER_PIPE_LOGICAL_SIZE 4096
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
|
||||
/**
|
||||
* Initialize DML HW connected with SDCC core
|
||||
*
|
||||
*/
|
||||
int msmsdcc_dml_init(struct msmsdcc_host *host)
|
||||
{
|
||||
int rc = 0;
|
||||
u32 config = 0;
|
||||
void __iomem *dml_base;
|
||||
|
||||
if (!host->dml_base) {
|
||||
host->dml_base = ioremap(host->dml_memres->start,
|
||||
resource_size(host->dml_memres));
|
||||
if (!host->dml_base) {
|
||||
pr_err("%s: DML ioremap() failed!!! %pr\n",
|
||||
mmc_hostname(host->mmc), host->dml_memres);
|
||||
rc = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
pr_info("%s: Qualcomm MSM SDCC-DML %pr\n",
|
||||
mmc_hostname(host->mmc), host->dml_memres);
|
||||
}
|
||||
|
||||
dml_base = host->dml_base;
|
||||
/* Reset the DML block */
|
||||
writel_relaxed(1, (dml_base + DML_SW_RESET));
|
||||
|
||||
/* Disable the producer and consumer CRCI */
|
||||
config = (PRODUCER_CRCI_DIS | CONSUMER_CRCI_DIS);
|
||||
/*
|
||||
* Disable the bypass mode. Bypass mode will only be used
|
||||
* if data transfer is to happen in PIO mode and don't
|
||||
* want the BAM interface to connect with SDCC-DML.
|
||||
*/
|
||||
config &= ~BYPASS;
|
||||
/*
|
||||
* Disable direct mode as we don't DML to MASTER the AHB bus.
|
||||
* BAM connected with DML should MASTER the AHB bus.
|
||||
*/
|
||||
config &= ~DIRECT_MODE;
|
||||
/*
|
||||
* Disable infinite mode transfer as we won't be doing any
|
||||
* infinite size data transfers. All data transfer will be
|
||||
* of finite data size.
|
||||
*/
|
||||
config &= ~INFINITE_CONS_TRANS;
|
||||
writel_relaxed(config, (dml_base + DML_CONFIG));
|
||||
|
||||
/*
|
||||
* Initialize the logical BAM pipe size for producer
|
||||
* and consumer.
|
||||
*/
|
||||
writel_relaxed(PRODUCER_PIPE_LOGICAL_SIZE,
|
||||
(dml_base + DML_PRODUCER_PIPE_LOGICAL_SIZE));
|
||||
writel_relaxed(CONSUMER_PIPE_LOGICAL_SIZE,
|
||||
(dml_base + DML_CONSUMER_PIPE_LOGICAL_SIZE));
|
||||
|
||||
/* Initialize Producer/consumer pipe id */
|
||||
writel_relaxed(host->sps.src_pipe_index |
|
||||
(host->sps.dest_pipe_index << CONSUMER_PIPE_ID_SHFT),
|
||||
(dml_base + DML_PIPE_ID));
|
||||
mb();
|
||||
out:
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* Soft reset DML HW
|
||||
*
|
||||
*/
|
||||
void msmsdcc_dml_reset(struct msmsdcc_host *host)
|
||||
{
|
||||
/* Reset the DML block */
|
||||
writel_relaxed(1, (host->dml_base + DML_SW_RESET));
|
||||
mb();
|
||||
}
|
||||
|
||||
/**
|
||||
* Checks if DML HW is busy or not?
|
||||
*
|
||||
*/
|
||||
bool msmsdcc_is_dml_busy(struct msmsdcc_host *host)
|
||||
{
|
||||
return !(readl_relaxed(host->dml_base + DML_STATUS) & PRODUCER_IDLE) ||
|
||||
!(readl_relaxed(host->dml_base + DML_STATUS) & CONSUMER_IDLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* Start data transfer.
|
||||
*
|
||||
*/
|
||||
void msmsdcc_dml_start_xfer(struct msmsdcc_host *host, struct mmc_data *data)
|
||||
{
|
||||
u32 config;
|
||||
void __iomem *dml_base = host->dml_base;
|
||||
|
||||
if (data->flags & MMC_DATA_READ) {
|
||||
/* Read operation: configure DML for producer operation */
|
||||
/* Set producer CRCI-x and disable consumer CRCI */
|
||||
config = readl_relaxed(dml_base + DML_CONFIG);
|
||||
config = (config & ~PRODUCER_CRCI_MSK) | PRODUCER_CRCI_X_SEL;
|
||||
config = (config & ~CONSUMER_CRCI_MSK) | CONSUMER_CRCI_DIS;
|
||||
writel_relaxed(config, (dml_base + DML_CONFIG));
|
||||
|
||||
/* Set the Producer BAM block size */
|
||||
writel_relaxed(data->blksz, (dml_base +
|
||||
DML_PRODUCER_BAM_BLOCK_SIZE));
|
||||
|
||||
/* Set Producer BAM Transaction size */
|
||||
writel_relaxed(host->curr.xfer_size,
|
||||
(dml_base + DML_PRODUCER_BAM_TRANS_SIZE));
|
||||
/* Set Producer Transaction End bit */
|
||||
writel_relaxed((readl_relaxed(dml_base + DML_CONFIG)
|
||||
| PRODUCER_TRANS_END_EN),
|
||||
(dml_base + DML_CONFIG));
|
||||
/* Trigger producer */
|
||||
writel_relaxed(1, (dml_base + DML_PRODUCER_START));
|
||||
} else {
|
||||
/* Write operation: configure DML for consumer operation */
|
||||
/* Set consumer CRCI-x and disable producer CRCI*/
|
||||
config = readl_relaxed(dml_base + DML_CONFIG);
|
||||
config = (config & ~CONSUMER_CRCI_MSK) | CONSUMER_CRCI_X_SEL;
|
||||
config = (config & ~PRODUCER_CRCI_MSK) | PRODUCER_CRCI_DIS;
|
||||
writel_relaxed(config, (dml_base + DML_CONFIG));
|
||||
/* Clear Producer Transaction End bit */
|
||||
writel_relaxed((readl_relaxed(dml_base + DML_CONFIG)
|
||||
& ~PRODUCER_TRANS_END_EN),
|
||||
(dml_base + DML_CONFIG));
|
||||
/* Trigger consumer */
|
||||
writel_relaxed(1, (dml_base + DML_CONSUMER_START));
|
||||
}
|
||||
mb();
|
||||
}
|
||||
|
||||
/**
|
||||
* Deinitialize DML HW connected with SDCC core
|
||||
*
|
||||
*/
|
||||
void msmsdcc_dml_exit(struct msmsdcc_host *host)
|
||||
{
|
||||
/* Put DML block in reset state before exiting */
|
||||
msmsdcc_dml_reset(host);
|
||||
iounmap(host->dml_base);
|
||||
}
|
||||
#endif /* CONFIG_MMC_MSM_SPS_SUPPORT */
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
/*
|
||||
* linux/drivers/mmc/host/msm_sdcc_dml.h - Qualcomm SDCC DML driver
|
||||
* header file
|
||||
*
|
||||
* Copyright (c) 2011, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _MSM_SDCC_DML_H
|
||||
#define _MSM_SDCC_DML_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/mmc/host.h>
|
||||
|
||||
#include "msm_sdcc.h"
|
||||
|
||||
#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
|
||||
/**
|
||||
* Initialize DML HW connected with SDCC core
|
||||
*
|
||||
* This function initialize DML HW.
|
||||
*
|
||||
* This function should only be called once
|
||||
* typically during driver probe.
|
||||
*
|
||||
* @host - Pointer to sdcc host structure
|
||||
*
|
||||
* @return - 0 if successful else negative value.
|
||||
*
|
||||
*/
|
||||
int msmsdcc_dml_init(struct msmsdcc_host *host);
|
||||
|
||||
/**
|
||||
* Start data transfer.
|
||||
*
|
||||
* This function configure DML HW registers with
|
||||
* data transfer direction and data transfer size.
|
||||
*
|
||||
* This function should be called after submitting
|
||||
* data transfer request to SPS HW and before kick
|
||||
* starting data transfer in SDCC core.
|
||||
*
|
||||
* @host - Pointer to sdcc host structure
|
||||
* @data - Pointer to mmc_data structure
|
||||
*
|
||||
*/
|
||||
void msmsdcc_dml_start_xfer(struct msmsdcc_host *host, struct mmc_data *data);
|
||||
|
||||
/**
|
||||
* Checks if DML HW is busy or not?
|
||||
*
|
||||
* @host - Pointer to sdcc host structure
|
||||
*
|
||||
* @return - 1 if DML HW is busy with data transfer
|
||||
* 0 if DML HW is IDLE.
|
||||
*
|
||||
*/
|
||||
bool msmsdcc_is_dml_busy(struct msmsdcc_host *host);
|
||||
|
||||
/**
|
||||
* Soft reset DML HW
|
||||
*
|
||||
* This function give soft reset to DML HW.
|
||||
*
|
||||
* This function should be called to reset DML HW
|
||||
* if data transfer error is detected.
|
||||
*
|
||||
* @host - Pointer to sdcc host structure
|
||||
*
|
||||
*/
|
||||
void msmsdcc_dml_reset(struct msmsdcc_host *host);
|
||||
|
||||
/**
|
||||
* Deinitialize DML HW connected with SDCC core
|
||||
*
|
||||
* This function resets DML HW and unmap DML
|
||||
* register region.
|
||||
*
|
||||
* This function should only be called once
|
||||
* typically during driver remove.
|
||||
*
|
||||
* @host - Pointer to sdcc host structure
|
||||
*
|
||||
*/
|
||||
void msmsdcc_dml_exit(struct msmsdcc_host *host);
|
||||
#else
|
||||
static inline int msmsdcc_dml_init(struct msmsdcc_host *host) { return 0; }
|
||||
static inline int msmsdcc_dml_start_xfer(struct msmsdcc_host *host,
|
||||
struct mmc_data *data) { return 0; }
|
||||
static inline bool msmsdcc_is_dml_busy(
|
||||
struct msmsdcc_host *host) { return 0; }
|
||||
static inline void msmsdcc_dml_reset(struct msmsdcc_host *host) { }
|
||||
static inline void msmsdcc_dml_exit(struct msmsdcc_host *host) { }
|
||||
#endif /* CONFIG_MMC_MSM_SPS_SUPPORT */
|
||||
|
||||
#endif /* _MSM_SDCC_DML_H */
|
||||
Loading…
Reference in New Issue