arm64: strcmp: align to 64B cache line

Align strcmp to 64B. This will ensure the preformance critical loop is within one 64B cache line. Change-Id: I9240fbb4407637b2290a44e02ad59098a377b356 Signed-off-by: Yuanyuan Zhong <zyy@motorola.com> Reviewed-on: https://gerrit.mot.com/902536 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver <sltawvr@motorola.com> Tested-by: Jira Key <jirakey@motorola.com> Reviewed-by: Yi-Wei Zhao <gbjc64@motorola.com> Reviewed-by: Igor Kovalenko <igork@motorola.com> Submit-Approved: Jira Key <jirakey@motorola.com>
2016-09-23 11:21:03 -05:00 · 2016-09-23 11:21:03 -05:00 · b4c98bc799
parent 5cb8aed1c3
commit b4c98bc799
1 changed files with 1 additions and 0 deletions
--- a/arch/arm64/lib/strcmp.S
+++ b/arch/arm64/lib/strcmp.S
@ -60,6 +60,7 @@ tmp3		.req	x9
 zeroones	.req	x10
 pos		.req	x11

+	.p2align 6
 ENTRY(strcmp)
 	eor	tmp1, src1, src2
 	mov	zeroones, #REP8_01