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ARM: clk-imx6q: fix video divider for rev T0 1.0
commit 81ef447950bf0955aca46f4a7617d8ce435cf0ce upstream. The post dividers do not work on i.MX6Q rev T0 1.0 so they must be fixed to 1. As the table index was wrong, a divider a of 4 could still be requested which implied the clock not to be set properly. This is the root cause of the HDMI not working at high resolution on rev T0 1.0 of the SoC. Signed-off-by: Gary Bisson <bisson.gary@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -301,7 +301,7 @@ int __init mx6q_clocks_init(void)
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post_div_table[1].div = 1;
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post_div_table[2].div = 1;
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video_div_table[1].div = 1;
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video_div_table[2].div = 1;
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video_div_table[3].div = 1;
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}
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/* type name parent_name base div_mask */
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