mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-11-07 04:09:21 +00:00
powerpc/powernv: Remove unused functions
We don't need them anymore. The patch removes those functions. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Reviewed-by: Ram Pai <linuxram@us.ibm.com> Reviewed-by: Richard Yang <weiyang@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Gavin Shan
Benjamin Herrenschmidt
parent
c40a4210a4
commit
b9ae38aeca
1 changed files with 0 additions and 441 deletions
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@ -34,14 +34,6 @@
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#include "powernv.h"
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#include "pci.h"
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struct resource_wrap {
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struct list_head link;
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resource_size_t size;
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resource_size_t align;
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struct pci_dev *dev; /* Set if it's a device */
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struct pci_bus *bus; /* Set if it's a bridge */
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};
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static int __pe_printk(const char *level, const struct pnv_ioda_pe *pe,
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struct va_format *vaf)
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{
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@ -77,273 +69,6 @@ define_pe_printk_level(pe_err, KERN_ERR);
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define_pe_printk_level(pe_warn, KERN_WARNING);
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define_pe_printk_level(pe_info, KERN_INFO);
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/* Calculate resource usage & alignment requirement of a single
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* device. This will also assign all resources within the device
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* for a given type starting at 0 for the biggest one and then
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* assigning in decreasing order of size.
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*/
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static void __devinit pnv_ioda_calc_dev(struct pci_dev *dev, unsigned int flags,
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resource_size_t *size,
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resource_size_t *align)
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{
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resource_size_t start;
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struct resource *r;
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int i;
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pr_devel(" -> CDR %s\n", pci_name(dev));
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*size = *align = 0;
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/* Clear the resources out and mark them all unset */
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for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
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r = &dev->resource[i];
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if (!(r->flags & flags))
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continue;
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if (r->start) {
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r->end -= r->start;
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r->start = 0;
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}
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r->flags |= IORESOURCE_UNSET;
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}
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/* We currently keep all memory resources together, we
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* will handle prefetch & 64-bit separately in the future
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* but for now we stick everybody in M32
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*/
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start = 0;
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for (;;) {
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resource_size_t max_size = 0;
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int max_no = -1;
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/* Find next biggest resource */
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for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
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r = &dev->resource[i];
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if (!(r->flags & IORESOURCE_UNSET) ||
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!(r->flags & flags))
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continue;
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if (resource_size(r) > max_size) {
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max_size = resource_size(r);
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max_no = i;
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}
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}
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if (max_no < 0)
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break;
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r = &dev->resource[max_no];
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if (max_size > *align)
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*align = max_size;
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*size += max_size;
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r->start = start;
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start += max_size;
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r->end = r->start + max_size - 1;
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r->flags &= ~IORESOURCE_UNSET;
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pr_devel(" -> R%d %016llx..%016llx\n",
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max_no, r->start, r->end);
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}
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pr_devel(" <- CDR %s size=%llx align=%llx\n",
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pci_name(dev), *size, *align);
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}
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/* Allocate a resource "wrap" for a given device or bridge and
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* insert it at the right position in the sorted list
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*/
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static void __devinit pnv_ioda_add_wrap(struct list_head *list,
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struct pci_bus *bus,
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struct pci_dev *dev,
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resource_size_t size,
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resource_size_t align)
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{
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struct resource_wrap *w1, *w = kzalloc(sizeof(*w), GFP_KERNEL);
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w->size = size;
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w->align = align;
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w->dev = dev;
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w->bus = bus;
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list_for_each_entry(w1, list, link) {
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if (w1->align < align) {
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list_add_tail(&w->link, &w1->link);
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return;
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}
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}
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list_add_tail(&w->link, list);
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}
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/* Offset device resources of a given type */
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static void __devinit pnv_ioda_offset_dev(struct pci_dev *dev,
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unsigned int flags,
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resource_size_t offset)
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{
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struct resource *r;
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int i;
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pr_devel(" -> ODR %s [%x] +%016llx\n", pci_name(dev), flags, offset);
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for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
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r = &dev->resource[i];
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if (r->flags & flags) {
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dev->resource[i].start += offset;
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dev->resource[i].end += offset;
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}
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}
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pr_devel(" <- ODR %s [%x] +%016llx\n", pci_name(dev), flags, offset);
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}
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/* Offset bus resources (& all children) of a given type */
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static void __devinit pnv_ioda_offset_bus(struct pci_bus *bus,
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unsigned int flags,
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resource_size_t offset)
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{
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struct resource *r;
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struct pci_dev *dev;
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struct pci_bus *cbus;
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int i;
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pr_devel(" -> OBR %s [%x] +%016llx\n",
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bus->self ? pci_name(bus->self) : "root", flags, offset);
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pci_bus_for_each_resource(bus, r, i) {
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if (r && (r->flags & flags)) {
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r->start += offset;
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r->end += offset;
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}
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}
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list_for_each_entry(dev, &bus->devices, bus_list)
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pnv_ioda_offset_dev(dev, flags, offset);
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list_for_each_entry(cbus, &bus->children, node)
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pnv_ioda_offset_bus(cbus, flags, offset);
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pr_devel(" <- OBR %s [%x]\n",
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bus->self ? pci_name(bus->self) : "root", flags);
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}
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/* This is the guts of our IODA resource allocation. This is called
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* recursively for each bus in the system. It calculates all the
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* necessary size and requirements for children and assign them
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* resources such that:
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*
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* - Each function fits in it's own contiguous set of IO/M32
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* segment
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*
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* - All segments behind a P2P bridge are contiguous and obey
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* alignment constraints of those bridges
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*/
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static void __devinit pnv_ioda_calc_bus(struct pci_bus *bus, unsigned int flags,
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resource_size_t *size,
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resource_size_t *align)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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struct pnv_phb *phb = hose->private_data;
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resource_size_t dev_size, dev_align, start;
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resource_size_t min_align, min_balign;
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struct pci_dev *cdev;
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struct pci_bus *cbus;
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struct list_head head;
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struct resource_wrap *w;
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unsigned int bres;
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*size = *align = 0;
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pr_devel("-> CBR %s [%x]\n",
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bus->self ? pci_name(bus->self) : "root", flags);
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/* Calculate alignment requirements based on the type
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* of resource we are working on
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*/
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if (flags & IORESOURCE_IO) {
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bres = 0;
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min_align = phb->ioda.io_segsize;
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min_balign = 0x1000;
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} else {
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bres = 1;
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min_align = phb->ioda.m32_segsize;
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min_balign = 0x100000;
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}
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/* Gather all our children resources ordered by alignment */
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INIT_LIST_HEAD(&head);
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/* - Busses */
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list_for_each_entry(cbus, &bus->children, node) {
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pnv_ioda_calc_bus(cbus, flags, &dev_size, &dev_align);
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pnv_ioda_add_wrap(&head, cbus, NULL, dev_size, dev_align);
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}
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/* - Devices */
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list_for_each_entry(cdev, &bus->devices, bus_list) {
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pnv_ioda_calc_dev(cdev, flags, &dev_size, &dev_align);
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/* Align them to segment size */
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if (dev_align < min_align)
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dev_align = min_align;
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pnv_ioda_add_wrap(&head, NULL, cdev, dev_size, dev_align);
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}
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if (list_empty(&head))
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goto empty;
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/* Now we can do two things: assign offsets to them within that
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* level and get our total alignment & size requirements. The
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* assignment algorithm is going to be uber-trivial for now, we
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* can try to be smarter later at filling out holes.
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*/
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if (bus->self) {
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/* No offset for downstream bridges */
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start = 0;
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} else {
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/* Offset from the root */
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if (flags & IORESOURCE_IO)
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/* Don't hand out IO 0 */
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start = hose->io_resource.start + 0x1000;
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else
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start = hose->mem_resources[0].start;
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}
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while(!list_empty(&head)) {
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w = list_first_entry(&head, struct resource_wrap, link);
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list_del(&w->link);
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if (w->size) {
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if (start) {
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start = ALIGN(start, w->align);
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if (w->dev)
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pnv_ioda_offset_dev(w->dev,flags,start);
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else if (w->bus)
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pnv_ioda_offset_bus(w->bus,flags,start);
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}
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if (w->align > *align)
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*align = w->align;
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}
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start += w->size;
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kfree(w);
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}
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*size = start;
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/* Align and setup bridge resources */
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*align = max_t(resource_size_t, *align,
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max_t(resource_size_t, min_align, min_balign));
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*size = ALIGN(*size,
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max_t(resource_size_t, min_align, min_balign));
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empty:
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/* Only setup P2P's, not the PHB itself */
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if (bus->self) {
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struct resource *res = bus->resource[bres];
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if (WARN_ON(res == NULL))
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return;
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/*
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* FIXME: We should probably export and call
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* pci_bridge_check_ranges() to properly re-initialize
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* the PCI portion of the flags here, and to detect
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* what the bridge actually supports.
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*/
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res->start = 0;
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res->flags = (*size) ? flags : 0;
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res->end = (*size) ? (*size - 1) : 0;
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}
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pr_devel("<- CBR %s [%x] *size=%016llx *align=%016llx\n",
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bus->self ? pci_name(bus->self) : "root", flags,*size,*align);
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}
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static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev)
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{
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struct device_node *np;
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@ -354,172 +79,6 @@ static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev)
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return PCI_DN(np);
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}
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static void __devinit pnv_ioda_setup_pe_segments(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
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unsigned int pe, i;
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resource_size_t pos;
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struct resource io_res;
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struct resource m32_res;
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struct pci_bus_region region;
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int rc;
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/* Anything not referenced in the device-tree gets PE#0 */
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pe = pdn ? pdn->pe_number : 0;
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/* Calculate the device min/max */
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io_res.start = m32_res.start = (resource_size_t)-1;
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io_res.end = m32_res.end = 0;
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io_res.flags = IORESOURCE_IO;
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m32_res.flags = IORESOURCE_MEM;
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for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
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struct resource *r = NULL;
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if (dev->resource[i].flags & IORESOURCE_IO)
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r = &io_res;
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if (dev->resource[i].flags & IORESOURCE_MEM)
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r = &m32_res;
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if (!r)
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continue;
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if (dev->resource[i].start < r->start)
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r->start = dev->resource[i].start;
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if (dev->resource[i].end > r->end)
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r->end = dev->resource[i].end;
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}
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/* Setup IO segments */
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if (io_res.start < io_res.end) {
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pcibios_resource_to_bus(dev, ®ion, &io_res);
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pos = region.start;
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i = pos / phb->ioda.io_segsize;
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while(i < phb->ioda.total_pe && pos <= region.end) {
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if (phb->ioda.io_segmap[i]) {
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pr_err("%s: Trying to use IO seg #%d which is"
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" already used by PE# %d\n",
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pci_name(dev), i,
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phb->ioda.io_segmap[i]);
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/* XXX DO SOMETHING TO DISABLE DEVICE ? */
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break;
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}
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phb->ioda.io_segmap[i] = pe;
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rc = opal_pci_map_pe_mmio_window(phb->opal_id, pe,
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OPAL_IO_WINDOW_TYPE,
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0, i);
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if (rc != OPAL_SUCCESS) {
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pr_err("%s: OPAL error %d setting up mapping"
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" for IO seg# %d\n",
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pci_name(dev), rc, i);
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/* XXX DO SOMETHING TO DISABLE DEVICE ? */
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break;
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}
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pos += phb->ioda.io_segsize;
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i++;
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};
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}
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/* Setup M32 segments */
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if (m32_res.start < m32_res.end) {
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pcibios_resource_to_bus(dev, ®ion, &m32_res);
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pos = region.start;
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i = pos / phb->ioda.m32_segsize;
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while(i < phb->ioda.total_pe && pos <= region.end) {
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if (phb->ioda.m32_segmap[i]) {
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pr_err("%s: Trying to use M32 seg #%d which is"
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" already used by PE# %d\n",
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pci_name(dev), i,
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phb->ioda.m32_segmap[i]);
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/* XXX DO SOMETHING TO DISABLE DEVICE ? */
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break;
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}
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phb->ioda.m32_segmap[i] = pe;
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rc = opal_pci_map_pe_mmio_window(phb->opal_id, pe,
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OPAL_M32_WINDOW_TYPE,
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0, i);
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if (rc != OPAL_SUCCESS) {
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pr_err("%s: OPAL error %d setting up mapping"
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" for M32 seg# %d\n",
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pci_name(dev), rc, i);
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/* XXX DO SOMETHING TO DISABLE DEVICE ? */
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break;
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}
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pos += phb->ioda.m32_segsize;
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i++;
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}
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}
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}
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/* Check if a resource still fits in the total IO or M32 range
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* for a given PHB
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*/
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static int __devinit pnv_ioda_resource_fit(struct pci_controller *hose,
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struct resource *r)
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{
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struct resource *bounds;
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if (r->flags & IORESOURCE_IO)
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bounds = &hose->io_resource;
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else if (r->flags & IORESOURCE_MEM)
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bounds = &hose->mem_resources[0];
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else
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return 1;
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if (r->start >= bounds->start && r->end <= bounds->end)
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return 1;
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r->flags = 0;
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return 0;
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}
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static void __devinit pnv_ioda_update_resources(struct pci_bus *bus)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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struct pci_bus *cbus;
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struct pci_dev *cdev;
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unsigned int i;
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/* We used to clear all device enables here. However it looks like
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* clearing MEM enable causes Obsidian (IPR SCS) to go bonkers,
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* and shoot fatal errors to the PHB which in turns fences itself
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* and we can't recover from that ... yet. So for now, let's leave
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* the enables as-is and hope for the best.
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*/
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/* Check if bus resources fit in our IO or M32 range */
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for (i = 0; bus->self && (i < 2); i++) {
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struct resource *r = bus->resource[i];
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if (r && !pnv_ioda_resource_fit(hose, r))
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pr_err("%s: Bus %d resource %d disabled, no room\n",
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pci_name(bus->self), bus->number, i);
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}
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/* Update self if it's not a PHB */
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if (bus->self)
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pci_setup_bridge(bus);
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/* Update child devices */
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list_for_each_entry(cdev, &bus->devices, bus_list) {
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/* Check if resource fits, if not, disabled it */
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for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
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struct resource *r = &cdev->resource[i];
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if (!pnv_ioda_resource_fit(hose, r))
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pr_err("%s: Resource %d disabled, no room\n",
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pci_name(cdev), i);
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}
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/* Assign segments */
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pnv_ioda_setup_pe_segments(cdev);
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/* Update HW BARs */
|
||||
for (i = 0; i <= PCI_ROM_RESOURCE; i++)
|
||||
pci_update_resource(cdev, i);
|
||||
}
|
||||
|
||||
/* Update child busses */
|
||||
list_for_each_entry(cbus, &bus->children, node)
|
||||
pnv_ioda_update_resources(cbus);
|
||||
}
|
||||
|
||||
static int __devinit pnv_ioda_alloc_pe(struct pnv_phb *phb)
|
||||
{
|
||||
unsigned long pe;
|
||||
|
|
|
|||
Loading…
Reference in a new issue