From bb4a3b53331dfa953ad0c0b7fe2e5f6cba7288d1 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 24 Jul 2015 15:01:55 +0530 Subject: [PATCH] ARM: dts: msm: Add qcom,clk-dis-wait-val value for MSM8976 Along with clk-dis-wait-val to 0x5, we need to sleep value of OXILI_GFX3D_CBCR to be 0x0. Change-Id: I8732a0d050d7f7ff2fba0d7faec12c38767861aa Signed-off-by: Taniya Das --- arch/arm/boot/dts/qcom/msm8976.dtsi | 1 + drivers/clk/qcom/clock-gcc-8976.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8976.dtsi b/arch/arm/boot/dts/qcom/msm8976.dtsi index e69da12a2d75..1c715c5c849d 100644 --- a/arch/arm/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm/boot/dts/qcom/msm8976.dtsi @@ -2666,6 +2666,7 @@ clocks =<&clock_gcc_gfx clk_gfx3d_clk_src>, <&clock_gcc_gfx clk_gcc_oxili_gmem_clk>; qcom,enable-root-clk; + qcom,clk-dis-wait-val = <0x5>; parent-supply = <&gfx_vreg_corner>; status = "okay"; }; diff --git a/drivers/clk/qcom/clock-gcc-8976.c b/drivers/clk/qcom/clock-gcc-8976.c index 2c479bb69f2e..08054dfc810d 100644 --- a/drivers/clk/qcom/clock-gcc-8976.c +++ b/drivers/clk/qcom/clock-gcc-8976.c @@ -3967,6 +3967,12 @@ static int msm_gcc_gfx_probe(struct platform_device *pdev) regval &= ~BIT(0); writel_relaxed(regval, GCC_REG_BASE(GX_DOMAIN_MISC)); + /* Configure Sleep and Wakeup cycles for OXILI clock */ + regval = readl_relaxed(GCC_REG_BASE(OXILI_GFX3D_CBCR)); + regval &= ~0xF0; + regval |= CLKFLAG_SLEEP_CYCLES << 4; + writel_relaxed(regval, GCC_REG_BASE(OXILI_GFX3D_CBCR)); + dev_info(&pdev->dev, "Registered GCC GFX clocks.\n"); populate_gpu_opp_table(pdev);