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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
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pwm: qpnp: do not control EN_PWM_OUTPUT for LPG lite peripherals
In LPG lite peripherals, the EN_PWM_OUTPUT bit controls whether or not the LPG_OUT signal is output onto DTEST as opposed to whether or not the LPG_OUT signal is output in general. DTEST output is not desired so ensure that the EN_PWM_OUTPUT bit is never set for LPG lite peripherals. CRs-Fixed: 803896 Change-Id: I34b7832e2b15e60b5bf2d9bcc0837af67f6d5400 Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
This commit is contained in:
Subbaraman Narayanamurthy
parent
379aabe350
commit
bc71f84cb1
1 changed files with 46 additions and 37 deletions
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@ -1,4 +1,4 @@
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/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -118,11 +118,6 @@ do { \
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#define QPNP_PWM_EN_RAMP_GEN_SHIFT 1
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#define QPNP_PWM_EN_RAMP_GEN_MASK 0x02
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#define QPNP_ENABLE_PWM(value) \
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(value |= (1 << QPNP_EN_PWM_OUTPUT_SHIFT) & QPNP_EN_PWM_OUTPUT_MASK)
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#define QPNP_DISABLE_PWM(value) (value &= ~QPNP_EN_PWM_OUTPUT_MASK)
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/* LPG Control for PWM_SYNC */
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#define QPNP_PWM_SYNC_VALUE 0x01
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#define QPNP_PWM_SYNC_MASK 0x01
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@ -369,23 +364,33 @@ static inline void qpnp_set_pwm_type_config(u8 *val, bool glitch,
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QPNP_EN_GLITCH_REMOVAL_MASK;
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}
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static int qpnp_set_control(bool pwm_hi, bool pwm_lo, bool pwm_out,
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bool pwm_src, bool ramp_gen)
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static int qpnp_set_control(struct qpnp_pwm_chip *chip, bool pwm_hi,
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bool pwm_lo, bool pwm_out, bool pwm_src, bool ramp_gen)
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{
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return (ramp_gen << QPNP_PWM_EN_RAMP_GEN_SHIFT)
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| (pwm_src << QPNP_PWM_SRC_SELECT_SHIFT)
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| (pwm_out << QPNP_EN_PWM_OUTPUT_SHIFT)
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| (pwm_lo << QPNP_EN_PWM_LO_SHIFT)
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| (pwm_hi << QPNP_EN_PWM_HIGH_SHIFT);
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int value;
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value = (ramp_gen << QPNP_PWM_EN_RAMP_GEN_SHIFT) |
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(pwm_src << QPNP_PWM_SRC_SELECT_SHIFT) |
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(pwm_lo << QPNP_EN_PWM_LO_SHIFT) |
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(pwm_hi << QPNP_EN_PWM_HIGH_SHIFT);
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if (chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE)
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value |= (pwm_out << QPNP_EN_PWM_OUTPUT_SHIFT);
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return value;
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}
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#define QPNP_ENABLE_LUT_CONTROL qpnp_set_control(0, 0, 0, 0, 1)
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#define QPNP_ENABLE_PWM_CONTROL qpnp_set_control(0, 0, 0, 1, 0)
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#define QPNP_ENABLE_PWM_MODE qpnp_set_control(1, 1, 1, 1, 0)
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#define QPNP_ENABLE_PWM_MODE_GPLED_CHANNEL qpnp_set_control(1, 1, 1, 1, 1)
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#define QPNP_ENABLE_LPG_MODE qpnp_set_control(1, 1, 1, 0, 1)
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#define QPNP_DISABLE_PWM_MODE qpnp_set_control(0, 0, 0, 1, 0)
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#define QPNP_DISABLE_LPG_MODE qpnp_set_control(0, 0, 0, 0, 1)
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#define QPNP_ENABLE_LUT_CONTROL(chip) \
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qpnp_set_control((chip), 0, 0, 0, 0, 1)
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#define QPNP_ENABLE_PWM_CONTROL(chip) \
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qpnp_set_control((chip), 0, 0, 0, 1, 0)
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#define QPNP_ENABLE_PWM_MODE(chip) \
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qpnp_set_control((chip), 1, 1, 1, 1, 0)
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#define QPNP_ENABLE_PWM_MODE_GPLED_CHANNEL(chip) \
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qpnp_set_control((chip), 1, 1, 1, 1, 1)
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#define QPNP_ENABLE_LPG_MODE(chip) \
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qpnp_set_control((chip), 1, 1, 1, 0, 1)
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#define QPNP_DISABLE_PWM_MODE(chip) \
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qpnp_set_control((chip), 0, 0, 0, 1, 0)
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#define QPNP_DISABLE_LPG_MODE(chip) \
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qpnp_set_control((chip), 0, 0, 0, 0, 1)
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#define QPNP_IS_PWM_CONFIG_SELECTED(val) (val & QPNP_PWM_SRC_SELECT_MASK)
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#define QPNP_ENABLE_PWM_MODE_ONLY_SUB_TYPE 0x80
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@ -763,11 +768,12 @@ static int qpnp_configure_pwm_control(struct qpnp_pwm_chip *chip)
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if (chip->sub_type == QPNP_PWM_MODE_ONLY_SUB_TYPE)
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return 0;
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value = QPNP_ENABLE_PWM_CONTROL;
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value = QPNP_ENABLE_PWM_CONTROL(chip);
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mask = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK |
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QPNP_EN_PWM_OUTPUT_MASK | QPNP_PWM_SRC_SELECT_MASK |
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QPNP_PWM_EN_RAMP_GEN_MASK;
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QPNP_PWM_SRC_SELECT_MASK | QPNP_PWM_EN_RAMP_GEN_MASK;
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if (chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE)
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mask |= QPNP_EN_PWM_OUTPUT_MASK;
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return qpnp_lpg_save_and_write(value, mask,
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&chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL],
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@ -781,11 +787,12 @@ static int qpnp_configure_lpg_control(struct qpnp_pwm_chip *chip)
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struct qpnp_lpg_config *lpg_config = &chip->lpg_config;
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u8 value, mask;
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value = QPNP_ENABLE_LUT_CONTROL;
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value = QPNP_ENABLE_LUT_CONTROL(chip);
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mask = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK |
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QPNP_EN_PWM_OUTPUT_MASK | QPNP_PWM_SRC_SELECT_MASK |
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QPNP_PWM_EN_RAMP_GEN_MASK;
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QPNP_PWM_SRC_SELECT_MASK | QPNP_PWM_EN_RAMP_GEN_MASK;
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if (chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE)
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mask |= QPNP_EN_PWM_OUTPUT_MASK;
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return qpnp_lpg_save_and_write(value, mask,
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&chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL],
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@ -1045,17 +1052,18 @@ static int qpnp_lpg_configure_lut_state(struct qpnp_pwm_chip *chip,
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reg1 = &chip->qpnp_lpg_registers[QPNP_RAMP_CONTROL];
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reg2 = &chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL];
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mask2 = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK |
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QPNP_EN_PWM_OUTPUT_MASK | QPNP_PWM_SRC_SELECT_MASK |
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QPNP_PWM_EN_RAMP_GEN_MASK;
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QPNP_PWM_SRC_SELECT_MASK | QPNP_PWM_EN_RAMP_GEN_MASK;
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if (chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE)
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mask2 |= QPNP_EN_PWM_OUTPUT_MASK;
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if (chip->sub_type == QPNP_LPG_CHAN_SUB_TYPE
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&& chip->revision == QPNP_LPG_REVISION_0) {
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if (state == QPNP_LUT_ENABLE) {
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QPNP_ENABLE_LUT_V0(value1);
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value2 = QPNP_ENABLE_LPG_MODE;
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value2 = QPNP_ENABLE_LPG_MODE(chip);
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} else {
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QPNP_DISABLE_LUT_V0(value1);
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value2 = QPNP_DISABLE_LPG_MODE;
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value2 = QPNP_DISABLE_LPG_MODE(chip);
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}
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mask1 = QPNP_RAMP_START_MASK;
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addr1 = SPMI_LPG_REG_ADDR(lpg_config->base_addr,
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@ -1066,9 +1074,9 @@ static int qpnp_lpg_configure_lut_state(struct qpnp_pwm_chip *chip,
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if (state == QPNP_LUT_ENABLE) {
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QPNP_ENABLE_LUT_V1(value1,
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lpg_config->lut_config.ramp_index);
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value2 = QPNP_ENABLE_LPG_MODE;
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value2 = QPNP_ENABLE_LPG_MODE(chip);
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} else {
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value2 = QPNP_DISABLE_LPG_MODE;
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value2 = QPNP_DISABLE_LPG_MODE(chip);
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}
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mask1 = value1;
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addr1 = lpg_config->lut_base_addr +
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@ -1105,8 +1113,8 @@ static int qpnp_lpg_configure_lut_state(struct qpnp_pwm_chip *chip,
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static inline int qpnp_enable_pwm_mode(struct qpnp_pwm_chip *chip)
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{
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if (chip->pwm_config.supported_sizes == QPNP_PWM_SIZE_7_8_BIT)
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return QPNP_ENABLE_PWM_MODE_GPLED_CHANNEL;
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return QPNP_ENABLE_PWM_MODE;
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return QPNP_ENABLE_PWM_MODE_GPLED_CHANNEL(chip);
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return QPNP_ENABLE_PWM_MODE(chip);
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}
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static int qpnp_lpg_configure_pwm_state(struct qpnp_pwm_chip *chip,
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@ -1128,11 +1136,12 @@ static int qpnp_lpg_configure_pwm_state(struct qpnp_pwm_chip *chip,
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if (state == QPNP_PWM_ENABLE)
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value = qpnp_enable_pwm_mode(chip);
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else
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value = QPNP_DISABLE_PWM_MODE;
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value = QPNP_DISABLE_PWM_MODE(chip);
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mask = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK |
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QPNP_EN_PWM_OUTPUT_MASK | QPNP_PWM_SRC_SELECT_MASK |
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QPNP_PWM_EN_RAMP_GEN_MASK;
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QPNP_PWM_SRC_SELECT_MASK | QPNP_PWM_EN_RAMP_GEN_MASK;
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if (chip->sub_type != QPNP_LPG_S_CHAN_SUB_TYPE)
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mask |= QPNP_EN_PWM_OUTPUT_MASK;
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}
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if (chip->in_test_mode) {
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