Merge "power: qpnp-fg: Fix IMA exception clear sequence"
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commit
c2b3e4d092
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@ -1046,6 +1046,7 @@ out:
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return rc;
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}
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#define MEM_INTF_IMA_CFG 0x52
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#define MEM_INTF_IMA_OPR_STS 0x54
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#define MEM_INTF_IMA_ERR_STS 0x5F
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#define MEM_INTF_IMA_EXP_STS 0x55
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@ -1080,15 +1081,15 @@ static int fg_check_ima_exception(struct fg_chip *chip)
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rc = err_sts;
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/* clear the error */
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ret |= fg_masked_write(chip, MEM_INTF_CFG(chip), IMA_IACS_CLR,
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IMA_IACS_CLR, 1);
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ret |= fg_masked_write(chip, chip->mem_base + MEM_INTF_IMA_CFG,
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IMA_IACS_CLR, IMA_IACS_CLR, 1);
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temp = 0x4;
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ret |= fg_write(chip, &temp, MEM_INTF_ADDR_LSB(chip) + 1, 1);
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temp = 0x0;
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ret |= fg_write(chip, &temp, MEM_INTF_WR_DATA0(chip) + 3, 1);
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ret |= fg_read(chip, &temp, MEM_INTF_RD_DATA0(chip) + 3, 1);
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ret |= fg_masked_write(chip, MEM_INTF_CFG(chip),
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IMA_IACS_CLR, 0, 1);
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ret |= fg_masked_write(chip, chip->mem_base + MEM_INTF_IMA_CFG,
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IMA_IACS_CLR, 0, 1);
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if (!ret)
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return -EAGAIN;
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else
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@ -1124,6 +1125,8 @@ static int fg_check_iacs_ready(struct fg_chip *chip)
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if (!timeout || rc) {
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pr_err("IACS_RDY not set\n");
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/* perform IACS_CLR sequence */
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fg_check_ima_exception(chip);
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return -EBUSY;
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}
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@ -1375,7 +1378,8 @@ retry:
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pr_info("Start beat_count = %x End beat_count = %x\n",
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start_beat_count, end_beat_count);
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if (start_beat_count != end_beat_count) {
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pr_err("Beat count do not match - retry transaction\n");
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if (fg_debug_mask & FG_MEM_DEBUG_READS)
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pr_info("Beat count do not match - retry transaction\n");
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goto retry;
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}
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out:
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