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ASoC: wcd9330: Update MCLK Frequency select for 12.288MHz clock
Some platforms will enable 12.288MHz clock to CODEC for normal operation. Update the MCLK Fselect correctly if 12.288MHz clock is used. Change-Id: Ib6c9bbe0323441b637ba742b12ef04c75f6e8207 Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
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1 changed files with 4 additions and 2 deletions
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@ -8751,9 +8751,11 @@ static int tomtom_codec_probe(struct snd_soc_codec *codec)
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tomtom->micb_2_users = 0;
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tomtom_update_reg_defaults(codec);
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pr_debug("%s: MCLK Rate = %x\n", __func__, wcd9xxx->mclk_rate);
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if (wcd9xxx->mclk_rate == TOMTOM_MCLK_CLK_12P288MHZ)
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if (wcd9xxx->mclk_rate == TOMTOM_MCLK_CLK_12P288MHZ) {
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snd_soc_update_bits(codec, TOMTOM_A_CHIP_CTL, 0x06, 0x0);
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else if (wcd9xxx->mclk_rate == TOMTOM_MCLK_CLK_9P6MHZ)
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snd_soc_update_bits(codec, TOMTOM_A_RX_COM_TIMER_DIV,
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0x01, 0x01);
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} else if (wcd9xxx->mclk_rate == TOMTOM_MCLK_CLK_9P6MHZ)
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snd_soc_update_bits(codec, TOMTOM_A_CHIP_CTL, 0x06, 0x2);
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tomtom_codec_init_reg(codec);
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