ASoC: wcd9330: Update MCLK Frequency select for 12.288MHz clock

Some platforms will enable 12.288MHz clock to CODEC for normal
operation. Update the MCLK Fselect correctly if 12.288MHz clock
is used.

Change-Id: Ib6c9bbe0323441b637ba742b12ef04c75f6e8207
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
This commit is contained in:
Phani Kumar Uppalapati 2015-04-09 00:04:58 -07:00 committed by Gerrit - the friendly Code Review server
parent 60d2ed6dc0
commit c31fa29db5

View file

@ -8751,9 +8751,11 @@ static int tomtom_codec_probe(struct snd_soc_codec *codec)
tomtom->micb_2_users = 0;
tomtom_update_reg_defaults(codec);
pr_debug("%s: MCLK Rate = %x\n", __func__, wcd9xxx->mclk_rate);
if (wcd9xxx->mclk_rate == TOMTOM_MCLK_CLK_12P288MHZ)
if (wcd9xxx->mclk_rate == TOMTOM_MCLK_CLK_12P288MHZ) {
snd_soc_update_bits(codec, TOMTOM_A_CHIP_CTL, 0x06, 0x0);
else if (wcd9xxx->mclk_rate == TOMTOM_MCLK_CLK_9P6MHZ)
snd_soc_update_bits(codec, TOMTOM_A_RX_COM_TIMER_DIV,
0x01, 0x01);
} else if (wcd9xxx->mclk_rate == TOMTOM_MCLK_CLK_9P6MHZ)
snd_soc_update_bits(codec, TOMTOM_A_CHIP_CTL, 0x06, 0x2);
tomtom_codec_init_reg(codec);