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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-09-21 11:53:01 +00:00
[PATCH] powerpc: Update MPIC workarounds
Cleanup the MPIC IO-APIC workarounds, make them a bit more generic, smaller and faster. Signed-off-by: Segher Boessenkool <segher@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -175,57 +175,57 @@ static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source_no
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return mpic->fixups[source_no].base != NULL;
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return mpic->fixups[source_no].base != NULL;
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}
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}
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static inline void mpic_apic_end_irq(struct mpic *mpic, unsigned int source_no)
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static inline void mpic_apic_end_irq(struct mpic *mpic, unsigned int source_no)
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{
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{
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struct mpic_irq_fixup *fixup = &mpic->fixups[source_no];
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struct mpic_irq_fixup *fixup = &mpic->fixups[source_no];
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u32 tmp;
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spin_lock(&mpic->fixup_lock);
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spin_lock(&mpic->fixup_lock);
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writeb(0x11 + 2 * fixup->irq, fixup->base);
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writeb(0x11 + 2 * fixup->irq, fixup->base + 2);
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tmp = readl(fixup->base + 2);
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writel(fixup->data, fixup->base + 4);
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writel(tmp | 0x80000000ul, fixup->base + 2);
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/* config writes shouldn't be posted but let's be safe ... */
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(void)readl(fixup->base + 2);
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spin_unlock(&mpic->fixup_lock);
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spin_unlock(&mpic->fixup_lock);
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}
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}
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static void __init mpic_amd8111_read_irq(struct mpic *mpic, u8 __iomem *devbase)
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static void __init mpic_scan_ioapic(struct mpic *mpic, u8 __iomem *devbase)
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{
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{
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int i, irq;
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int i, irq, n;
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u32 tmp;
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u32 tmp;
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u8 pos;
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printk(KERN_INFO "mpic: - Workarounds on AMD 8111 @ %p\n", devbase);
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for (pos = readb(devbase + 0x34); pos; pos = readb(devbase + pos + 1)) {
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u8 id = readb(devbase + pos);
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for (i=0; i < 24; i++) {
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if (id == 0x08) {
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writeb(0x10 + 2*i, devbase + 0xf2);
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id = readb(devbase + pos + 3);
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tmp = readl(devbase + 0xf4);
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if (id == 0x80)
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if ((tmp & 0x1) || !(tmp & 0x20))
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break;
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}
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}
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if (pos == 0)
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return;
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printk(KERN_INFO "mpic: - Workarounds @ %p, pos = 0x%02x\n", devbase, pos);
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devbase += pos;
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writeb(0x01, devbase + 2);
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n = (readl(devbase + 4) >> 16) & 0xff;
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for (i = 0; i <= n; i++) {
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writeb(0x10 + 2 * i, devbase + 2);
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tmp = readl(devbase + 4);
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if ((tmp & 0x21) != 0x20)
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continue;
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continue;
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irq = (tmp >> 16) & 0xff;
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irq = (tmp >> 16) & 0xff;
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mpic->fixups[irq].irq = i;
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mpic->fixups[irq].irq = i;
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mpic->fixups[irq].base = devbase + 0xf2;
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mpic->fixups[irq].base = devbase;
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writeb(0x11 + 2 * i, devbase + 2);
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mpic->fixups[irq].data = readl(devbase + 4) | 0x80000000;
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}
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}
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}
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}
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static void __init mpic_amd8131_read_irq(struct mpic *mpic, u8 __iomem *devbase)
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{
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int i, irq;
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u32 tmp;
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printk(KERN_INFO "mpic: - Workarounds on AMD 8131 @ %p\n", devbase);
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for (i=0; i < 4; i++) {
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writeb(0x10 + 2*i, devbase + 0xba);
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tmp = readl(devbase + 0xbc);
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if ((tmp & 0x1) || !(tmp & 0x20))
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continue;
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irq = (tmp >> 16) & 0xff;
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mpic->fixups[irq].irq = i;
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mpic->fixups[irq].base = devbase + 0xba;
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}
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}
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static void __init mpic_scan_ioapics(struct mpic *mpic)
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static void __init mpic_scan_ioapics(struct mpic *mpic)
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{
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{
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unsigned int devfn;
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unsigned int devfn;
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@ -241,21 +241,19 @@ static void __init mpic_scan_ioapics(struct mpic *mpic)
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/* Init spinlock */
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/* Init spinlock */
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spin_lock_init(&mpic->fixup_lock);
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spin_lock_init(&mpic->fixup_lock);
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/* Map u3 config space. We assume all IO-APICs are on the primary bus
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/* Map U3 config space. We assume all IO-APICs are on the primary bus
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* and slot will never be above "0xf" so we only need to map 32k
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* so we only need to map 64kB.
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*/
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*/
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cfgspace = (unsigned char __iomem *)ioremap(0xf2000000, 0x8000);
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cfgspace = ioremap(0xf2000000, 0x10000);
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BUG_ON(cfgspace == NULL);
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BUG_ON(cfgspace == NULL);
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/* Now we scan all slots. We do a very quick scan, we read the header type,
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/* Now we scan all slots. We do a very quick scan, we read the header type,
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* vendor ID and device ID only, that's plenty enough
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* vendor ID and device ID only, that's plenty enough
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*/
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*/
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for (devfn = 0; devfn < PCI_DEVFN(0x10,0); devfn ++) {
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for (devfn = 0; devfn < 0x100; devfn++) {
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u8 __iomem *devbase = cfgspace + (devfn << 8);
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u8 __iomem *devbase = cfgspace + (devfn << 8);
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u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
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u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
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u32 l = readl(devbase + PCI_VENDOR_ID);
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u32 l = readl(devbase + PCI_VENDOR_ID);
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u16 vendor_id, device_id;
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int multifunc = 0;
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DBG("devfn %x, l: %x\n", devfn, l);
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DBG("devfn %x, l: %x\n", devfn, l);
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@ -264,21 +262,11 @@ static void __init mpic_scan_ioapics(struct mpic *mpic)
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l == 0x0000ffff || l == 0xffff0000)
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l == 0x0000ffff || l == 0xffff0000)
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goto next;
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goto next;
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/* Check if it's a multifunction device (only really used
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mpic_scan_ioapic(mpic, devbase);
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* to function 0 though
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*/
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multifunc = !!(hdr_type & 0x80);
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vendor_id = l & 0xffff;
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device_id = (l >> 16) & 0xffff;
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/* If a known device, go to fixup setup code */
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if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7460)
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mpic_amd8111_read_irq(mpic, devbase);
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if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7450)
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mpic_amd8131_read_irq(mpic, devbase);
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next:
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next:
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/* next device, if function 0 */
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/* next device, if function 0 */
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if ((PCI_FUNC(devfn) == 0) && !multifunc)
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if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
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devfn += 7;
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devfn += 7;
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}
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}
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}
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}
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@ -117,7 +117,8 @@ typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
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struct mpic_irq_fixup
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struct mpic_irq_fixup
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{
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{
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u8 __iomem *base;
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u8 __iomem *base;
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unsigned int irq;
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u32 data;
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unsigned int irq;
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};
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};
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#endif /* CONFIG_MPIC_BROKEN_U3 */
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#endif /* CONFIG_MPIC_BROKEN_U3 */
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