mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-11-07 04:09:21 +00:00
Resurrect Cobalt support for 2.6.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
049b13c358
commit
c4ed38a0c6
14 changed files with 279 additions and 226 deletions
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@ -323,6 +323,7 @@ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
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# Cobalt Server
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#
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core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
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cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/cobalt
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load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
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#
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@ -2,6 +2,6 @@
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# Makefile for the Cobalt micro systems family specific parts of the kernel
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#
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obj-y := irq.o int-handler.o reset.o setup.o promcon.o
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obj-y := irq.o int-handler.o reset.o setup.o
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EXTRA_AFLAGS := $(CFLAGS)
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@ -18,8 +18,8 @@
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SAVE_ALL
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CLI
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la ra, ret_from_irq
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move a1, sp
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PTR_LA ra, ret_from_irq
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move a0, sp
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j cobalt_irq
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END(cobalt_handle_int)
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@ -10,6 +10,8 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <asm/i8259.h>
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#include <asm/irq_cpu.h>
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@ -25,8 +27,8 @@ extern void cobalt_handle_int(void);
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* the CPU interrupt lines, and ones that come in on the via chip. The CPU
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* mappings are:
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*
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* 16, - Software interrupt 0 (unused) IE_SW0
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* 17 - Software interrupt 1 (unused) IE_SW0
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* 16 - Software interrupt 0 (unused) IE_SW0
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* 17 - Software interrupt 1 (unused) IE_SW1
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* 18 - Galileo chip (timer) IE_IRQ0
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* 19 - Tulip 0 + NCR SCSI IE_IRQ1
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* 20 - Tulip 1 IE_IRQ2
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@ -42,61 +44,94 @@ extern void cobalt_handle_int(void);
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* 15 - IDE1
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*/
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asmlinkage void cobalt_irq(struct pt_regs *regs)
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static inline void galileo_irq(struct pt_regs *regs)
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{
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unsigned int pending = read_c0_status() & read_c0_cause();
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unsigned int mask, pending, devfn;
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if (pending & CAUSEF_IP2) { /* int 18 */
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unsigned long irq_src = GALILEO_INL(GT_INTRCAUSE_OFS);
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mask = GALILEO_INL(GT_INTRMASK_OFS);
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pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;
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/* Check for timer irq ... */
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if (irq_src & GALILEO_T0EXP) {
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/* Clear the int line */
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GALILEO_OUTL(0, GT_INTRCAUSE_OFS);
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do_IRQ(COBALT_TIMER_IRQ, regs);
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}
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return;
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}
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if (pending & GALILEO_INTR_T0EXP) {
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if (pending & CAUSEF_IP6) { /* int 22 */
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int irq = i8259_irq();
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GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
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do_IRQ(COBALT_GALILEO_IRQ, regs);
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if (irq >= 0)
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do_IRQ(irq, regs);
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return;
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}
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} else if (pending & GALILEO_INTR_RETRY_CTR) {
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if (pending & CAUSEF_IP3) { /* int 19 */
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do_IRQ(COBALT_ETH0_IRQ, regs);
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return;
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}
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devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;
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GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);
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printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",
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PCI_SLOT(devfn), PCI_FUNC(devfn));
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if (pending & CAUSEF_IP4) { /* int 20 */
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do_IRQ(COBALT_ETH1_IRQ, regs);
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return;
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}
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} else {
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if (pending & CAUSEF_IP5) { /* int 21 */
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do_IRQ(COBALT_SERIAL_IRQ, regs);
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return;
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}
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if (pending & CAUSEF_IP7) { /* int 23 */
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do_IRQ(COBALT_QUBE_SLOT_IRQ, regs);
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return;
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GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);
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printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);
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}
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}
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static inline void via_pic_irq(struct pt_regs *regs)
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{
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int irq;
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irq = i8259_irq();
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if (irq >= 0)
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do_IRQ(irq, regs);
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}
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asmlinkage void cobalt_irq(struct pt_regs *regs)
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{
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unsigned pending;
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pending = read_c0_status() & read_c0_cause();
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if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
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galileo_irq(regs);
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else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
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via_pic_irq(regs);
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else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
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do_IRQ(COBALT_CPU_IRQ + 3, regs);
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else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
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do_IRQ(COBALT_CPU_IRQ + 4, regs);
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else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
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do_IRQ(COBALT_CPU_IRQ + 5, regs);
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else if (pending & CAUSEF_IP7) /* IRQ 23 */
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do_IRQ(COBALT_CPU_IRQ + 7, regs);
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}
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static struct irqaction irq_via = {
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no_action, 0, { { 0, } }, "cascade", NULL, NULL
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};
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void __init arch_init_irq(void)
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{
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/*
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* Mask all Galileo interrupts. The Galileo
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* handler is set in cobalt_timer_setup()
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*/
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GALILEO_OUTL(0, GT_INTRMASK_OFS);
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set_except_vector(0, cobalt_handle_int);
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init_i8259_irqs(); /* 0 ... 15 */
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mips_cpu_irq_init(16); /* 16 ... 23 */
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mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
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/*
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* Mask all cpu interrupts
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* (except IE4, we already masked those at VIA level)
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*/
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change_c0_status(ST0_IM, IE_IRQ4);
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setup_irq(COBALT_VIA_IRQ, &irq_via);
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}
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@ -1,87 +0,0 @@
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/*
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* PROM console for Cobalt Raq2
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997 by Ralf Baechle
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* Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
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*
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*/
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/kdev_t.h>
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#include <linux/serial_reg.h>
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#include <asm/delay.h>
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#include <asm/serial.h>
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#include <asm/io.h>
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static unsigned long port = 0xc800000;
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static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr)
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{
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char lsr;
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do {
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lsr = inb(ioaddr + UART_LSR);
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} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
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outb(ch, ioaddr + UART_TX);
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}
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static __inline__ char ns16550_cons_get_char(unsigned long ioaddr)
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{
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while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0)
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udelay(1);
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return inb(ioaddr + UART_RX);
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}
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void ns16550_console_write(struct console *co, const char *s, unsigned count)
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{
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char lsr, ier;
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unsigned i;
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ier = inb(port + UART_IER);
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outb(0x00, port + UART_IER);
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for (i=0; i < count; i++, s++) {
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if(*s == '\n')
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ns16550_cons_put_char('\r', port);
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ns16550_cons_put_char(*s, port);
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}
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do {
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lsr = inb(port + UART_LSR);
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} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
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outb(ier, port + UART_IER);
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}
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char getDebugChar(void)
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{
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return ns16550_cons_get_char(port);
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}
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void putDebugChar(char kgdb_char)
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{
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ns16550_cons_put_char(kgdb_char, port);
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}
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static struct console ns16550_console = {
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.name = "prom",
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.setup = NULL,
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.write = ns16550_console_write,
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.flags = CON_PRINTBUFFER,
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.index = -1,
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};
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static int __init ns16550_setup_console(void)
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{
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register_console(&ns16550_console);
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return 0;
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}
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console_initcall(ns16550_setup_console);
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@ -16,48 +16,45 @@
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#include <asm/reboot.h>
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#include <asm/system.h>
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#include <asm/mipsregs.h>
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void cobalt_machine_restart(char *command)
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{
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*(volatile char *)0xbc000000 = 0x0f;
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/*
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* Ouch, we're still alive ... This time we take the silver bullet ...
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* ... and find that we leave the hardware in a state in which the
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* kernel in the flush locks up somewhen during of after the PCI
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* detection stuff.
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*/
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set_c0_status(ST0_BEV | ST0_ERL);
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change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
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flush_cache_all();
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write_c0_wired(0);
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__asm__ __volatile__(
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"jr\t%0"
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:
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: "r" (0xbfc00000));
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}
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extern int led_state;
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#define kLED 0xBC000000
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#define LEDSet(x) (*(volatile unsigned char *) kLED) = (( unsigned char)x)
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#include <asm/cobalt/cobalt.h>
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void cobalt_machine_halt(void)
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{
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int mark;
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int state, last, diff;
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unsigned long mark;
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/* Blink our cute? little LED (number 3)... */
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while (1) {
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led_state = led_state | ( 1 << 3 );
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LEDSet(led_state);
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mark = jiffies;
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while (jiffies<(mark+HZ));
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led_state = led_state & ~( 1 << 3 );
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LEDSet(led_state);
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mark = jiffies;
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while (jiffies<(mark+HZ));
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/*
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* turn off bar on Qube, flash power off LED on RaQ (0.5Hz)
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*
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* restart if ENTER and SELECT are pressed
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*/
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last = COBALT_KEY_PORT;
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for (state = 0;;) {
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state ^= COBALT_LED_POWER_OFF;
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COBALT_LED_PORT = state;
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diff = COBALT_KEY_PORT ^ last;
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last ^= diff;
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if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)))
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COBALT_LED_PORT = COBALT_LED_RESET;
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for (mark = jiffies; jiffies - mark < HZ;)
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;
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}
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}
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void cobalt_machine_restart(char *command)
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{
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COBALT_LED_PORT = COBALT_LED_RESET;
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/* we should never get here */
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cobalt_machine_halt();
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}
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/*
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* This triggers the luser mode device driver for the power switch ;-)
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*/
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@ -13,6 +13,8 @@
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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@ -21,6 +23,7 @@
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#include <asm/processor.h>
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#include <asm/reboot.h>
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#include <asm/gt64120.h>
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#include <asm/serial.h>
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#include <asm/cobalt/cobalt.h>
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@ -30,45 +33,44 @@ extern void cobalt_machine_power_off(void);
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int cobalt_board_id;
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static char my_cmdline[CL_SIZE] = {
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"console=ttyS0,115200 "
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#ifdef CONFIG_IP_PNP
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"ip=on "
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#endif
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#ifdef CONFIG_ROOT_NFS
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"root=/dev/nfs "
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#else
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"root=/dev/hda1 "
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#endif
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};
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const char *get_system_type(void)
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{
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switch (cobalt_board_id) {
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case COBALT_BRD_ID_QUBE1:
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return "Cobalt Qube";
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case COBALT_BRD_ID_RAQ1:
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return "Cobalt RaQ";
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case COBALT_BRD_ID_QUBE2:
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return "Cobalt Qube2";
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case COBALT_BRD_ID_RAQ2:
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return "Cobalt RaQ2";
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}
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return "MIPS Cobalt";
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}
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static void __init cobalt_timer_setup(struct irqaction *irq)
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{
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/* Load timer value for 150 Hz */
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GALILEO_OUTL(500000, GT_TC0_OFS);
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/* Load timer value for 1KHz (TCLK is 50MHz) */
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GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS);
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/* Register our timer interrupt */
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setup_irq(COBALT_TIMER_IRQ, irq);
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/* Enable timer */
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GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS);
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/* Enable timer ints */
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GALILEO_OUTL((GALILEO_ENTC0 | GALILEO_SELTC0), GT_TC_CONTROL_OFS);
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/* Unmask timer int */
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GALILEO_OUTL(0x100, GT_INTRMASK_OFS);
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/* Register interrupt */
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setup_irq(COBALT_GALILEO_IRQ, irq);
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/* Enable interrupt */
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GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
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}
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extern struct pci_ops gt64111_pci_ops;
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static struct resource cobalt_mem_resource = {
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"GT64111 PCI MEM", GT64111_IO_BASE, 0xffffffffUL, IORESOURCE_MEM
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"PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM
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};
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static struct resource cobalt_io_resource = {
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"GT64111 IO MEM", 0x00001000UL, 0x0fffffffUL, IORESOURCE_IO
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"PCI I/O", 0x1000, 0xffff, IORESOURCE_IO
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};
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static struct resource cobalt_io_resources[] = {
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@ -86,11 +88,12 @@ static struct pci_controller cobalt_pci_controller = {
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.mem_resource = &cobalt_mem_resource,
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.mem_offset = 0,
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.io_resource = &cobalt_io_resource,
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.io_offset = 0x00001000UL - GT64111_IO_BASE
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.io_offset = 0 - GT64111_IO_BASE
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};
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void __init plat_setup(void)
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{
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static struct uart_port uart;
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unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
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int i;
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@ -100,7 +103,10 @@ void __init plat_setup(void)
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board_timer_setup = cobalt_timer_setup;
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set_io_port_base(KSEG1ADDR(GT64111_IO_BASE));
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set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
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/* I/O port resource must include UART and LCD/buttons */
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ioport_resource.end = 0x0fffffff;
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/*
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* This is a prom style console. We just poke at the
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@ -120,25 +126,61 @@ void __init plat_setup(void)
|
|||
cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
|
||||
cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
|
||||
|
||||
printk("Cobalt board ID: %d\n", cobalt_board_id);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
register_pci_controller(&cobalt_pci_controller);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_8250
|
||||
if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
|
||||
|
||||
uart.line = 0;
|
||||
uart.type = PORT_UNKNOWN;
|
||||
uart.uartclk = 18432000;
|
||||
uart.irq = COBALT_SERIAL_IRQ;
|
||||
uart.flags = STD_COM_FLAGS;
|
||||
uart.iobase = 0xc800000;
|
||||
uart.iotype = UPIO_PORT;
|
||||
|
||||
early_serial_setup(&uart);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Prom init. We read our one and only communication with the firmware.
|
||||
* Grab the amount of installed memory
|
||||
* Grab the amount of installed memory.
|
||||
* Better boot loaders (CoLo) pass a command line too :-)
|
||||
*/
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
int argc = fw_arg0;
|
||||
|
||||
strcpy(arcs_cmdline, my_cmdline);
|
||||
int narg, indx, posn, nchr;
|
||||
unsigned long memsz;
|
||||
char **argv;
|
||||
|
||||
mips_machgroup = MACH_GROUP_COBALT;
|
||||
|
||||
add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM);
|
||||
memsz = fw_arg0 & 0x7fff0000;
|
||||
narg = fw_arg0 & 0x0000ffff;
|
||||
|
||||
if (narg) {
|
||||
arcs_cmdline[0] = '\0';
|
||||
argv = (char **) fw_arg1;
|
||||
posn = 0;
|
||||
for (indx = 1; indx < narg; ++indx) {
|
||||
nchr = strlen(argv[indx]);
|
||||
if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
|
||||
break;
|
||||
if (posn)
|
||||
arcs_cmdline[posn++] = ' ';
|
||||
strcpy(arcs_cmdline + posn, argv[indx]);
|
||||
posn += nchr;
|
||||
}
|
||||
}
|
||||
|
||||
add_memory_region(0x0, memsz, BOOT_MEM_RAM);
|
||||
}
|
||||
|
||||
unsigned long __init prom_free_prom_memory(void)
|
||||
|
|
|
|||
|
|
@ -21,6 +21,20 @@
|
|||
|
||||
extern int cobalt_board_id;
|
||||
|
||||
static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
|
||||
{
|
||||
if (dev->devfn == PCI_DEVFN(0, 0) &&
|
||||
(dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
|
||||
|
||||
dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
|
||||
|
||||
printk(KERN_INFO "Galileo: fixed bridge class\n");
|
||||
}
|
||||
}
|
||||
|
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
|
||||
qube_raq_galileo_early_fixup);
|
||||
|
||||
static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
|
||||
{
|
||||
unsigned short cfgword;
|
||||
|
|
@ -48,6 +62,9 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
|
|||
{
|
||||
unsigned short galileo_id;
|
||||
|
||||
if (dev->devfn != PCI_DEVFN(0, 0))
|
||||
return;
|
||||
|
||||
/* Fix PCI latency-timer and cache-line-size values in Galileo
|
||||
* host bridge.
|
||||
*/
|
||||
|
|
@ -55,6 +72,13 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
|
|||
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
|
||||
|
||||
/*
|
||||
* The code described by the comment below has been removed
|
||||
* as it causes bus mastering by the Ethernet controllers
|
||||
* to break under any kind of network load. We always set
|
||||
* the retry timeouts to their maximum.
|
||||
*
|
||||
* --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
|
||||
*
|
||||
* On all machines prior to Q2, we had the STOP line disconnected
|
||||
* from Galileo to VIA on PCI. The new Galileo does not function
|
||||
* correctly unless we have it connected.
|
||||
|
|
@ -64,21 +88,43 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
|
|||
*/
|
||||
pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
|
||||
galileo_id &= 0xff; /* mask off class info */
|
||||
|
||||
printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
|
||||
|
||||
#if 0
|
||||
if (galileo_id >= 0x10) {
|
||||
/* New Galileo, assumes PCI stop line to VIA is connected. */
|
||||
GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
|
||||
} else if (galileo_id == 0x1 || galileo_id == 0x2) {
|
||||
} else if (galileo_id == 0x1 || galileo_id == 0x2)
|
||||
#endif
|
||||
{
|
||||
signed int timeo;
|
||||
/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
|
||||
timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
|
||||
/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
|
||||
GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS);
|
||||
GALILEO_OUTL(
|
||||
(0xff << 16) | /* retry count */
|
||||
(0xff << 8) | /* timeout 1 */
|
||||
0xff, /* timeout 0 */
|
||||
GT_PCI0_TOR_OFS);
|
||||
|
||||
/* enable PCI retry exceeded interrupt */
|
||||
GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
|
||||
}
|
||||
}
|
||||
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GALILEO, PCI_ANY_ID,
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
|
||||
qube_raq_galileo_fixup);
|
||||
|
||||
static char irq_tab_qube1[] __initdata = {
|
||||
[COBALT_PCICONF_CPU] = 0,
|
||||
[COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ,
|
||||
[COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
|
||||
[COBALT_PCICONF_VIA] = 0,
|
||||
[COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
|
||||
[COBALT_PCICONF_ETH1] = 0
|
||||
};
|
||||
|
||||
static char irq_tab_cobalt[] __initdata = {
|
||||
[COBALT_PCICONF_CPU] = 0,
|
||||
[COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
|
||||
|
|
@ -99,6 +145,9 @@ static char irq_tab_raq2[] __initdata = {
|
|||
|
||||
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
|
||||
return irq_tab_qube1[slot];
|
||||
|
||||
if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
|
||||
return irq_tab_raq2[slot];
|
||||
|
||||
|
|
|
|||
|
|
@ -18,15 +18,15 @@
|
|||
#include <asm/cobalt/cobalt.h>
|
||||
|
||||
/*
|
||||
* Accessing device 31 hangs the GT64120. Not sure if this will also hang
|
||||
* the GT64111, let's be paranoid for now.
|
||||
* Device 31 on the GT64111 is used to generate PCI special
|
||||
* cycles, so we shouldn't expected to find a device there ...
|
||||
*/
|
||||
static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn)
|
||||
{
|
||||
if (bus->number == 0 && devfn == PCI_DEVFN(31, 0))
|
||||
return -1;
|
||||
if (bus->number == 0 && PCI_SLOT(devfn) < 31)
|
||||
return 0;
|
||||
|
||||
return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
|
|
|
|||
|
|
@ -575,8 +575,8 @@ static inline int button_pressed(void)
|
|||
|
||||
static int lcd_waiters = 0;
|
||||
|
||||
static long lcd_read(struct inode *inode, struct file *file, char *buf,
|
||||
unsigned long count)
|
||||
static ssize_t lcd_read(struct file *file, char *buf,
|
||||
size_t count, loff_t *ofs)
|
||||
{
|
||||
long buttons_now;
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ static int timeout(volatile unsigned long);
|
|||
#define MAX_IDLE_TIME 120
|
||||
|
||||
struct lcd_display {
|
||||
unsigned long buttons;
|
||||
unsigned buttons;
|
||||
int size1;
|
||||
int size2;
|
||||
unsigned char line1[LCD_CHARS_PER_LINE];
|
||||
|
|
|
|||
|
|
@ -19,18 +19,23 @@
|
|||
* 9 - PCI
|
||||
* 14 - IDE0
|
||||
* 15 - IDE1
|
||||
*
|
||||
*/
|
||||
#define COBALT_QUBE_SLOT_IRQ 9
|
||||
|
||||
/*
|
||||
* CPU IRQs are 16 ... 23
|
||||
*/
|
||||
#define COBALT_TIMER_IRQ 18
|
||||
#define COBALT_SCC_IRQ 19 /* pre-production has 85C30 */
|
||||
#define COBALT_RAQ_SCSI_IRQ 19
|
||||
#define COBALT_ETH0_IRQ 19
|
||||
#define COBALT_ETH1_IRQ 20
|
||||
#define COBALT_SERIAL_IRQ 21
|
||||
#define COBALT_SCSI_IRQ 21
|
||||
#define COBALT_VIA_IRQ 22 /* Chained to VIA ISA bridge */
|
||||
#define COBALT_QUBE_SLOT_IRQ 23
|
||||
#define COBALT_CPU_IRQ 16
|
||||
|
||||
#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
|
||||
#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */
|
||||
#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
|
||||
#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
|
||||
#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
|
||||
#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4)
|
||||
#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5)
|
||||
#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5)
|
||||
#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */
|
||||
|
||||
/*
|
||||
* PCI configuration space manifest constants. These are wired into
|
||||
|
|
@ -69,16 +74,21 @@
|
|||
* Most of this really should go into a separate GT64111 header file.
|
||||
*/
|
||||
#define GT64111_IO_BASE 0x10000000UL
|
||||
#define GT64111_IO_END 0x11ffffffUL
|
||||
#define GT64111_MEM_BASE 0x12000000UL
|
||||
#define GT64111_MEM_END 0x13ffffffUL
|
||||
#define GT64111_BASE 0x14000000UL
|
||||
#define GALILEO_REG(ofs) (KSEG0 + GT64111_BASE + (unsigned long)(ofs))
|
||||
#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
|
||||
|
||||
#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port))
|
||||
#define GALILEO_OUTL(val, port) \
|
||||
do { \
|
||||
*(volatile unsigned int *) GALILEO_REG(port) = (port); \
|
||||
*(volatile unsigned int *) GALILEO_REG(port) = (val); \
|
||||
} while (0)
|
||||
|
||||
#define GALILEO_T0EXP 0x0100
|
||||
#define GALILEO_INTR_T0EXP (1 << 8)
|
||||
#define GALILEO_INTR_RETRY_CTR (1 << 20)
|
||||
|
||||
#define GALILEO_ENTC0 0x01
|
||||
#define GALILEO_SELTC0 0x02
|
||||
|
||||
|
|
@ -86,5 +96,21 @@ do { \
|
|||
GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \
|
||||
(PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
|
||||
|
||||
#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
|
||||
# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */
|
||||
# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */
|
||||
# define COBALT_LED_WEB (1 << 2) /* RaQ */
|
||||
# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */
|
||||
# define COBALT_LED_RESET 0x0f
|
||||
|
||||
#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
|
||||
# define COBALT_KEY_CLEAR (1 << 1)
|
||||
# define COBALT_KEY_LEFT (1 << 2)
|
||||
# define COBALT_KEY_UP (1 << 3)
|
||||
# define COBALT_KEY_DOWN (1 << 4)
|
||||
# define COBALT_KEY_RIGHT (1 << 5)
|
||||
# define COBALT_KEY_ENTER (1 << 6)
|
||||
# define COBALT_KEY_SELECT (1 << 7)
|
||||
# define COBALT_KEY_MASK 0xfe
|
||||
|
||||
#endif /* __ASM_COBALT_H */
|
||||
|
|
|
|||
1
include/asm-mips/cobalt/mach-gt64120.h
Normal file
1
include/asm-mips/cobalt/mach-gt64120.h
Normal file
|
|
@ -0,0 +1 @@
|
|||
/* there's something here ... in the dark */
|
||||
|
|
@ -52,16 +52,6 @@
|
|||
#define JAZZ_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_COBALT
|
||||
#include <asm/cobalt/cobalt.h>
|
||||
#define COBALT_BASE_BAUD (18432000 / 16)
|
||||
#define COBALT_SERIAL_PORT_DEFNS \
|
||||
/* UART CLK PORT IRQ FLAGS */ \
|
||||
{ 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS }, /* ttyS0 */
|
||||
#else
|
||||
#define COBALT_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Both Galileo boards have the same UART mappings.
|
||||
*/
|
||||
|
|
@ -342,7 +332,6 @@
|
|||
#endif /* CONFIG_SGI_IP32 */
|
||||
|
||||
#define SERIAL_PORT_DFNS \
|
||||
COBALT_SERIAL_PORT_DEFNS \
|
||||
DDB5477_SERIAL_PORT_DEFNS \
|
||||
EV96100_SERIAL_PORT_DEFNS \
|
||||
IP32_SERIAL_PORT_DEFNS \
|
||||
|
|
|
|||
Loading…
Reference in a new issue