mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-09-21 20:04:01 +00:00
[PATCH] ppc32/8xx: Fix r3 trashing due to 8MB TLB page instantiation
Instantiation of 8MB pages on the TLB cache for the kernel static mapping trashes r3 register on !CONFIG_8xx_CPU6 configurations. This ensures r3 gets saved and restored. Signed-off-by: Marcelo Tosatti <marcelo@kvack.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
parent
e4de00215c
commit
c51e078f82
1 changed files with 0 additions and 4 deletions
|
@ -355,9 +355,7 @@ InstructionTLBMiss:
|
||||||
|
|
||||||
. = 0x1200
|
. = 0x1200
|
||||||
DataStoreTLBMiss:
|
DataStoreTLBMiss:
|
||||||
#ifdef CONFIG_8xx_CPU6
|
|
||||||
stw r3, 8(r0)
|
stw r3, 8(r0)
|
||||||
#endif
|
|
||||||
DO_8xx_CPU6(0x3f80, r3)
|
DO_8xx_CPU6(0x3f80, r3)
|
||||||
mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
|
mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
|
||||||
mfcr r10
|
mfcr r10
|
||||||
|
@ -417,9 +415,7 @@ DataStoreTLBMiss:
|
||||||
lwz r11, 0(r0)
|
lwz r11, 0(r0)
|
||||||
mtcr r11
|
mtcr r11
|
||||||
lwz r11, 4(r0)
|
lwz r11, 4(r0)
|
||||||
#ifdef CONFIG_8xx_CPU6
|
|
||||||
lwz r3, 8(r0)
|
lwz r3, 8(r0)
|
||||||
#endif
|
|
||||||
rfi
|
rfi
|
||||||
|
|
||||||
/* This is an instruction TLB error on the MPC8xx. This could be due
|
/* This is an instruction TLB error on the MPC8xx. This could be due
|
||||||
|
|
Loading…
Reference in a new issue