mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-11-01 10:33:27 +00:00
ASoC: Automatically calculate clock ratio for WM8580
Implement set_sysclk() and then rather than assuming 256fs use the supplied value to calculate and configure the clock ratio for the currently used sample rate. As a side effect we also end up implementing clock selection for the ADC path. In order to avoid confusion remove the existing set_clkdiv() based configuration of the clock source for the DAC and update the SMDK64xx driver (which is the only in-tree user of the CODEC). Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
This commit is contained in:
Mark Brown
parent
8ef339df25
commit
c5607d8e7a
3 changed files with 90 additions and 34 deletions
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@ -192,6 +192,7 @@ struct wm8580_priv {
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u16 reg_cache[WM8580_MAX_REGISTER + 1];
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struct pll_state a;
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struct pll_state b;
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int sysclk[2];
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};
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static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
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@ -464,6 +465,10 @@ static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
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return 0;
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}
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static const int wm8580_sysclk_ratios[] = {
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128, 192, 256, 384, 512, 768, 1152,
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};
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/*
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* Set PCM DAI bit size and sample rate.
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*/
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@ -473,7 +478,10 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_codec *codec = rtd->codec;
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struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
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u16 paifa = 0;
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u16 paifb = 0;
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int i, ratio;
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/* bit size */
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switch (params_format(params)) {
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@ -492,6 +500,22 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
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return -EINVAL;
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}
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/* Look up the SYSCLK ratio; accept only exact matches */
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ratio = wm8580->sysclk[dai->id] / params_rate(params);
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for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
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if (ratio == wm8580_sysclk_ratios[i])
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break;
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if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
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dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
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wm8580->sysclk[dai->id], params_rate(params));
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return -EINVAL;
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}
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paifa |= i;
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dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n",
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wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
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snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
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WM8580_AIF_RATE_MASK, paifa);
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snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
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WM8580_AIF_LENGTH_MASK, paifb);
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return 0;
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@ -501,9 +525,11 @@ static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
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unsigned int fmt)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
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unsigned int aifa;
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unsigned int aifb;
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int can_invert_lrclk;
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int sysclk;
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aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
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aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
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@ -572,6 +598,8 @@ static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
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return -EINVAL;
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}
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sysclk = wm8580->sysclk[codec_dai->driver->id];
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snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
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snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
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@ -611,28 +639,6 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
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snd_soc_write(codec, WM8580_PLLB4, reg);
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break;
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case WM8580_DAC_CLKSEL:
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reg = snd_soc_read(codec, WM8580_CLKSEL);
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reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
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switch (div) {
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case WM8580_CLKSRC_MCLK:
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break;
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case WM8580_CLKSRC_PLLA:
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reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
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break;
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case WM8580_CLKSRC_PLLB:
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reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
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break;
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default:
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return -EINVAL;
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}
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snd_soc_write(codec, WM8580_CLKSEL, reg);
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break;
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case WM8580_CLKOUTSRC:
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reg = snd_soc_read(codec, WM8580_PLLB4);
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reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
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@ -666,6 +672,55 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
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return 0;
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}
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static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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unsigned int freq, int dir)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
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int sel, sel_mask, sel_shift;
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switch (dai->driver->id) {
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case WM8580_DAI_PAIFTX:
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sel_mask = 0x3;
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sel_shift = 0;
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break;
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case WM8580_DAI_PAIFRX:
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sel_mask = 0xc;
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sel_shift = 2;
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break;
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default:
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BUG_ON("Unknown DAI driver ID\n");
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return -EINVAL;
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}
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switch (clk_id) {
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case WM8580_CLKSRC_ADCMCLK:
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if (dai->id != WM8580_DAI_PAIFTX)
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return -EINVAL;
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sel = 0 << sel_shift;
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break;
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case WM8580_CLKSRC_PLLA:
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sel = 1 << sel_shift;
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break;
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case WM8580_CLKSRC_PLLB:
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sel = 2 << sel_shift;
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break;
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case WM8580_CLKSRC_MCLK:
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sel = 3 << sel_shift;
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break;
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default:
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dev_err(codec->dev, "Unknown clock %d\n", clk_id);
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return -EINVAL;
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}
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/* We really should validate PLL settings but not yet */
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wm8580->sysclk[dai->id] = freq;
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return snd_soc_update_bits(codec, WM8580_CLKSEL, sel, sel_mask);
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}
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static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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@ -719,6 +774,7 @@ static int wm8580_set_bias_level(struct snd_soc_codec *codec,
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SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
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static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
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.set_sysclk = wm8580_set_sysclk,
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.hw_params = wm8580_paif_hw_params,
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.set_fmt = wm8580_set_paif_dai_fmt,
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.set_clkdiv = wm8580_set_dai_clkdiv,
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@ -727,6 +783,7 @@ static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
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};
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static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
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.set_sysclk = wm8580_set_sysclk,
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.hw_params = wm8580_paif_hw_params,
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.set_fmt = wm8580_set_paif_dai_fmt,
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.set_clkdiv = wm8580_set_dai_clkdiv,
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@ -19,14 +19,14 @@
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#define WM8580_PLLB 2
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#define WM8580_MCLK 1
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#define WM8580_DAC_CLKSEL 2
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#define WM8580_CLKOUTSRC 3
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#define WM8580_CLKOUTSRC 2
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#define WM8580_CLKSRC_MCLK 1
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#define WM8580_CLKSRC_PLLA 2
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#define WM8580_CLKSRC_PLLB 3
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#define WM8580_CLKSRC_OSC 4
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#define WM8580_CLKSRC_NONE 5
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#define WM8580_CLKSRC_ADCMCLK 6
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#define WM8580_DAI_PAIFRX 0
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#define WM8580_DAI_PAIFTX 1
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@ -113,14 +113,13 @@ static int smdk64xx_hw_params(struct snd_pcm_substream *substream,
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if (ret < 0)
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return ret;
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/* Explicitly set WM8580-DAC to source from MCLK */
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ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_DAC_CLKSEL,
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WM8580_CLKSRC_MCLK);
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ret = snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 0,
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SMDK64XX_WM8580_FREQ, pll_out);
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if (ret < 0)
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return ret;
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ret = snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 0,
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SMDK64XX_WM8580_FREQ, pll_out);
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ret = snd_soc_dai_set_sysclk(codec_dai, WM8580_CLKSRC_PLLA,
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pll_out, SND_SOC_CLOCK_IN);
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if (ret < 0)
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return ret;
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