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Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable

Browse source
This commit is contained in:
Russell King 2011-05-20 10:38:27 +01:00
parent 1e87347c2f 27ad4bf72a
commit c721be2807
126 changed files with 1344 additions and 3356 deletions
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3
arch/arm/Makefile
View file

@ -158,9 +158,8 @@ machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
machine-$(CONFIG_ARCH_MX1) := imx
machine-$(CONFIG_ARCH_MX2) := imx
machine-$(CONFIG_ARCH_MX25) := imx
machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_MX3) := imx
machine-$(CONFIG_ARCH_MX5) := mx5
machine-$(CONFIG_ARCH_MXC91231) := mxc91231
machine-$(CONFIG_ARCH_MXS) := mxs
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NOMADIK) := nomadik

1
arch/arm/configs/mx1_defconfig
View file

@ -15,6 +15,7 @@ CONFIG_ARCH_MXC=y
CONFIG_ARCH_MX1=y
CONFIG_ARCH_MX1ADS=y
CONFIG_MACH_SCB9328=y
CONFIG_MACH_APF9328=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y

2
arch/arm/configs/mx51_defconfig
View file

@ -13,7 +13,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MXC=y
CONFIG_ARCH_MX5=y
CONFIG_ARCH_MX51=y
CONFIG_MACH_MX51_BABBAGE=y
CONFIG_MACH_MX51_3DS=y
CONFIG_MACH_EUKREA_CPUIMX51=y

286
arch/arm/mach-imx/Kconfig
View file

@ -1,5 +1,15 @@
config IMX_HAVE_DMA_V1
bool
#
# ARCH_MX31 and ARCH_MX35 are left for compatibility
# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
# more sensible) names are used: SOC_IMX31 and SOC_IMX35
config ARCH_MX31
bool
config ARCH_MX35
bool
config SOC_IMX1
bool
@ -31,6 +41,24 @@ config SOC_IMX27
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
config SOC_IMX31
bool
select CPU_V6
select IMX_HAVE_PLATFORM_MXC_RNGA
select ARCH_MXC_AUDMUX_V2
select ARCH_MX31
select MXC_AVIC
config SOC_IMX35
bool
select CPU_V6
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select HAVE_EPIT
select ARCH_MX35
select MXC_AVIC
if ARCH_MX1
comment "MX1 platforms:"
@ -40,6 +68,7 @@ config MACH_MXLADS
config ARCH_MX1ADS
bool "MX1ADS platform"
select MACH_MXLADS
select SOC_IMX1
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
help
@ -51,6 +80,13 @@ config MACH_SCB9328
help
Say Y here if you are using a Synertronixx scb9328 board
config MACH_APF9328
bool "APF9328"
select SOC_IMX1
select IMX_HAVE_PLATFORM_IMX_UART
help
Say Yes here if you are using the Armadeus APF9328 development board
endif
if ARCH_MX2
@ -129,6 +165,7 @@ choice
config MACH_EUKREA_MBIMXSD25_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_SSI
help
This adds board specific devices that can be found on Eukrea's
@ -254,6 +291,7 @@ config MACH_MX27_3DS
config MACH_IMX27_VISSTRIM_M10
bool "Vista Silicon i.MX27 Visstrim_m10"
select SOC_IMX27
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
@ -314,3 +352,251 @@ config MACH_IMX27IPCAM
configurations for the board and its peripherals.
endif
if ARCH_MX3
comment "MX31 platforms:"
config MACH_MX31ADS
bool "Support MX31ADS platforms"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
default y
help
Include support for MX31ADS platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31ADS_WM1133_EV1
bool "Support Wolfson Microelectronics 1133-EV1 module"
depends on MACH_MX31ADS
depends on MFD_WM8350_I2C
depends on REGULATOR_WM8350
select MFD_WM8350_CONFIG_MODE_0
select MFD_WM8352_CONFIG_MODE_0
help
Include support for the Wolfson Microelectronics 1133-EV1 PMU
and audio module for the MX31ADS platform.
config MACH_MX31LILLY
bool "Support MX31 LILLY-1131 platforms (INCO startec)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for mx31 based LILLY1131 modules. This includes
specific configurations for the board and its peripherals.
config MACH_MX31LITE
bool "Support MX31 LITEKIT (LogicPD)"
select SOC_IMX31
select MXC_ULPI if USB_ULPI
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_RTC
select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for MX31 LITEKIT platform. This includes specific
configurations for the board and its peripherals.
config MACH_PCM037
bool "Support Phytec pcm037 (i.MX31) platforms"
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm037 platform. This includes
specific configurations for the board and its peripherals.
config MACH_PCM037_EET
bool "Support pcm037 EET board extensions"
depends on MACH_PCM037
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_SPI_IMX
help
Add support for PCM037 EET baseboard extensions. If you are using the
OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
command-line parameter.
config MACH_MX31_3DS
bool "Support MX31PDK (3DS)"
select SOC_IMX31
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for MX31PDK (3DS) platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31_3DS_MXC_NAND_USE_BBT
bool "Make the MXC NAND driver use the in flash Bad Block Table"
depends on MACH_MX31_3DS
depends on MTD_NAND_MXC
help
Enable this if you want that the MXC NAND driver uses the in flash
Bad Block Table to know what blocks are bad instead of scanning the
entire flash looking for bad block markers.
config MACH_MX31MOBOARD
bool "Support mx31moboard platforms (EPFL Mobots group)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for mx31moboard platform. This includes specific
configurations for the board and its peripherals.
config MACH_QONG
bool "Support Dave/DENX QongEVB-LITE platform"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for Dave/DENX QongEVB-LITE platform. This includes
specific configurations for the board and its peripherals.
config MACH_ARMADILLO5X0
bool "Support Atmark Armadillo-500 Development Base Board"
select SOC_IMX31
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select MXC_ULPI if USB_ULPI
help
Include support for Atmark Armadillo-500 platform. This includes
specific configurations for the board and its peripherals.
config MACH_KZM_ARM11_01
bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for KZM-ARM11-01. This includes specific
configurations for the board and its peripherals.
config MACH_BUG
bool "Support Buglabs BUGBase platform"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
default y
help
Include support for BUGBase 1.3 platform. This includes specific
configurations for the board and its peripherals.
comment "MX35 platforms:"
config MACH_PCM043
bool "Support Phytec pcm043 (i.MX35) platforms"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm043 platform. This includes
specific configurations for the board and its peripherals.
config MACH_MX35_3DS
bool "Support MX35PDK platform"
select SOC_IMX35
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX35PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_EUKREA_CPUIMX35
bool "Support Eukrea CPUIMX35 Platform"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX35 platform. This includes
specific configurations for the board and its peripherals.
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX35
default MACH_EUKREA_MBIMXSD35_BASEBOARD
config MACH_EUKREA_MBIMXSD35_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IPU_CORE
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
config MACH_VPR200
bool "Support VPR200 platform"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for VPR200 platform. This includes specific
configurations for the board and its peripherals.
endif

40
arch/arm/mach-imx/Makefile
View file

@ -1,9 +1,3 @@
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
@ -14,18 +8,27 @@ obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
# Support for CMOS sensor interface
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
# Support for CMOS sensor interface
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
# i.MX1 based machines
obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
# i.MX21 based machines
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
# i.MX25 based machines
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
# i.MX27 based machines
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
@ -37,3 +40,24 @@ obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
# i.MX31 based machines
obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
mx31moboard-marxbot.o mx31moboard-smartbot.o
obj-$(CONFIG_MACH_QONG) += mach-qong.o
obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
obj-$(CONFIG_MACH_BUG) += mach-bug.o
# i.MX35 based machines
obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o

4
arch/arm/mach-imx/Makefile.boot
View file

@ -13,3 +13,7 @@ initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000
zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
zreladdr-$(CONFIG_ARCH_MX3) := 0x80008000
params_phys-$(CONFIG_ARCH_MX3) := 0x80000100
initrd_phys-$(CONFIG_ARCH_MX3) := 0x80800000

56
arch/arm/mach-imx/cache-l2x0.c Normal file
View file

@ -0,0 +1,56 @@
/*
* Copyright (C) 2009-2010 Pengutronix
* Sascha Hauer <s.hauer@pengutronix.de>
* Juergen Beisert <j.beisert@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/hardware.h>
static int mxc_init_l2x0(void)
{
void __iomem *l2x0_base;
void __iomem *clkctl_base;
if (!cpu_is_mx31() && !cpu_is_mx35())
return 0;
/*
* First of all, we must repair broken chip settings. There are some
* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
* Workaraound is to setup the correct register setting prior enabling the
* L2 cache. This should not hurt already working CPUs, as they are using the
* same value.
*/
#define L2_MEM_VAL 0x10
clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
if (clkctl_base != NULL) {
writel(0x00000515, clkctl_base + L2_MEM_VAL);
iounmap(clkctl_base);
} else {
pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
}
l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
if (IS_ERR(l2x0_base)) {
printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
PTR_ERR(l2x0_base));
return 0;
}
l2x0_init(l2x0_base, 0x00030024, 0x00000000);
return 0;
}
arch_initcall(mxc_init_l2x0);

3
arch/arm/mach-mx3/clock-imx31.c → arch/arm/mach-imx/clock-imx31.c
View file

@ -32,7 +32,7 @@
#include <mach/mx31.h>
#include <mach/common.h>
#include "crm_regs.h"
#include "crmregs-imx31.h"
#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
@ -627,4 +627,3 @@ int __init mx31_clocks_init(unsigned long fref)
return 0;
}

1
arch/arm/mach-mx3/clock-imx35.c → arch/arm/mach-imx/clock-imx35.c
View file

@ -547,4 +547,3 @@ int __init mx35_clocks_init()
return 0;
}

38
arch/arm/mach-mx3/cpu.c → arch/arm/mach-imx/cpu-imx31.c
View file

@ -1,5 +1,5 @@
/*
* MX3 CPU type detection
* MX31 CPU type detection
*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*
@ -17,14 +17,12 @@
unsigned int mx31_cpu_rev;
EXPORT_SYMBOL(mx31_cpu_rev);
struct mx3_cpu_type {
static struct {
u8 srev;
const char *name;
const char *v;
unsigned int rev;
};
static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
} mx31_cpu_type[] __initdata = {
{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
{ .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
@ -57,33 +55,3 @@ void __init mx31_read_cpu_rev(void)
printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
}
unsigned int mx35_cpu_rev;
EXPORT_SYMBOL(mx35_cpu_rev);
void __init mx35_read_cpu_rev(void)
{
u32 rev;
char *srev;
rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
switch (rev) {
case 0x00:
mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
srev = "1.0";
break;
case 0x10:
mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
srev = "2.0";
break;
case 0x11:
mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
srev = "2.1";
break;
default:
mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
srev = "unknown";
}
printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
}

44
arch/arm/mach-imx/cpu-imx35.c Normal file
View file

@ -0,0 +1,44 @@
/*
* MX35 CPU type detection
*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/iim.h>
unsigned int mx35_cpu_rev;
EXPORT_SYMBOL(mx35_cpu_rev);
void __init mx35_read_cpu_rev(void)
{
u32 rev;
char *srev;
rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
switch (rev) {
case 0x00:
mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
srev = "1.0";
break;
case 0x10:
mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
srev = "2.0";
break;
case 0x11:
mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
srev = "2.1";
break;
default:
mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
srev = "unknown";
}
printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
}

0
arch/arm/mach-mx3/crm_regs.h → arch/arm/mach-imx/crmregs-imx31.h
View file

8
arch/arm/mach-imx/devices-imx1.h
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@ -9,21 +9,21 @@
#include <mach/mx1.h>
#include <mach/devices-common.h>
extern const struct imx_imx_fb_data imx1_imx_fb_data __initconst;
extern const struct imx_imx_fb_data imx1_imx_fb_data;
#define imx1_add_imx_fb(pdata) \
imx_add_imx_fb(&imx1_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
extern const struct imx_imx_i2c_data imx1_imx_i2c_data;
#define imx1_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[];
#define imx1_add_imx_uart(id, pdata) \
imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)
extern const struct imx_spi_imx_data imx1_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx1_cspi_data[];
#define imx1_add_cspi(id, pdata) \
imx_add_spi_imx(&imx1_cspi_data[id], pdata)

22
arch/arm/mach-imx/devices-imx21.h
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@ -9,31 +9,31 @@
#include <mach/mx21.h>
#include <mach/devices-common.h>
extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst;
extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data;
#define imx21_add_imx21_hcd(pdata) \
imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst;
extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data;
#define imx21_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx21_imx2_wdt_data)
extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst;
extern const struct imx_imx_fb_data imx21_imx_fb_data;
#define imx21_add_imx_fb(pdata) \
imx_add_imx_fb(&imx21_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
extern const struct imx_imx_i2c_data imx21_imx_i2c_data;
#define imx21_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst;
extern const struct imx_imx_keypad_data imx21_imx_keypad_data;
#define imx21_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
extern const struct imx_imx_ssi_data imx21_imx_ssi_data[];
#define imx21_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[];
#define imx21_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata)
@ -41,19 +41,19 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst;
extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[];
#define imx21_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
extern const struct imx_mxc_nand_data imx21_mxc_nand_data;
#define imx21_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst;
extern const struct imx_mxc_w1_data imx21_mxc_w1_data;
#define imx21_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx21_mxc_w1_data)
extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx21_cspi_data[];
#define imx21_add_cspi(id, pdata) \
imx_add_spi_imx(&imx21_cspi_data[id], pdata)
#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata)

35
arch/arm/mach-imx/devices-imx25.h
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@ -9,48 +9,48 @@
#include <mach/mx25.h>
#include <mach/devices-common.h>
extern const struct imx_fec_data imx25_fec_data __initconst;
extern const struct imx_fec_data imx25_fec_data;
#define imx25_add_fec(pdata) \
imx_add_fec(&imx25_fec_data, pdata)
extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst;
extern const struct imx_flexcan_data imx25_flexcan_data[];
#define imx25_add_flexcan(id, pdata) \
imx_add_flexcan(&imx25_flexcan_data[id], pdata)
#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata)
#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata)
extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst;
extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
#define imx25_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst;
extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
#define imx25_add_imxdi_rtc(pdata) \
imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst;
extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
#define imx25_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx25_imx2_wdt_data)
extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst;
extern const struct imx_imx_fb_data imx25_imx_fb_data;
#define imx25_add_imx_fb(pdata) \
imx_add_imx_fb(&imx25_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
extern const struct imx_imx_i2c_data imx25_imx_i2c_data[];
#define imx25_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata)
#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst;
extern const struct imx_imx_keypad_data imx25_imx_keypad_data;
#define imx25_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
extern const struct imx_imx_ssi_data imx25_imx_ssi_data[];
#define imx25_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[];
#define imx25_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata)
@ -59,33 +59,32 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst;
extern const struct imx_mx2_camera_data imx25_mx2_camera_data;
#define imx25_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst;
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data;
#define imx25_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst;
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data;
#define imx25_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
extern const struct imx_mxc_nand_data imx25_mxc_nand_data;
#define imx25_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
extern const struct imx_sdhci_esdhc_imx_data
imx25_sdhci_esdhc_imx_data[] __initconst;
extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[];
#define imx25_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx25_cspi_data[];
#define imx25_add_spi_imx(id, pdata) \
imx_add_spi_imx(&imx25_cspi_data[id], pdata)
#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst;
extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[];
#define imx25_add_mxc_pwm(id) \
imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])

30
arch/arm/mach-imx/devices-imx27.h
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@ -9,35 +9,35 @@
#include <mach/mx27.h>
#include <mach/devices-common.h>
extern const struct imx_fec_data imx27_fec_data __initconst;
extern const struct imx_fec_data imx27_fec_data;
#define imx27_add_fec(pdata) \
imx_add_fec(&imx27_fec_data, pdata)
extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst;
extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
#define imx27_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst;
extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
#define imx27_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx27_imx2_wdt_data)
extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst;
extern const struct imx_imx_fb_data imx27_imx_fb_data;
#define imx27_add_imx_fb(pdata) \
imx_add_imx_fb(&imx27_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
extern const struct imx_imx_i2c_data imx27_imx_i2c_data[];
#define imx27_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst;
extern const struct imx_imx_keypad_data imx27_imx_keypad_data;
#define imx27_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
extern const struct imx_imx_ssi_data imx27_imx_ssi_data[];
#define imx27_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
#define imx27_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata)
@ -47,30 +47,30 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst;
extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
#define imx27_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst;
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
#define imx27_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst;
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[];
#define imx27_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst;
extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[];
#define imx27_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
extern const struct imx_mxc_nand_data imx27_mxc_nand_data;
#define imx27_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst;
extern const struct imx_mxc_w1_data imx27_mxc_w1_data;
#define imx27_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx27_mxc_w1_data)
extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx27_cspi_data[];
#define imx27_add_cspi(id, pdata) \
imx_add_spi_imx(&imx27_cspi_data[id], pdata)
#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata)

36
arch/arm/mach-mx3/devices-imx31.h → arch/arm/mach-imx/devices-imx31.h
View file

@ -9,30 +9,30 @@
#include <mach/mx31.h>
#include <mach/devices-common.h>
extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst;
extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data;
#define imx31_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst;
extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data;
#define imx31_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx31_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
extern const struct imx_imx_i2c_data imx31_imx_i2c_data[];
#define imx31_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata)
#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst;
extern const struct imx_imx_keypad_data imx31_imx_keypad_data;
#define imx31_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
extern const struct imx_imx_ssi_data imx31_imx_ssi_data[];
#define imx31_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
#define imx31_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata)
@ -41,26 +41,38 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst;
extern const struct imx_ipu_core_data imx31_ipu_core_data;
#define imx31_add_ipu_core(pdata) \
imx_add_ipu_core(&imx31_ipu_core_data, pdata)
#define imx31_alloc_mx3_camera(pdata) \
imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
#define imx31_add_mx3_sdc_fb(pdata) \
imx_add_mx3_sdc_fb(&imx31_ipu_core_data, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data;
#define imx31_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst;
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[];
#define imx31_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst;
extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[];
#define imx31_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
extern const struct imx_mxc_nand_data imx31_mxc_nand_data;
#define imx31_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst;
extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data;
#define imx31_add_mxc_rtc(pdata) \
imx_add_mxc_rtc(&imx31_mxc_rtc_data)
extern const struct imx_mxc_w1_data imx31_mxc_w1_data;
#define imx31_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx31_mxc_w1_data)
extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx31_cspi_data[];
#define imx31_add_cspi(id, pdata) \
imx_add_spi_imx(&imx31_cspi_data[id], pdata)
#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata)

37
arch/arm/mach-mx3/devices-imx35.h → arch/arm/mach-imx/devices-imx35.h
View file

@ -9,67 +9,74 @@
#include <mach/mx35.h>
#include <mach/devices-common.h>
extern const struct imx_fec_data imx35_fec_data __initconst;
extern const struct imx_fec_data imx35_fec_data;
#define imx35_add_fec(pdata) \
imx_add_fec(&imx35_fec_data, pdata)
extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst;
extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data;
#define imx35_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst;
extern const struct imx_flexcan_data imx35_flexcan_data[];
#define imx35_add_flexcan(id, pdata) \
imx_add_flexcan(&imx35_flexcan_data[id], pdata)
#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata)
#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata)
extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst;
extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data;
#define imx35_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx35_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
extern const struct imx_imx_i2c_data imx35_imx_i2c_data[];
#define imx35_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata)
#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
extern const struct imx_imx_keypad_data imx35_imx_keypad_data;
#define imx35_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
extern const struct imx_imx_ssi_data imx35_imx_ssi_data[];
#define imx35_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
#define imx35_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata)
#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst;
extern const struct imx_ipu_core_data imx35_ipu_core_data;
#define imx35_add_ipu_core(pdata) \
imx_add_ipu_core(&imx35_ipu_core_data, pdata)
#define imx35_alloc_mx3_camera(pdata) \
imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
#define imx35_add_mx3_sdc_fb(pdata) \
imx_add_mx3_sdc_fb(&imx35_ipu_core_data, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data;
#define imx35_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst;
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data;
#define imx35_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
extern const struct imx_mxc_nand_data imx35_mxc_nand_data;
#define imx35_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst;
extern const struct imx_mxc_w1_data imx35_mxc_w1_data;
#define imx35_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx35_mxc_w1_data)
extern const struct imx_sdhci_esdhc_imx_data
imx35_sdhci_esdhc_imx_data[] __initconst;
extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[];
#define imx35_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx35_cspi_data[];
#define imx35_add_cspi(id, pdata) \
imx_add_spi_imx(&imx35_cspi_data[id], pdata)
#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)

1
arch/arm/mach-mx3/ehci-imx31.c → arch/arm/mach-imx/ehci-imx31.c
View file

@ -80,4 +80,3 @@ int mx31_initialize_usb_hw(int port, unsigned int flags)
return 0;
}

1
arch/arm/mach-mx3/ehci-imx35.c → arch/arm/mach-imx/ehci-imx35.c
View file

@ -77,4 +77,3 @@ int mx35_initialize_usb_hw(int port, unsigned int flags)
return 0;
}

1
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
View file

@ -32,7 +32,6 @@
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/hardware.h>
#include <mach/spi.h>
#include <mach/audmux.h>
#include "devices-imx27.h"

17
arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
View file

@ -22,7 +22,6 @@
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <video/platform_lcd.h>
@ -32,9 +31,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/mx25.h>
#include <mach/imx-uart.h>
#include <mach/audmux.h>
#include <mach/esdhc.h>
#include "devices-imx25.h"
@ -208,23 +205,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
},
};
static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
static const struct gpio_keys_platform_data
eukrea_mbimxsd_button_data __initconst = {
.buttons = eukrea_mbimxsd_gpio_buttons,
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
};
static struct platform_device eukrea_mbimxsd_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &eukrea_mbimxsd_button_data,
}
};
static struct platform_device *platform_devices[] __initdata = {
&eukrea_mbimxsd_leds_gpio,
&eukrea_mbimxsd_button_device,
&eukrea_mbimxsd_lcd_powerdev,
};
@ -299,4 +287,5 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
}

29
arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c → arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
View file

@ -26,7 +26,6 @@
#include <linux/interrupt.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <video/platform_lcd.h>
#include <linux/i2c.h>
@ -38,15 +37,10 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx35.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/audmux.h>
#include <mach/esdhc.h>
#include "devices-imx35.h"
#include "devices.h"
static const struct fb_videomode fb_modedb[] = {
{
@ -101,12 +95,11 @@ static const struct fb_videomode fb_modedb[] = {
},
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "CMO-QVGA",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -223,23 +216,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
},
};
static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
static const struct gpio_keys_platform_data
eukrea_mbimxsd_button_data __initconst = {
.buttons = eukrea_mbimxsd_gpio_buttons,
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
};
static struct platform_device eukrea_mbimxsd_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &eukrea_mbimxsd_button_data,
}
};
static struct platform_device *platform_devices[] __initdata = {
&eukrea_mbimxsd_leds_gpio,
&eukrea_mbimxsd_button_device,
&eukrea_mbimxsd_lcd_powerdev,
};
@ -292,8 +276,8 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
#endif
imx35_add_imx_uart1(&uart_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx35_add_ipu_core(&mx3_ipu_data);
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
@ -315,4 +299,5 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
}

0
arch/arm/mach-mx3/iomux-imx31.c → arch/arm/mach-imx/iomux-imx31.c
View file

144
arch/arm/mach-imx/mach-apf9328.c Normal file
View file

@ -0,0 +1,144 @@
/*
* linux/arch/arm/mach-imx/mach-apf9328.c
*
* Copyright (c) 2005-2011 ARMadeus systems <support@armadeus.com>
*
* This work is based on mach-scb9328.c which is:
* Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
* Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/dm9000.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/iomux-mx1.h>
#include "devices-imx1.h"
static const int apf9328_pins[] __initconst = {
/* UART1 */
PC9_PF_UART1_CTS,
PC10_PF_UART1_RTS,
PC11_PF_UART1_TXD,
PC12_PF_UART1_RXD,
/* UART2 */
PB28_PF_UART2_CTS,
PB29_PF_UART2_RTS,
PB30_PF_UART2_TXD,
PB31_PF_UART2_RXD,
};
/*
* The APF9328 can have up to 32MB NOR Flash
*/
static struct resource flash_resource = {
.start = MX1_CS0_PHYS,
.end = MX1_CS0_PHYS + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};
static struct physmap_flash_data apf9328_flash_data = {
.width = 2,
};
static struct platform_device apf9328_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &apf9328_flash_data,
},
.resource = &flash_resource,
.num_resources = 1,
};
/*
* APF9328 has a DM9000 Ethernet controller
*/
static struct dm9000_plat_data dm9000_setup = {
.flags = DM9000_PLATF_16BITONLY
};
static struct resource dm9000_resources[] = {
{
.start = MX1_CS4_PHYS + 0x00C00000,
.end = MX1_CS4_PHYS + 0x00C00001,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_CS4_PHYS + 0x00C00002,
.end = MX1_CS4_PHYS + 0x00C00003,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_GPIOB(14),
.end = IRQ_GPIOB(14),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
static struct platform_device dm9000x_device = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(dm9000_resources),
.resource = dm9000_resources,
.dev = {
.platform_data = &dm9000_setup,
}
};
/* --- SERIAL RESSOURCE --- */
static const struct imxuart_platform_data uart0_pdata __initconst = {
.flags = 0,
};
static const struct imxuart_platform_data uart1_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct platform_device *devices[] __initdata = {
&apf9328_flash_device,
&dm9000x_device,
};
static void __init apf9328_init(void)
{
mxc_gpio_setup_multiple_pins(apf9328_pins,
ARRAY_SIZE(apf9328_pins),
"APF9328");
imx1_add_imx_uart0(&uart0_pdata);
imx1_add_imx_uart1(&uart1_pdata);
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init apf9328_timer_init(void)
{
mx1_clocks_init(32768);
}
static struct sys_timer apf9328_timer = {
.init = apf9328_timer_init,
};
MACHINE_START(APF9328, "Armadeus APF9328")
/* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */
.map_io = mx1_map_io,
.init_early = imx1_init_early,
.init_irq = mx1_init_irq,
.timer = &apf9328_timer,
.init_machine = apf9328_init,
MACHINE_END

29
arch/arm/mach-mx3/mach-armadillo5x0.c → arch/arm/mach-imx/mach-armadillo5x0.c
View file

@ -34,7 +34,6 @@
#include <linux/mtd/physmap.h>
#include <linux/io.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/i2c.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
@ -49,13 +48,10 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
#include "crm_regs.h"
#include "crmregs-imx31.h"
static int armadillo5x0_pins[] = {
/* UART1 */
@ -280,20 +276,12 @@ static struct gpio_keys_button armadillo5x0_buttons[] = {
}
};
static struct gpio_keys_platform_data armadillo5x0_button_data = {
static const struct gpio_keys_platform_data
armadillo5x0_button_data __initconst = {
.buttons = armadillo5x0_buttons,
.nbuttons = ARRAY_SIZE(armadillo5x0_buttons),
};
static struct platform_device armadillo5x0_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &armadillo5x0_button_data,
}
};
/*
* NAND Flash
*/
@ -383,12 +371,11 @@ static const struct fb_videomode fb_modedb[] = {
},
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "CRT-VGA",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -496,7 +483,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
static struct platform_device *devices[] __initdata = {
&armadillo5x0_smc911x_device,
&armadillo5x0_button_device,
};
/*
@ -508,6 +494,7 @@ static void __init armadillo5x0_init(void)
ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
platform_add_devices(devices, ARRAY_SIZE(devices));
imx_add_gpio_keys(&armadillo5x0_button_data);
imx31_add_imx_i2c1(NULL);
/* Register UART */
@ -521,8 +508,8 @@ static void __init armadillo5x0_init(void)
imx31_add_mxc_mmc(0, &sdhc_pdata);
/* Register FB */
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx31_add_ipu_core(&mx3_ipu_data);
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* Register NOR Flash */
mxc_register_device(&armadillo5x0_nor_flash,

1
arch/arm/mach-mx3/mach-bug.c → arch/arm/mach-imx/mach-bug.c
View file

@ -20,7 +20,6 @@
#include <linux/platform_device.h>
#include <mach/iomux-mx3.h>
#include <mach/imx-uart.h>
#include <mach/hardware.h>
#include <mach/common.h>

1
arch/arm/mach-imx/mach-cpuimx27.c
View file

@ -38,7 +38,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"

2
arch/arm/mach-mx3/mach-cpuimx35.c → arch/arm/mach-imx/mach-cpuimx35.c
View file

@ -41,10 +41,8 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/mxc_nand.h>
#include "devices-imx35.h"
#include "devices.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,

2
arch/arm/mach-imx/mach-eukrea_cpuimx25.c
View file

@ -36,8 +36,6 @@
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/mx25.h>
#include <mach/mxc_nand.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx25.h>
#include "devices-imx25.h"

14
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
View file

@ -27,7 +27,6 @@
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/i2c/pca953x.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/delay.h>
@ -130,19 +129,12 @@ static struct gpio_keys_button visstrim_gpio_keys[] = {
}
};
static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = {
static const struct gpio_keys_platform_data
visstrim_gpio_keys_platform_data __initconst = {
.buttons = visstrim_gpio_keys,
.nbuttons = ARRAY_SIZE(visstrim_gpio_keys),
};
static struct platform_device visstrim_gpio_keys_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &visstrim_gpio_keys_platform_data,
},
};
/* Visstrim_SM10 has a microSD slot connected to sdhc1 */
static int visstrim_m10_sdhc1_init(struct device *dev,
irq_handler_t detect_irq, void *data)
@ -186,7 +178,6 @@ static struct platform_device visstrim_m10_nor_mtd_device = {
};
static struct platform_device *platform_devices[] __initdata = {
&visstrim_gpio_keys_device,
&visstrim_m10_nor_mtd_device,
};
@ -255,6 +246,7 @@ static void __init visstrim_m10_board_init(void)
imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
imx27_add_fec(NULL);
imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}

1
arch/arm/mach-mx3/mach-kzm_arm11_01.c → arch/arm/mach-imx/mach-kzm_arm11_01.c
View file

@ -39,7 +39,6 @@
#include <mach/iomux-mx3.h>
#include "devices-imx31.h"
#include "devices.h"
#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \

1
arch/arm/mach-imx/mach-mx1ads.c
View file

@ -25,7 +25,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/i2c.h>
#include <mach/iomux-mx1.h>
#include <mach/irqs.h>

1
arch/arm/mach-imx/mach-mx21ads.c
View file

@ -25,7 +25,6 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/iomux-mx21.h>
#include <mach/mxc_nand.h>
#include "devices-imx21.h"

13
arch/arm/mach-imx/mach-mx25_3ds.c
View file

@ -29,7 +29,6 @@
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/input/matrix_keypad.h>
#include <linux/usb/otg.h>
#include <mach/hardware.h>
@ -103,6 +102,8 @@ static iomux_v3_cfg_t mx25pdk_pads[] = {
MX25_PAD_SD1_DATA1__SD1_DATA1,
MX25_PAD_SD1_DATA2__SD1_DATA2,
MX25_PAD_SD1_DATA3__SD1_DATA3,
MX25_PAD_A14__GPIO_2_0, /* WriteProtect */
MX25_PAD_A15__GPIO_2_1, /* CardDetect */
/* I2C1 */
MX25_PAD_I2C1_CLK__I2C1_CLK,
@ -208,6 +209,14 @@ static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
.bitrate = 100000,
};
#define SD1_GPIO_WP IMX_GPIO_NR(2, 0)
#define SD1_GPIO_CD IMX_GPIO_NR(2, 1)
static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
.wp_gpio = SD1_GPIO_WP,
.cd_gpio = SD1_GPIO_CD,
};
static void __init mx25pdk_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
@ -225,7 +234,7 @@ static void __init mx25pdk_init(void)
imx25_add_fec(&mx25_fec_pdata);
imx25_add_imx_keypad(&mx25pdk_keymap_data);
imx25_add_sdhci_esdhc_imx(0, NULL);
imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
}

1
arch/arm/mach-imx/mach-mx27ads.c
View file

@ -29,7 +29,6 @@
#include <asm/mach/map.h>
#include <mach/gpio.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include "devices-imx27.h"

50
arch/arm/mach-mx3/mach-mx31_3ds.c → arch/arm/mach-imx/mach-mx31_3ds.c
View file

@ -39,13 +39,8 @@
#include <mach/iomux-mx3.h>
#include <mach/3ds_debugboard.h>
#include <mach/ulpi.h>
#include <mach/mmc.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/mx3_camera.h>
#include "devices-imx31.h"
#include "devices.h"
/* CPLD IRQ line for external uart, external ethernet etc */
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
@ -178,22 +173,37 @@ static struct gpio mx31_3ds_camera_gpios[] = {
{ MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
};
static int __init mx31_3ds_camera_alloc_dma(void)
static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
.flags = MX3_CAMERA_DATAWIDTH_10,
.mclk_10khz = 2600,
};
static int __init mx31_3ds_init_camera(void)
{
int dma;
int dma, ret = -ENOMEM;
struct platform_device *pdev =
imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
if (!mx3_camera_base)
return -ENOMEM;
goto err;
dma = dma_declare_coherent_memory(&mx3_camera.dev,
dma = dma_declare_coherent_memory(&pdev->dev,
mx3_camera_base, mx3_camera_base,
MX31_3DS_CAMERA_BUF_SIZE,
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
if (!(dma & DMA_MEMORY_MAP))
return -ENOMEM;
goto err;
return 0;
ret = platform_device_add(pdev);
if (ret)
err:
platform_device_put(pdev);
return ret;
}
static int mx31_3ds_camera_power(struct device *dev, int on)
@ -241,12 +251,6 @@ static struct platform_device mx31_3ds_ov2640 = {
},
};
struct mx3_camera_pdata mx31_3ds_camera_pdata = {
.dma_dev = &mx3_ipu.dev,
.flags = MX3_CAMERA_DATAWIDTH_10,
.mclk_10khz = 2600,
};
/*
* FB support
*/
@ -273,8 +277,7 @@ static struct ipu_platform_data mx3_ipu_data = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "Epson-VGA",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -723,8 +726,8 @@ static void __init mx31_3ds_init(void)
imx31_add_mxc_mmc(0, &sdhc1_pdata);
imx31_add_spi_imx0(&spi0_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx31_add_ipu_core(&mx3_ipu_data);
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* CSI */
/* Camera power: default - off */
@ -735,10 +738,7 @@ static void __init mx31_3ds_init(void)
iclink_ov2640.power = NULL;
}
if (!mx31_3ds_camera_alloc_dma())
mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata);
else
pr_err("Failed to allocate dma memory for camera");
mx31_3ds_init_camera();
}
static void __init mx31_3ds_timer_init(void)

1
arch/arm/mach-mx3/mach-mx31ads.c → arch/arm/mach-imx/mach-mx31ads.c
View file

@ -38,7 +38,6 @@
#endif
#include "devices-imx31.h"
#include "devices.h"
/* PBC Board interrupt status register */
#define PBC_INTSTATUS 0x000016

1
arch/arm/mach-mx3/mach-mx31lilly.c → arch/arm/mach-imx/mach-mx31lilly.c
View file

@ -46,7 +46,6 @@
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
/*
* This file contains module-specific initialization routines for LILLY-1131.

1
arch/arm/mach-mx3/mach-mx31lite.c → arch/arm/mach-imx/mach-mx31lite.c
View file

@ -44,7 +44,6 @@
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
/*
* This file contains the module-specific initialization routines.

75
arch/arm/mach-mx3/mach-mx31moboard.c → arch/arm/mach-imx/mach-mx31moboard.c
View file

@ -27,6 +27,7 @@
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/types.h>
#include <linux/memblock.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
@ -39,13 +40,9 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/mx3_camera.h>
#include <mach/spi.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
static unsigned int moboard_pins[] = {
/* UART0 */
@ -102,7 +99,7 @@ static unsigned int moboard_pins[] = {
};
static struct physmap_flash_data mx31moboard_flash_data = {
.width = 2,
.width = 2,
};
static struct resource mx31moboard_flash_resource = {
@ -194,8 +191,8 @@ static struct regulator_init_data sdhc_vreg_data = {
static struct regulator_consumer_supply cam_consumers[] = {
{
.dev = &mx3_camera.dev,
.supply = "cam_vcc",
.dev_name = "mx3_camera.0",
.supply = "cam_vcc",
},
};
@ -430,9 +427,9 @@ static int __init moboard_usbh2_init(void)
static struct gpio_led mx31moboard_leds[] = {
{
.name = "coreboard-led-0:red:running",
.name = "coreboard-led-0:red:running",
.default_trigger = "heartbeat",
.gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
.gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
}, {
.name = "coreboard-led-1:red",
.gpio = IOMUX_TO_GPIO(MX31_PIN_STX0),
@ -446,7 +443,7 @@ static struct gpio_led mx31moboard_leds[] = {
};
static struct gpio_led_platform_data mx31moboard_led_pdata = {
.num_leds = ARRAY_SIZE(mx31moboard_leds),
.num_leds = ARRAY_SIZE(mx31moboard_leds),
.leds = mx31moboard_leds,
};
@ -458,7 +455,7 @@ static struct platform_device mx31moboard_leds_device = {
},
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
@ -467,37 +464,39 @@ static struct platform_device *devices[] __initdata = {
&mx31moboard_leds_device,
};
static struct mx3_camera_pdata camera_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3_camera_pdata camera_pdata __initdata = {
.flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
.mclk_10khz = 4800,
};
#define CAMERA_BUF_SIZE (4*1024*1024)
static phys_addr_t mx3_camera_base __initdata;
#define MX3_CAMERA_BUF_SIZE SZ_4M
static int __init mx31moboard_cam_alloc_dma(const size_t buf_size)
static int __init mx31moboard_init_cam(void)
{
dma_addr_t dma_handle;
void *buf;
int dma;
int dma, ret = -ENOMEM;
struct platform_device *pdev;
if (buf_size < 2 * 1024 * 1024)
return -EINVAL;
imx31_add_ipu_core(&mx3_ipu_data);
buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
if (!buf) {
pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
return -ENOMEM;
}
pdev = imx31_alloc_mx3_camera(&camera_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
memset(buf, 0, buf_size);
dma = dma_declare_coherent_memory(&mx3_camera.dev,
dma_handle, dma_handle, buf_size,
dma = dma_declare_coherent_memory(&pdev->dev,
mx3_camera_base, mx3_camera_base,
MX3_CAMERA_BUF_SIZE,
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
if (!(dma & DMA_MEMORY_MAP))
goto err;
ret = platform_device_add(pdev);
if (ret)
err:
platform_device_put(pdev);
return ret;
/* The way we call dma_declare_coherent_memory only a malloc can fail */
return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
}
static int mx31moboard_baseboard;
@ -529,9 +528,7 @@ static void __init mx31moboard_init(void)
imx31_add_mxc_mmc(0, &sdhc1_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
mxc_register_device(&mx3_camera, &camera_pdata);
mx31moboard_init_cam();
usb_xcvr_reset();
@ -565,9 +562,19 @@ struct sys_timer mx31moboard_timer = {
.init = mx31moboard_timer_init,
};
static void __init mx31moboard_reserve(void)
{
/* reserve 4 MiB for mx3-camera */
mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
MX3_CAMERA_BUF_SIZE);
memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
}
MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
/* Maintainer: Valentin Longchamp, EPFL Mobots group */
.boot_params = MX3x_PHYS_OFFSET + 0x100,
.reserve = mx31moboard_reserve,
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,

1
arch/arm/mach-mx3/mach-mx35_3ds.c → arch/arm/mach-imx/mach-mx35_3ds.c
View file

@ -42,7 +42,6 @@
#include <mach/3ds_debugboard.h>
#include "devices-imx35.h"
#include "devices.h"
#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)

1
arch/arm/mach-imx/mach-mxt_td60.c
View file

@ -29,7 +29,6 @@
#include <asm/mach/map.h>
#include <linux/gpio.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <linux/i2c/pca953x.h>
#include "devices-imx27.h"

1
arch/arm/mach-imx/mach-pca100.c
View file

@ -37,7 +37,6 @@
#include <mach/iomux-mx27.h>
#include <asm/mach/time.h>
#include <mach/audmux.h>
#include <mach/mxc_nand.h>
#include <mach/irqs.h>
#include <mach/ulpi.h>

65
arch/arm/mach-mx3/mach-pcm037.c → arch/arm/mach-imx/mach-pcm037.c
View file

@ -31,6 +31,7 @@
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/gfp.h>
#include <linux/memblock.h>
#include <media/soc_camera.h>
@ -41,13 +42,9 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/mx3_camera.h>
#include <mach/mx3fb.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
#include "pcm037.h"
static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
@ -404,35 +401,35 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.exit = pcm970_sdhc1_exit,
};
struct mx3_camera_pdata camera_pdata = {
.dma_dev = &mx3_ipu.dev,
struct mx3_camera_pdata camera_pdata __initdata = {
.flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
.mclk_10khz = 2000,
};
static int __init pcm037_camera_alloc_dma(const size_t buf_size)
static phys_addr_t mx3_camera_base __initdata;
#define MX3_CAMERA_BUF_SIZE SZ_4M
static int __init pcm037_init_camera(void)
{
dma_addr_t dma_handle;
void *buf;
int dma;
int dma, ret = -ENOMEM;
struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata);
if (buf_size < 2 * 1024 * 1024)
return -EINVAL;
if (IS_ERR(pdev))
return PTR_ERR(pdev);
buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
if (!buf) {
pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
return -ENOMEM;
}
memset(buf, 0, buf_size);
dma = dma_declare_coherent_memory(&mx3_camera.dev,
dma_handle, dma_handle, buf_size,
dma = dma_declare_coherent_memory(&pdev->dev,
mx3_camera_base, mx3_camera_base,
MX3_CAMERA_BUF_SIZE,
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
if (!(dma & DMA_MEMORY_MAP))
goto err;
/* The way we call dma_declare_coherent_memory only a malloc can fail */
return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
ret = platform_device_add(pdev);
if (ret)
err:
platform_device_put(pdev);
return ret;
}
static struct platform_device *devices[] __initdata = {
@ -442,7 +439,7 @@ static struct platform_device *devices[] __initdata = {
&pcm037_mt9v022,
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
@ -500,7 +497,6 @@ static const struct fb_videomode fb_modedb[] = {
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
.name = "Sharp-LQ035Q7DH06-QVGA",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -638,8 +634,8 @@ static void __init pcm037_init(void)
imx31_add_mxc_nand(&pcm037_nand_board_info);
imx31_add_mxc_mmc(0, &sdhc_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx31_add_ipu_core(&mx3_ipu_data);
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* CSI */
/* Camera power: default - off */
@ -649,8 +645,7 @@ static void __init pcm037_init(void)
else
iclink_mt9t031.power = NULL;
if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
mxc_register_device(&mx3_camera, &camera_pdata);
pcm037_init_camera();
platform_device_register(&pcm970_sja1000);
@ -680,9 +675,19 @@ struct sys_timer pcm037_timer = {
.init = pcm037_timer_init,
};
static void __init pcm037_reserve(void)
{
/* reserve 4 MiB for mx3-camera */
mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
MX3_CAMERA_BUF_SIZE);
memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
}
MACHINE_START(PCM037, "Phytec Phycore pcm037")
/* Maintainer: Pengutronix */
.boot_params = MX3x_PHYS_OFFSET + 0x100,
.reserve = pcm037_reserve,
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,

17
arch/arm/mach-mx3/mach-pcm037_eet.c → arch/arm/mach-imx/mach-pcm037_eet.c
View file

@ -7,19 +7,16 @@
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/spi.h>
#include <asm/mach-types.h>
#include "pcm037.h"
#include "devices.h"
#include "devices-imx31.h"
static unsigned int pcm037_eet_pins[] = {
@ -156,20 +153,13 @@ static struct gpio_keys_button pcm037_gpio_keys[] = {
},
};
static struct gpio_keys_platform_data pcm037_gpio_keys_platform_data = {
static const struct gpio_keys_platform_data
pcm037_gpio_keys_platform_data __initconst = {
.buttons = pcm037_gpio_keys,
.nbuttons = ARRAY_SIZE(pcm037_gpio_keys),
.rep = 0, /* No auto-repeat */
};
static struct platform_device pcm037_gpio_keys_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &pcm037_gpio_keys_platform_data,
},
};
static int __init eet_init_devices(void)
{
if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET)
@ -182,9 +172,8 @@ static int __init eet_init_devices(void)
spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
imx31_add_spi_imx0(&pcm037_spi1_pdata);
platform_device_register(&pcm037_gpio_keys_device);
imx_add_gpio_keys(&pcm037_gpio_keys_platform_data);
return 0;
}
late_initcall(eet_init_devices);

1
arch/arm/mach-imx/mach-pcm038.c
View file

@ -36,7 +36,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"

17
arch/arm/mach-mx3/mach-pcm043.c → arch/arm/mach-imx/mach-pcm043.c
View file

@ -36,14 +36,10 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/ulpi.h>
#include <mach/audmux.h>
#include <mach/esdhc.h>
#include "devices-imx35.h"
#include "devices.h"
static const struct fb_videomode fb_modedb[] = {
{
@ -81,12 +77,11 @@ static const struct fb_videomode fb_modedb[] = {
},
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "Sharp-LQ035Q7",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -127,12 +122,12 @@ static struct at24_platform_data board_eeprom = {
};
static struct i2c_board_info pcm043_i2c_devices[] = {
{
{
I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
.platform_data = &board_eeprom,
}, {
I2C_BOARD_INFO("pcf8563", 0x51),
}
},
};
static struct platform_device *devices[] __initdata = {
@ -390,8 +385,8 @@ static void __init pcm043_init(void)
imx35_add_imx_i2c0(&pcm043_i2c0_data);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx35_add_ipu_core(&mx3_ipu_data);
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
if (otg_mode_host) {
otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |

15
arch/arm/mach-mx3/mach-qong.c → arch/arm/mach-imx/mach-qong.c
View file

@ -33,24 +33,23 @@
#include <mach/iomux-mx3.h>
#include "devices-imx31.h"
#include "devices.h"
/* FPGA defines */
#define QONG_FPGA_VERSION(major, minor, rev) \
(((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
#define QONG_FPGA_PERIPH_SIZE (1 << 24)
#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
#define QONG_FPGA_PERIPH_SIZE (1 << 24)
#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
#define QONG_FPGA_CTRL_SIZE 0x10
#define QONG_FPGA_CTRL_SIZE 0x10
/* FPGA control registers */
#define QONG_FPGA_CTRL_VERSION 0x00
#define QONG_DNET_ID 1
#define QONG_DNET_BASEADDR \
(QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
#define QONG_DNET_SIZE 0x00001000
#define QONG_DNET_SIZE 0x00001000
#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
@ -166,15 +165,15 @@ static struct platform_nand_data qong_nand_data = {
.options = 0,
},
.ctrl = {
.cmd_ctrl = qong_nand_cmd_ctrl,
.cmd_ctrl = qong_nand_cmd_ctrl,
.dev_ready = qong_nand_device_ready,
.select_chip = qong_nand_select_chip,
}
};
static struct resource qong_nand_resource = {
.start = MX31_CS3_BASE_ADDR,
.end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
.start = MX31_CS3_BASE_ADDR,
.end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};

25
arch/arm/mach-mx3/mach-vpr200.c → arch/arm/mach-imx/mach-vpr200.c
View file

@ -32,16 +32,12 @@
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/irqs.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/mfd/mc13xxx.h>
#include <linux/gpio_keys.h>
#include "devices-imx35.h"
#include "devices.h"
#define GPIO_LCDPWR IMX_GPIO_NR(1, 2)
#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
@ -91,12 +87,11 @@ static const struct fb_videomode fb_modedb[] = {
}
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "PT0708048",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -141,18 +136,12 @@ static struct gpio_keys_button vpr200_gpio_keys_table[] = {
{KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
};
static struct gpio_keys_platform_data vpr200_gpio_keys_data = {
static const struct gpio_keys_platform_data
vpr200_gpio_keys_data __initconst = {
.buttons = vpr200_gpio_keys_table,
.nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
};
static struct platform_device vpr200_device_gpiokeys = {
.name = "gpio-keys",
.dev = {
.platform_data = &vpr200_gpio_keys_data,
}
};
static struct mc13xxx_platform_data vpr200_pmic = {
.flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
};
@ -271,7 +260,6 @@ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
static struct platform_device *devices[] __initdata = {
&vpr200_flash,
&vpr200_device_gpiokeys,
};
/*
@ -283,6 +271,7 @@ static void __init vpr200_board_init(void)
imx35_add_fec(NULL);
imx35_add_imx2_wdt(NULL);
imx_add_gpio_keys(&vpr200_gpio_keys_data);
platform_add_devices(devices, ARRAY_SIZE(devices));
@ -299,8 +288,8 @@ static void __init vpr200_board_init(void)
imx35_add_imx_uart0(NULL);
imx35_add_imx_uart2(NULL);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx35_add_ipu_core(&mx3_ipu_data);
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
imx35_add_fsl_usb2_udc(&otg_device_pdata);
imx35_add_mxc_ehci_hs(&usb_host_pdata);

66
arch/arm/mach-imx/mm-imx31.c Normal file
View file

@ -0,0 +1,66 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/gpio.h>
#include <mach/irqs.h>
static struct map_desc mx31_io_desc[] __initdata = {
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx31_map_io(void)
{
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
}
void __init imx31_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
}
static struct mxc_gpio_port imx31_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
};
void __init mx31_init_irq(void)
{
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
}

63
arch/arm/mach-imx/mm-imx35.c Normal file
View file

@ -0,0 +1,63 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/gpio.h>
#include <mach/irqs.h>
static struct map_desc mx35_io_desc[] __initdata = {
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
};
void __init mx35_map_io(void)
{
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
}
void __init imx35_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
}
static struct mxc_gpio_port imx35_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
};
void __init mx35_init_irq(void)
{
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
}

13
arch/arm/mach-mx3/mx31lilly-db.c → arch/arm/mach-imx/mx31lilly-db.c
View file

@ -34,11 +34,8 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31lilly.h>
#include <mach/mx3fb.h>
#include <mach/ipu.h>
#include "devices-imx31.h"
#include "devices.h"
/*
* This file contains board-specific initialization routines for the
@ -164,13 +161,13 @@ static const struct imxmmc_platform_data mmc_pdata __initconst = {
};
/* Framebuffer support */
static struct ipu_platform_data ipu_data __initdata = {
static const struct ipu_platform_data ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static const struct fb_videomode fb_modedb = {
/* 640x480 TFT panel (IPS-056T) */
.name = "CRT-VGA",
.name = "CRT-VGA",
.refresh = 64,
.xres = 640,
.yres = 480,
@ -187,7 +184,6 @@ static const struct fb_videomode fb_modedb = {
};
static struct mx3fb_platform_data fb_pdata __initdata = {
.dma_dev = &mx3_ipu.dev,
.name = "CRT-VGA",
.mode = &fb_modedb,
.num_modes = 1,
@ -202,8 +198,8 @@ static void __init mx31lilly_init_fb(void)
return;
}
mxc_register_device(&mx3_ipu, &ipu_data);
mxc_register_device(&mx3_fb, &fb_pdata);
imx31_add_ipu_core(&ipu_data);
imx31_add_mx3_sdc_fb(&fb_pdata);
gpio_direction_output(LCD_VCC_EN_GPIO, 1);
}
@ -218,4 +214,3 @@ void __init mx31lilly_db_init(void)
imx31_add_mxc_mmc(0, &mmc_pdata);
mx31lilly_init_fb();
}

3
arch/arm/mach-mx3/mx31lite-db.c → arch/arm/mach-imx/mx31lite-db.c
View file

@ -37,7 +37,6 @@
#include <mach/board-mx31lite.h>
#include "devices-imx31.h"
#include "devices.h"
/*
* This file contains board-specific initialization routines for the
@ -200,5 +199,5 @@ void __init mx31lite_db_init(void)
imx31_add_spi_imx0(&spi0_pdata);
platform_device_register(&litekit_led_device);
imx31_add_imx2_wdt(NULL);
mxc_register_device(&imx_rtc_device0, NULL);
imx31_add_mxc_rtc(NULL);
}

1
arch/arm/mach-mx3/mx31moboard-devboard.c → arch/arm/mach-imx/mx31moboard-devboard.c
View file

@ -28,7 +28,6 @@
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
static unsigned int devboard_pins[] = {
/* UART1 */

2
arch/arm/mach-mx3/mx31moboard-marxbot.c → arch/arm/mach-imx/mx31moboard-marxbot.c
View file

@ -26,14 +26,12 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/ulpi.h>
#include <media/soc_camera.h>
#include "devices-imx31.h"
#include "devices.h"
static unsigned int marxbot_pins[] = {
/* SDHC2 */

1
arch/arm/mach-mx3/mx31moboard-smartbot.c → arch/arm/mach-imx/mx31moboard-smartbot.c
View file

@ -32,7 +32,6 @@
#include <media/soc_camera.h>
#include "devices-imx31.h"
#include "devices.h"
static unsigned int smartbot_pins[] = {
/* UART1 */

0
arch/arm/mach-mx3/pcm037.h → arch/arm/mach-imx/pcm037.h
View file

257
arch/arm/mach-mx3/Kconfig
View file

@ -1,257 +0,0 @@
if ARCH_MX3
# ARCH_MX31 and ARCH_MX35 are left for compatibility
# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
# more sensible) names are used: SOC_IMX31 and SOC_IMX35
config ARCH_MX31
bool
config ARCH_MX35
bool
config SOC_IMX31
bool
select IMX_HAVE_PLATFORM_MXC_RNGA
select ARCH_MXC_AUDMUX_V2
select ARCH_MX31
select MXC_AVIC
config SOC_IMX35
bool
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select HAVE_EPIT
select ARCH_MX35
select MXC_AVIC
comment "MX3 platforms:"
config MACH_MX31ADS
bool "Support MX31ADS platforms"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
default y
help
Include support for MX31ADS platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31ADS_WM1133_EV1
bool "Support Wolfson Microelectronics 1133-EV1 module"
depends on MACH_MX31ADS
depends on MFD_WM8350_I2C
depends on REGULATOR_WM8350
select MFD_WM8350_CONFIG_MODE_0
select MFD_WM8352_CONFIG_MODE_0
help
Include support for the Wolfson Microelectronics 1133-EV1 PMU
and audio module for the MX31ADS platform.
config MACH_PCM037
bool "Support Phytec pcm037 (i.MX31) platforms"
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm037 platform. This includes
specific configurations for the board and its peripherals.
config MACH_PCM037_EET
bool "Support pcm037 EET board extensions"
depends on MACH_PCM037
select IMX_HAVE_PLATFORM_SPI_IMX
help
Add support for PCM037 EET baseboard extensions. If you are using the
OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
command-line parameter.
config MACH_MX31LITE
bool "Support MX31 LITEKIT (LogicPD)"
select SOC_IMX31
select MXC_ULPI if USB_ULPI
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for MX31 LITEKIT platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31_3DS
bool "Support MX31PDK (3DS)"
select SOC_IMX31
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for MX31PDK (3DS) platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31_3DS_MXC_NAND_USE_BBT
bool "Make the MXC NAND driver use the in flash Bad Block Table"
depends on MACH_MX31_3DS
depends on MTD_NAND_MXC
help
Enable this if you want that the MXC NAND driver uses the in flash
Bad Block Table to know what blocks are bad instead of scanning the
entire flash looking for bad block markers.
config MACH_MX31MOBOARD
bool "Support mx31moboard platforms (EPFL Mobots group)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for mx31moboard platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31LILLY
bool "Support MX31 LILLY-1131 platforms (INCO startec)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for mx31 based LILLY1131 modules. This includes
specific configurations for the board and its peripherals.
config MACH_QONG
bool "Support Dave/DENX QongEVB-LITE platform"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for Dave/DENX QongEVB-LITE platform. This includes
specific configurations for the board and its peripherals.
config MACH_PCM043
bool "Support Phytec pcm043 (i.MX35) platforms"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm043 platform. This includes
specific configurations for the board and its peripherals.
config MACH_ARMADILLO5X0
bool "Support Atmark Armadillo-500 Development Base Board"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select MXC_ULPI if USB_ULPI
help
Include support for Atmark Armadillo-500 platform. This includes
specific configurations for the board and its peripherals.
config MACH_MX35_3DS
bool "Support MX35PDK platform"
select SOC_IMX35
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX35PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_KZM_ARM11_01
bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for KZM-ARM11-01. This includes specific
configurations for the board and its peripherals.
config MACH_BUG
bool "Support Buglabs BUGBase platform"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
default y
help
Include support for BUGBase 1.3 platform. This includes specific
configurations for the board and its peripherals.
config MACH_EUKREA_CPUIMX35
bool "Support Eukrea CPUIMX35 Platform"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX35 platform. This includes
specific configurations for the board and its peripherals.
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX35
default MACH_EUKREA_MBIMXSD35_BASEBOARD
config MACH_EUKREA_MBIMXSD35_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_IMX_SSI
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
config MACH_VPR200
bool "Support VPR200 platform"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for VPR200 platform. This includes specific
configurations for the board and its peripherals.
endif

26
arch/arm/mach-mx3/Makefile
View file

@ -1,26 +0,0 @@
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := mm.o devices.o cpu.o
obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o ehci-imx31.o
obj-$(CONFIG_SOC_IMX35) += clock-imx35.o ehci-imx35.o
obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
mx31moboard-marxbot.o mx31moboard-smartbot.o
obj-$(CONFIG_MACH_QONG) += mach-qong.o
obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
obj-$(CONFIG_MACH_BUG) += mach-bug.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o
obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o

3
arch/arm/mach-mx3/Makefile.boot
View file

@ -1,3 +0,0 @@
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000

115
arch/arm/mach-mx3/devices.c
View file

@ -1,115 +0,0 @@
/*
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/common.h>
#include <mach/mx3_camera.h>
#include "devices.h"
/* i.MX31 Image Processing Unit */
/* The resource order is important! */
static struct resource mx3_ipu_rsrc[] = {
{
.start = MX3x_IPU_CTRL_BASE_ADDR,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
.flags = IORESOURCE_MEM,
}, {
.start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
.flags = IORESOURCE_MEM,
}, {
.start = MX3x_INT_IPU_SYN,
.end = MX3x_INT_IPU_SYN,
.flags = IORESOURCE_IRQ,
}, {
.start = MX3x_INT_IPU_ERR,
.end = MX3x_INT_IPU_ERR,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx3_ipu = {
.name = "ipu-core",
.id = -1,
.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
.resource = mx3_ipu_rsrc,
};
static struct resource fb_resources[] = {
{
.start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mx3_fb = {
.name = "mx3_sdc_fb",
.id = -1,
.num_resources = ARRAY_SIZE(fb_resources),
.resource = fb_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource camera_resources[] = {
{
.start = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mx3_camera = {
.name = "mx3-camera",
.id = 0,
.num_resources = ARRAY_SIZE(camera_resources),
.resource = camera_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource imx_rtc_resources[] = {
{
.start = MX31_RTC_BASE_ADDR,
.end = MX31_RTC_BASE_ADDR + 0x3fff,
.flags = IORESOURCE_MEM,
},
{
.start = MX31_INT_RTC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_rtc_device0 = {
.name = "mxc_rtc",
.id = -1,
.num_resources = ARRAY_SIZE(imx_rtc_resources),
.resource = imx_rtc_resources,
};

4
arch/arm/mach-mx3/devices.h
View file

@ -1,4 +0,0 @@
extern struct platform_device mx3_ipu;
extern struct platform_device mx3_fb;
extern struct platform_device mx3_camera;
extern struct platform_device imx_rtc_device0;

141
arch/arm/mach-mx3/mm.c
View file

@ -1,141 +0,0 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/gpio.h>
#include <mach/irqs.h>
#ifdef CONFIG_SOC_IMX31
static struct map_desc mx31_io_desc[] __initdata = {
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx31_map_io(void)
{
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
}
void __init imx31_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
}
static struct mxc_gpio_port imx31_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
};
void __init mx31_init_irq(void)
{
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
}
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
static struct map_desc mx35_io_desc[] __initdata = {
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
};
void __init mx35_map_io(void)
{
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
}
void __init imx35_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
}
static struct mxc_gpio_port imx35_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
};
void __init mx35_init_irq(void)
{
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
}
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_CACHE_L2X0
static int mxc_init_l2x0(void)
{
void __iomem *l2x0_base;
void __iomem *clkctl_base;
/*
* First of all, we must repair broken chip settings. There are some
* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
* Workaraound is to setup the correct register setting prior enabling the
* L2 cache. This should not hurt already working CPUs, as they are using the
* same value
*/
#define L2_MEM_VAL 0x10
clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
if (clkctl_base != NULL) {
writel(0x00000515, clkctl_base + L2_MEM_VAL);
iounmap(clkctl_base);
} else {
pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
}
l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
if (IS_ERR(l2x0_base)) {
printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
PTR_ERR(l2x0_base));
return 0;
}
l2x0_init(l2x0_base, 0x00030024, 0x00000000);
return 0;
}
arch_initcall(mxc_init_l2x0);
#endif

58
arch/arm/mach-mx5/Kconfig
View file

@ -1,11 +1,11 @@
if ARCH_MX5
# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single
if ARCH_MX503 || ARCH_MX51
# ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single
# image. So for most time, SOC_IMX50/51/53 should be used.
config ARCH_MX50
config ARCH_MX5
bool
config ARCH_MX51
config ARCH_MX50
bool
config ARCH_MX53
@ -13,27 +13,54 @@ config ARCH_MX53
config SOC_IMX50
bool
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select ARCH_HAS_CPUFREQ
select ARCH_MX5
select ARCH_MX50
config SOC_IMX51
bool
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select ARCH_HAS_CPUFREQ
select ARCH_MX51
select ARCH_MX5
config SOC_IMX53
bool
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MX5
select ARCH_MX53
comment "MX5 platforms:"
if ARCH_MX50_SUPPORTED
#comment "i.MX50 machines:"
config MACH_MX50_RDP
bool "Support MX50 reference design platform"
depends on BROKEN
select SOC_IMX50
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select IMX_HAVE_PLATFORM_FEC
help
Include support for MX50 reference design platform (RDP) board. This
includes specific configurations for the board and its peripherals.
endif # ARCH_MX50_SUPPORTED
if ARCH_MX51
comment "i.MX51 machines:"
config MACH_MX51_BABBAGE
bool "Support MX51 BABBAGE platforms"
@ -136,6 +163,11 @@ config MACH_MX51_EFIKASB
Include support for Genesi Efika Smartbook. This includes specific
configurations for the board and its peripherals.
endif # ARCH_MX51
if ARCH_MX53_SUPPORTED
comment "i.MX53 machines:"
config MACH_MX53_EVK
bool "Support MX53 EVK platforms"
select SOC_IMX53
@ -154,6 +186,7 @@ config MACH_MX53_SMD
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX53 SMD platform. This includes specific
configurations for the board and its peripherals.
@ -170,17 +203,6 @@ config MACH_MX53_LOCO
Include support for MX53 LOCO platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX50_RDP
bool "Support MX50 reference design platform"
depends on BROKEN
select SOC_IMX50
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select IMX_HAVE_PLATFORM_FEC
help
Include support for MX50 reference design platform (RDP) board. This
includes specific configurations for the board and its peripherals.
endif # ARCH_MX53_SUPPORTED
endif

2
arch/arm/mach-mx5/board-cpuimx51.c
View file

@ -23,13 +23,11 @@
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/fsl_devices.h>
#include <mach/eukrea-baseboards.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>

2
arch/arm/mach-mx5/board-cpuimx51sd.c
View file

@ -23,7 +23,6 @@
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/fsl_devices.h>
#include <linux/i2c-gpio.h>
#include <linux/spi/spi.h>
#include <linux/can/platform/mcp251x.h>
@ -32,7 +31,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>

1
arch/arm/mach-mx5/board-mx50_rdp.c
View file

@ -23,7 +23,6 @@
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <mach/common.h>
#include <mach/hardware.h>

18
arch/arm/mach-mx5/board-mx51_babbage.c
View file

@ -16,9 +16,6 @@
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/fec.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
@ -26,7 +23,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
@ -208,18 +204,16 @@ static inline void babbage_usbhub_reset(void)
{
int ret;
/* Bring USB hub out of reset */
ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
/* Reset USB hub */
ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
GPIOF_OUT_INIT_LOW, "GPIO1_7");
if (ret) {
printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
return;
}
gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
/* USB HUB RESET - De-assert USB HUB RESET_N */
msleep(1);
gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
msleep(1);
msleep(2);
/* Deassert reset */
gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
}
@ -361,7 +355,7 @@ static void __init mx51_babbage_init(void)
/* Set the PAD settings for the pwr key. */
mxc_iomux_v3_setup_pad(power_key);
imx51_add_gpio_keys(&imx_button_data);
imx_add_gpio_keys(&imx_button_data);
imx51_add_imx_i2c(0, &babbage_i2c_data);
imx51_add_imx_i2c(1, &babbage_i2c_data);

5
arch/arm/mach-mx5/board-mx51_efikamx.c
View file

@ -22,7 +22,6 @@
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13892.h>
@ -32,8 +31,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/i2c.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
@ -252,7 +249,7 @@ static void __init mx51_efikamx_init(void)
}
platform_device_register(&mx51_efikamx_leds_device);
imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
if (system_rev == 0x11) {
gpio_request(EFIKAMX_RESET1_1, "reset");

5
arch/arm/mach-mx5/board-mx51_efikasb.c
View file

@ -22,7 +22,6 @@
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13892.h>
@ -35,8 +34,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/i2c.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
@ -260,7 +257,7 @@ static void __init efikasb_board_init(void)
imx51_add_sdhci_esdhc_imx(1, NULL);
platform_device_register(&mx51_efikasb_leds_device);
imx51_add_gpio_keys(&mx51_efikasb_keys_data);
imx_add_gpio_keys(&mx51_efikasb_keys_data);
}

2
arch/arm/mach-mx5/board-mx53_evk.c
View file

@ -21,7 +21,6 @@
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/spi/flash.h>
@ -31,7 +30,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)

2
arch/arm/mach-mx5/board-mx53_loco.c
View file

@ -20,13 +20,11 @@
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>

30
arch/arm/mach-mx5/board-mx53_smd.c
View file

@ -20,13 +20,11 @@
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>
@ -52,6 +50,31 @@ static iomux_v3_cfg_t mx53_smd_pads[] = {
/* I2C1 */
MX53_PAD_CSI0_DAT8__I2C1_SDA,
MX53_PAD_CSI0_DAT9__I2C1_SCL,
/* SD1 */
MX53_PAD_SD1_CMD__ESDHC1_CMD,
MX53_PAD_SD1_CLK__ESDHC1_CLK,
MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
/* SD2 */
MX53_PAD_SD2_CMD__ESDHC2_CMD,
MX53_PAD_SD2_CLK__ESDHC2_CLK,
MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
/* SD3 */
MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
MX53_PAD_PATA_IORDY__ESDHC3_CLK,
MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
};
static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
@ -97,6 +120,9 @@ static void __init mx53_smd_board_init(void)
imx53_add_fec(&mx53_smd_fec_data);
imx53_add_imx2_wdt(0, NULL);
imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
imx53_add_sdhci_esdhc_imx(0, NULL);
imx53_add_sdhci_esdhc_imx(1, NULL);
imx53_add_sdhci_esdhc_imx(2, NULL);
}
static void __init mx53_smd_timer_init(void)

1
arch/arm/mach-mx5/clock-mx51-mx53.c
View file

@ -1563,6 +1563,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
clk_enable(&iim_clk);
mx53_revision();
clk_disable(&iim_clk);
mx53_display_revision();
/* Set SDHC parents to be PLL2 */
clk_set_parent(&esdhc1_clk, &pll2_sw_clk);

23
arch/arm/mach-mx5/cpu.c
View file

@ -166,6 +166,29 @@ int mx50_revision(void)
}
EXPORT_SYMBOL(mx50_revision);
void mx53_display_revision(void)
{
int rev;
char *srev;
rev = mx53_revision();
switch (rev) {
case IMX_CHIP_REVISION_1_0:
srev = IMX_CHIP_REVISION_1_0_STRING;
break;
case IMX_CHIP_REVISION_2_0:
srev = IMX_CHIP_REVISION_2_0_STRING;
break;
case IMX_CHIP_REVISION_2_1:
srev = IMX_CHIP_REVISION_2_1_STRING;
break;
default:
srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
}
printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev);
}
EXPORT_SYMBOL(mx53_display_revision);
static int __init post_cpu_init(void)
{
unsigned int reg;

6
arch/arm/mach-mx5/devices-imx50.h
View file

@ -21,14 +21,14 @@
#include <mach/mx50.h>
#include <mach/devices-common.h>
extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
#define imx50_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
extern const struct imx_fec_data imx50_fec_data __initconst;
extern const struct imx_fec_data imx50_fec_data;
#define imx50_add_fec(pdata) \
imx_add_fec(&imx50_fec_data, pdata)
extern const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst;
extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
#define imx50_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)

25
arch/arm/mach-mx5/devices-imx51.h
View file

@ -9,49 +9,46 @@
#include <mach/mx51.h>
#include <mach/devices-common.h>
extern const struct imx_fec_data imx51_fec_data __initconst;
extern const struct imx_fec_data imx51_fec_data;
#define imx51_add_fec(pdata) \
imx_add_fec(&imx51_fec_data, pdata)
#define imx51_add_gpio_keys(pdata) imx_add_gpio_keys(pdata)
extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
#define imx51_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst;
extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
#define imx51_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
#define imx51_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
#define imx51_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
extern const struct imx_sdhci_esdhc_imx_data
imx51_sdhci_esdhc_imx_data[] __initconst;
extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
#define imx51_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
extern const struct imx_spi_imx_data imx51_cspi_data;
#define imx51_add_cspi(pdata) \
imx_add_spi_imx(&imx51_cspi_data, pdata)
extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
extern const struct imx_spi_imx_data imx51_ecspi_data[];
#define imx51_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst;
extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
#define imx51_add_imx2_wdt(id, pdata) \
imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst;
extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
#define imx51_add_mxc_pwm(id) \
imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
extern const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst;
extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
#define imx51_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)

13
arch/arm/mach-mx5/devices-imx53.h
View file

@ -8,28 +8,27 @@
#include <mach/mx53.h>
#include <mach/devices-common.h>
extern const struct imx_fec_data imx53_fec_data __initconst;
extern const struct imx_fec_data imx53_fec_data;
#define imx53_add_fec(pdata) \
imx_add_fec(&imx53_fec_data, pdata)
extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
#define imx53_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
extern const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst;
extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
#define imx53_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
extern const struct imx_sdhci_esdhc_imx_data
imx53_sdhci_esdhc_imx_data[] __initconst;
extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
#define imx53_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
extern const struct imx_spi_imx_data imx53_ecspi_data[];
#define imx53_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst;
extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
#define imx53_add_imx2_wdt(id, pdata) \
imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])

2
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
View file

@ -18,13 +18,11 @@
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/fsl_devices.h>
#include <linux/i2c/tsc2007.h>
#include <linux/leds.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx51.h>
#include <asm/mach/arch.h>

16
arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
View file

@ -27,7 +27,6 @@
#include <linux/irq.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/i2c.h>
@ -38,7 +37,6 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx51.h>
#include <mach/audmux.h>
@ -108,23 +106,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
},
};
static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
static const struct gpio_keys_platform_data
eukrea_mbimxsd_button_data __initconst = {
.buttons = eukrea_mbimxsd_gpio_buttons,
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
};
static struct platform_device eukrea_mbimxsd_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &eukrea_mbimxsd_button_data,
}
};
static struct platform_device *platform_devices[] __initdata = {
&eukrea_mbimxsd_leds_gpio,
&eukrea_mbimxsd_button_device,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
@ -166,4 +155,5 @@ void __init eukrea_mbimxsd51_baseboard_init(void)
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
}

3
arch/arm/mach-mx5/mx51_efika.c
View file

@ -20,7 +20,6 @@
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13892.h>
@ -30,8 +29,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/i2c.h>
#include <mach/mxc_ehci.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>

11
arch/arm/mach-mxc91231/Kconfig
View file

@ -1,11 +0,0 @@
if ARCH_MXC91231
comment "MXC91231 platforms:"
config MACH_MAGX_ZN5
bool "Support Motorola Zn5 GSM phone"
default n
help
Include support for Motorola Zn5 GSM phone.
endif

2
arch/arm/mach-mxc91231/Makefile
View file

@ -1,2 +0,0 @@
obj-y := mm.o clock.o devices.o system.o iomux.o
obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o

3
arch/arm/mach-mxc91231/Makefile.boot
View file

@ -1,3 +0,0 @@
zreladdr-y := 0x90008000
params_phys-y := 0x90000100
initrd_phys-y := 0x90800000

640
arch/arm/mach-mxc91231/clock.c
View file

@ -1,640 +0,0 @@
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <mach/clock.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <asm/bug.h>
#include <asm/div64.h>
#include "crm_regs.h"
#define CRM_SMALL_DIVIDER(base, name) \
crm_small_divider(base, \
base ## _ ## name ## _OFFSET, \
base ## _ ## name ## _MASK)
#define CRM_1DIVIDER(base, name) \
crm_divider(base, \
base ## _ ## name ## _OFFSET, \
base ## _ ## name ## _MASK, 1)
#define CRM_16DIVIDER(base, name) \
crm_divider(base, \
base ## _ ## name ## _OFFSET, \
base ## _ ## name ## _MASK, 16)
static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
{
static const u32 crm_small_dividers[] = {
2, 3, 4, 5, 6, 8, 10, 12
};
u8 idx;
idx = (__raw_readl(reg) & mask) >> offset;
if (idx > 7)
return 1;
return crm_small_dividers[idx];
}
static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
{
u32 div;
div = (__raw_readl(reg) & mask) >> offset;
return div ? div : z;
}
static int _clk_1bit_enable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg |= 1 << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
return 0;
}
static void _clk_1bit_disable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg &= ~(1 << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
}
static int _clk_3bit_enable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg |= 0x7 << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
return 0;
}
static void _clk_3bit_disable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg &= ~(0x7 << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
}
static unsigned long ckih_rate;
static unsigned long clk_ckih_get_rate(struct clk *clk)
{
return ckih_rate;
}
static struct clk ckih_clk = {
.get_rate = clk_ckih_get_rate,
};
static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
{
return 2 * clk_get_rate(clk->parent);
}
static struct clk ckih_x2_clk = {
.parent = &ckih_clk,
.get_rate = clk_ckih_x2_get_rate,
};
static unsigned long clk_ckil_get_rate(struct clk *clk)
{
return CKIL_CLK_FREQ;
}
static struct clk ckil_clk = {
.get_rate = clk_ckil_get_rate,
};
/* plls stuff */
static struct clk mcu_pll_clk;
static struct clk dsp_pll_clk;
static struct clk usb_pll_clk;
static struct clk *pll_clk(u8 sel)
{
switch (sel) {
case 0:
return &mcu_pll_clk;
case 1:
return &dsp_pll_clk;
case 2:
return &usb_pll_clk;
}
BUG();
}
static void __iomem *pll_base(struct clk *clk)
{
if (clk == &mcu_pll_clk)
return MXC_PLL0_BASE;
else if (clk == &dsp_pll_clk)
return MXC_PLL1_BASE;
else if (clk == &usb_pll_clk)
return MXC_PLL2_BASE;
BUG();
}
static unsigned long clk_pll_get_rate(struct clk *clk)
{
const void __iomem *pllbase;
unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
long mfn, mfn_abs, mfd, pdf;
s64 temp;
pllbase = pll_base(clk);
pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
if (pll_hfsm == 0) {
dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
} else {
dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
}
pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
mfi = (mfi <= 5) ? 5 : mfi;
mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
if (mfn < 0)
mfn_abs = -mfn;
else
mfn_abs = mfn;
/* XXX: actually this asumes that ckih is fed to pll, but spec says
* that ckih_x2 is also possible. need to check this out.
*/
ref_clk = clk_get_rate(&ckih_clk);
ref_clk *= 2;
ref_clk /= pdf + 1;
temp = (u64) ref_clk * mfn_abs;
do_div(temp, mfd);
if (mfn < 0)
temp = -temp;
temp += ref_clk * mfi;
return temp;
}
static int clk_pll_enable(struct clk *clk)
{
void __iomem *ctl;
u32 reg;
ctl = pll_base(clk);
reg = __raw_readl(ctl);
reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
__raw_writel(reg, ctl);
do {
reg = __raw_readl(ctl);
} while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
return 0;
}
static void clk_pll_disable(struct clk *clk)
{
void __iomem *ctl;
u32 reg;
ctl = pll_base(clk);
reg = __raw_readl(ctl);
reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
__raw_writel(reg, ctl);
}
static struct clk mcu_pll_clk = {
.parent = &ckih_clk,
.get_rate = clk_pll_get_rate,
.enable = clk_pll_enable,
.disable = clk_pll_disable,
};
static struct clk dsp_pll_clk = {
.parent = &ckih_clk,
.get_rate = clk_pll_get_rate,
.enable = clk_pll_enable,
.disable = clk_pll_disable,
};
static struct clk usb_pll_clk = {
.parent = &ckih_clk,
.get_rate = clk_pll_get_rate,
.enable = clk_pll_enable,
.disable = clk_pll_disable,
};
/* plls stuff end */
/* ap_ref_clk stuff */
static struct clk ap_ref_clk;
static unsigned long clk_ap_ref_get_rate(struct clk *clk)
{
u32 ascsr, acsr;
u8 ap_pat_ref_div_2, ap_isel, acs, ads;
ascsr = __raw_readl(MXC_CRMAP_ASCSR);
acsr = __raw_readl(MXC_CRMAP_ACSR);
/* 0 for ckih, 1 for ckih*2 */
ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
/* reg divider */
ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
/* undocumented, 1 for disabling divider */
ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
/* 0 for pat_ref, 1 for divider out */
acs = acsr & MXC_CRMAP_ACSR_ACS;
if (acs & !ads)
/* use divided clock */
return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
}
static struct clk ap_ref_clk = {
.parent = &ckih_clk,
.get_rate = clk_ap_ref_get_rate,
};
/* ap_ref_clk stuff end */
/* ap_pre_dfs_clk stuff */
static struct clk ap_pre_dfs_clk;
static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
{
u32 acsr, ascsr;
acsr = __raw_readl(MXC_CRMAP_ACSR);
ascsr = __raw_readl(MXC_CRMAP_ASCSR);
if (acsr & MXC_CRMAP_ACSR_ACS) {
u8 sel;
sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
MXC_CRMAP_ASCSR_APSEL_OFFSET;
return clk_get_rate(pll_clk(sel)) /
CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
}
return clk_get_rate(&ap_ref_clk);
}
static struct clk ap_pre_dfs_clk = {
.get_rate = clk_ap_pre_dfs_get_rate,
};
/* ap_pre_dfs_clk stuff end */
/* usb_clk stuff */
static struct clk usb_clk;
static struct clk *clk_usb_parent(struct clk *clk)
{
u32 acsr, ascsr;
acsr = __raw_readl(MXC_CRMAP_ACSR);
ascsr = __raw_readl(MXC_CRMAP_ASCSR);
if (acsr & MXC_CRMAP_ACSR_ACS) {
u8 sel;
sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
MXC_CRMAP_ASCSR_USBSEL_OFFSET;
return pll_clk(sel);
}
return &ap_ref_clk;
}
static unsigned long clk_usb_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) /
CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
}
static struct clk usb_clk = {
.enable_reg = MXC_CRMAP_ACDER2,
.enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
.get_rate = clk_usb_get_rate,
.enable = _clk_1bit_enable,
.disable = _clk_1bit_disable,
};
/* usb_clk stuff end */
static unsigned long clk_ipg_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
}
static unsigned long clk_ahb_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) /
CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
}
static struct clk ipg_clk = {
.parent = &ap_pre_dfs_clk,
.get_rate = clk_ipg_get_rate,
};
static struct clk ahb_clk = {
.parent = &ap_pre_dfs_clk,
.get_rate = clk_ahb_get_rate,
};
/* perclk_clk stuff */
static struct clk perclk_clk;
static unsigned long clk_perclk_get_rate(struct clk *clk)
{
u32 acder2;
acder2 = __raw_readl(MXC_CRMAP_ACDER2);
if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
return 2 * clk_get_rate(clk->parent);
return clk_get_rate(clk->parent);
}
static struct clk perclk_clk = {
.parent = &ckih_clk,
.get_rate = clk_perclk_get_rate,
};
/* perclk_clk stuff end */
/* uart_clk stuff */
static struct clk uart_clk[];
static unsigned long clk_uart_get_rate(struct clk *clk)
{
u32 div;
switch (clk->id) {
case 0:
case 1:
div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
break;
case 2:
div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
break;
default:
BUG();
}
return clk_get_rate(clk->parent) / div;
}
static struct clk uart_clk[] = {
{
.id = 0,
.parent = &perclk_clk,
.enable_reg = MXC_CRMAP_APRA,
.enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
.get_rate = clk_uart_get_rate,
.enable = _clk_1bit_enable,
.disable = _clk_1bit_disable,
}, {
.id = 1,
.parent = &perclk_clk,
.enable_reg = MXC_CRMAP_APRA,
.enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
.get_rate = clk_uart_get_rate,
.enable = _clk_1bit_enable,
.disable = _clk_1bit_disable,
}, {
.id = 2,
.parent = &perclk_clk,
.enable_reg = MXC_CRMAP_APRA,
.enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
.get_rate = clk_uart_get_rate,
.enable = _clk_1bit_enable,
.disable = _clk_1bit_disable,
},
};
/* uart_clk stuff end */
/* sdhc_clk stuff */
static struct clk nfc_clk;
static unsigned long clk_nfc_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) /
CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
}
static struct clk nfc_clk = {
.parent = &ahb_clk,
.enable_reg = MXC_CRMAP_ACDER2,
.enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
.get_rate = clk_nfc_get_rate,
.enable = _clk_1bit_enable,
.disable = _clk_1bit_disable,
};
/* sdhc_clk stuff end */
/* sdhc_clk stuff */
static struct clk sdhc_clk[];
static struct clk *clk_sdhc_parent(struct clk *clk)
{
u32 aprb;
u8 sel;
u32 mask;
int offset;
aprb = __raw_readl(MXC_CRMAP_APRB);
switch (clk->id) {
case 0:
mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
break;
case 1:
mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
break;
default:
BUG();
}
sel = (aprb & mask) >> offset;
switch (sel) {
case 0:
return &ckih_clk;
case 1:
return &ckih_x2_clk;
}
return &usb_clk;
}
static unsigned long clk_sdhc_get_rate(struct clk *clk)
{
u32 div;
switch (clk->id) {
case 0:
div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
break;
case 1:
div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
break;
default:
BUG();
}
return clk_get_rate(clk->parent) / div;
}
static int clk_sdhc_enable(struct clk *clk)
{
u32 amlpmre1, aprb;
amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
aprb = __raw_readl(MXC_CRMAP_APRB);
switch (clk->id) {
case 0:
amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
break;
case 1:
amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
break;
}
__raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
__raw_writel(aprb, MXC_CRMAP_APRB);
return 0;
}
static void clk_sdhc_disable(struct clk *clk)
{
u32 amlpmre1, aprb;
amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
aprb = __raw_readl(MXC_CRMAP_APRB);
switch (clk->id) {
case 0:
amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
break;
case 1:
amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
break;
}
__raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
__raw_writel(aprb, MXC_CRMAP_APRB);
}
static struct clk sdhc_clk[] = {
{
.id = 0,
.get_rate = clk_sdhc_get_rate,
.enable = clk_sdhc_enable,
.disable = clk_sdhc_disable,
}, {
.id = 1,
.get_rate = clk_sdhc_get_rate,
.enable = clk_sdhc_enable,
.disable = clk_sdhc_disable,
},
};
/* sdhc_clk stuff end */
/* wdog_clk stuff */
static struct clk wdog_clk[] = {
{
.id = 0,
.parent = &ipg_clk,
.enable_reg = MXC_CRMAP_AMLPMRD,
.enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
.enable = _clk_3bit_enable,
.disable = _clk_3bit_disable,
}, {
.id = 1,
.parent = &ipg_clk,
.enable_reg = MXC_CRMAP_AMLPMRD,
.enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
.enable = _clk_3bit_enable,
.disable = _clk_3bit_disable,
},
};
/* wdog_clk stuff end */
/* gpt_clk stuff */
static struct clk gpt_clk = {
.parent = &ipg_clk,
.enable_reg = MXC_CRMAP_AMLPMRC,
.enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
.enable = _clk_3bit_enable,
.disable = _clk_3bit_disable,
};
/* gpt_clk stuff end */
/* cspi_clk stuff */
static struct clk cspi_clk[] = {
{
.id = 0,
.parent = &ipg_clk,
.enable_reg = MXC_CRMAP_AMLPMRE2,
.enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
.enable = _clk_3bit_enable,
.disable = _clk_3bit_disable,
}, {
.id = 1,
.parent = &ipg_clk,
.enable_reg = MXC_CRMAP_AMLPMRE1,
.enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
.enable = _clk_3bit_enable,
.disable = _clk_3bit_disable,
},
};
/* cspi_clk stuff end */
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
.con_id = n, \
.clk = &c, \
},
static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
_REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
_REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
_REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
_REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
_REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
_REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
_REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
};
int __init mxc91231_clocks_init(unsigned long fref)
{
void __iomem *gpt_base;
ckih_rate = fref;
usb_clk.parent = clk_usb_parent(&usb_clk);
sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
return 0;
}

394
arch/arm/mach-mxc91231/crm_regs.h
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@ -1,394 +0,0 @@
/*
* Copyright 2006 Freescale Semiconductor, Inc.
* Copyright 2006-2007 Motorola, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
#define CKIL_CLK_FREQ 32768
#define MXC_CRM_AP_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
#define MXC_CRM_COM_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
#define MXC_DSM_BASE MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
#define MXC_PLL0_BASE MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
#define MXC_PLL1_BASE MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
#define MXC_PLL2_BASE MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
#define MXC_CLKCTL_BASE MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
/* PLL Register Offsets */
#define MXC_PLL_DP_CTL 0x00
#define MXC_PLL_DP_CONFIG 0x04
#define MXC_PLL_DP_OP 0x08
#define MXC_PLL_DP_MFD 0x0C
#define MXC_PLL_DP_MFN 0x10
#define MXC_PLL_DP_HFS_OP 0x1C
#define MXC_PLL_DP_HFS_MFD 0x20
#define MXC_PLL_DP_HFS_MFN 0x24
/* PLL Register Bit definitions */
#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
#define MXC_PLL_DP_CTL_ADE 0x800
#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
#define MXC_PLL_DP_CTL_HFSM 0x80
#define MXC_PLL_DP_CTL_PRE 0x40
#define MXC_PLL_DP_CTL_UPEN 0x20
#define MXC_PLL_DP_CTL_RST 0x10
#define MXC_PLL_DP_CTL_RCP 0x8
#define MXC_PLL_DP_CTL_PLM 0x4
#define MXC_PLL_DP_CTL_BRM0 0x2
#define MXC_PLL_DP_CTL_LRF 0x1
#define MXC_PLL_DP_OP_MFI_OFFSET 4
#define MXC_PLL_DP_OP_MFI_MASK 0xF
#define MXC_PLL_DP_OP_PDF_OFFSET 0
#define MXC_PLL_DP_OP_PDF_MASK 0xF
#define MXC_PLL_DP_MFD_OFFSET 0
#define MXC_PLL_DP_MFD_MASK 0x7FFFFFF
#define MXC_PLL_DP_MFN_OFFSET 0
#define MXC_PLL_DP_MFN_MASK 0x7FFFFFF
/* CRM AP Register Offsets */
#define MXC_CRMAP_ASCSR (MXC_CRM_AP_BASE + 0x00)
#define MXC_CRMAP_ACDR (MXC_CRM_AP_BASE + 0x04)
#define MXC_CRMAP_ACDER1 (MXC_CRM_AP_BASE + 0x08)
#define MXC_CRMAP_ACDER2 (MXC_CRM_AP_BASE + 0x0C)
#define MXC_CRMAP_ACGCR (MXC_CRM_AP_BASE + 0x10)
#define MXC_CRMAP_ACCGCR (MXC_CRM_AP_BASE + 0x14)
#define MXC_CRMAP_AMLPMRA (MXC_CRM_AP_BASE + 0x18)
#define MXC_CRMAP_AMLPMRB (MXC_CRM_AP_BASE + 0x1C)
#define MXC_CRMAP_AMLPMRC (MXC_CRM_AP_BASE + 0x20)
#define MXC_CRMAP_AMLPMRD (MXC_CRM_AP_BASE + 0x24)
#define MXC_CRMAP_AMLPMRE1 (MXC_CRM_AP_BASE + 0x28)
#define MXC_CRMAP_AMLPMRE2 (MXC_CRM_AP_BASE + 0x2C)
#define MXC_CRMAP_AMLPMRF (MXC_CRM_AP_BASE + 0x30)
#define MXC_CRMAP_AMLPMRG (MXC_CRM_AP_BASE + 0x34)
#define MXC_CRMAP_APGCR (MXC_CRM_AP_BASE + 0x38)
#define MXC_CRMAP_ACSR (MXC_CRM_AP_BASE + 0x3C)
#define MXC_CRMAP_ADCR (MXC_CRM_AP_BASE + 0x40)
#define MXC_CRMAP_ACR (MXC_CRM_AP_BASE + 0x44)
#define MXC_CRMAP_AMCR (MXC_CRM_AP_BASE + 0x48)
#define MXC_CRMAP_APCR (MXC_CRM_AP_BASE + 0x4C)
#define MXC_CRMAP_AMORA (MXC_CRM_AP_BASE + 0x50)
#define MXC_CRMAP_AMORB (MXC_CRM_AP_BASE + 0x54)
#define MXC_CRMAP_AGPR (MXC_CRM_AP_BASE + 0x58)
#define MXC_CRMAP_APRA (MXC_CRM_AP_BASE + 0x5C)
#define MXC_CRMAP_APRB (MXC_CRM_AP_BASE + 0x60)
#define MXC_CRMAP_APOR (MXC_CRM_AP_BASE + 0x64)
#define MXC_CRMAP_ADFMR (MXC_CRM_AP_BASE + 0x68)
/* CRM AP Register Bit definitions */
#define MXC_CRMAP_ASCSR_CRS 0x10000
#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET 15
#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2 0x8000
#define MXC_CRMAP_ASCSR_USBSEL_OFFSET 13
#define MXC_CRMAP_ASCSR_USBSEL_MASK (0x3 << 13)
#define MXC_CRMAP_ASCSR_CSISEL_OFFSET 11
#define MXC_CRMAP_ASCSR_CSISEL_MASK (0x3 << 11)
#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET 7
#define MXC_CRMAP_ASCSR_SSI2SEL_MASK (0x3 << 7)
#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET 5
#define MXC_CRMAP_ASCSR_SSI1SEL_MASK (0x3 << 5)
#define MXC_CRMAP_ASCSR_APSEL_OFFSET 3
#define MXC_CRMAP_ASCSR_APSEL_MASK (0x3 << 3)
#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET 2
#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1 0x4
#define MXC_CRMAP_ASCSR_APISEL 0x1
#define MXC_CRMAP_ACDR_ARMDIV_OFFSET 8
#define MXC_CRMAP_ACDR_ARMDIV_MASK (0xF << 8)
#define MXC_CRMAP_ACDR_AHBDIV_OFFSET 4
#define MXC_CRMAP_ACDR_AHBDIV_MASK (0xF << 4)
#define MXC_CRMAP_ACDR_IPDIV_OFFSET 0
#define MXC_CRMAP_ACDR_IPDIV_MASK 0xF
#define MXC_CRMAP_ACDER1_CSIEN_OFFSET 30
#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET 24
#define MXC_CRMAP_ACDER1_CSIDIV_MASK (0x3F << 24)
#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET 14
#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET 8
#define MXC_CRMAP_ACDER1_SSI2DIV_MASK (0x3F << 8)
#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET 6
#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET 0
#define MXC_CRMAP_ACDER1_SSI1DIV_MASK 0x3F
#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET 24
#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK (0x7 << 24)
#define MXC_CRMAP_ACDER2_NFCEN_OFFSET 20
#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET 16
#define MXC_CRMAP_ACDER2_NFCDIV_MASK (0xF << 16)
#define MXC_CRMAP_ACDER2_USBEN_OFFSET 12
#define MXC_CRMAP_ACDER2_USBDIV_OFFSET 8
#define MXC_CRMAP_ACDER2_USBDIV_MASK (0xF << 8)
#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET 5
#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK (0x3 << 5)
#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET 0
#define MXC_CRMAP_ACDER2_BAUDDIV_MASK 0xF
#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET 22
#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK (0x7 << 22)
#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET 19
#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK (0x7 << 19)
#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET 12
#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK (0x7 << 12)
#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET 9
#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET 6
#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET 3
#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK (0x7 << 3)
#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET 0
#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK 0x7
#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET 28
#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK (0x7 << 28)
#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET 22
#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK (0x7 << 22)
#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET 16
#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK (0x7 << 16)
#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET 12
#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK (0x7 << 12)
#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET 9
#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET 6
#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET 3
#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK (0x7 << 3)
#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET 0
#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK 0x7
#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET 22
#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK (0x7 << 22)
#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET 12
#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK (0x7 << 12)
#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET 9
#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET 6
#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET 0
#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK 0x7
#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET 28
#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK (0x7 << 28)
#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET 25
#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK (0x7 << 25)
#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET 22
#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK (0x7 << 22)
#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET 19
#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK (0x7 << 19)
#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET 16
#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK (0x7 << 16)
#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET 12
#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK (0x7 << 12)
#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET 9
#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET 6
#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET 3
#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK (0x7 << 3)
#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET 0
#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK 0x7
#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET 0
#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK 0x7
#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET 19
#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK (0x7 << 19)
#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET 16
#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK (0x7 << 16)
#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET 9
#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET 6
#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET 3
#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK (0x7 << 3)
#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET 0
#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK (0x7 << 0)
#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET 28
#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK (0x7 << 28)
#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET 22
#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK (0x7 << 22)
#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET 19
#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK (0x7 << 19)
#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET 16
#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK (0x7 << 16)
#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET 12
#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK (0x7 << 12)
#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET 9
#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET 6
#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET 3
#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK (0x7 << 3)
#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET 0
#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK 0x7
#define MXC_CRMAP_AGPR_IPUPAD_OFFSET 20
#define MXC_CRMAP_AGPR_IPUPAD_MASK (0x7 << 20)
#define MXC_CRMAP_APRA_EL1TEN_OFFSET 29
#define MXC_CRMAP_APRA_SIMEN_OFFSET 24
#define MXC_CRMAP_APRA_UART3DIV_OFFSET 17
#define MXC_CRMAP_APRA_UART3DIV_MASK (0xF << 17)
#define MXC_CRMAP_APRA_UART3EN_OFFSET 16
#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
#define MXC_CRMAP_APRA_MQSPIEN_OFFSET 13
#define MXC_CRMAP_APRA_UART2EN_OFFSET 8
#define MXC_CRMAP_APRA_UART1EN_OFFSET 0
#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET 13
#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK (0x7 << 13)
#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET 9
#define MXC_CRMAP_APRB_SDHC2_DIV_MASK (0xF << 9)
#define MXC_CRMAP_APRB_SDHC2EN_OFFSET 8
#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET 5
#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK (0x7 << 5)
#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET 1
#define MXC_CRMAP_APRB_SDHC1_DIV_MASK (0xF << 1)
#define MXC_CRMAP_APRB_SDHC1EN_OFFSET 0
#define MXC_CRMAP_ACSR_ADS_OFFSET 8
#define MXC_CRMAP_ACSR_ADS (0x1 << 8)
#define MXC_CRMAP_ACSR_ACS 0x1
#define MXC_CRMAP_ADCR_LFDF_0 (0x0 << 8)
#define MXC_CRMAP_ADCR_LFDF_2 (0x1 << 8)
#define MXC_CRMAP_ADCR_LFDF_4 (0x2 << 8)
#define MXC_CRMAP_ADCR_LFDF_8 (0x3 << 8)
#define MXC_CRMAP_ADCR_LFDF_OFFSET 8
#define MXC_CRMAP_ADCR_LFDF_MASK (0x3 << 8)
#define MXC_CRMAP_ADCR_ALT_PLL 0x80
#define MXC_CRMAP_ADCR_DFS_DIVEN 0x20
#define MXC_CRMAP_ADCR_DIV_BYP 0x2
#define MXC_CRMAP_ADCR_VSTAT 0x8
#define MXC_CRMAP_ADCR_TSTAT 0x10
#define MXC_CRMAP_ADCR_DVFS_VCTRL 0x10
#define MXC_CRMAP_ADCR_CLK_ON 0x40
#define MXC_CRMAP_ADFMR_FC_OFFSET 16
#define MXC_CRMAP_ADFMR_FC_MASK (0x1F << 16)
#define MXC_CRMAP_ADFMR_MF_OFFSET 1
#define MXC_CRMAP_ADFMR_MF_MASK (0x3FF << 1)
#define MXC_CRMAP_ADFMR_DFM_CLK_READY 0x1
#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN 0x8000
#define MXC_CRMAP_ACR_CKOHS_HIGH (1 << 18)
#define MXC_CRMAP_ACR_CKOS_HIGH (1 << 16)
#define MXC_CRMAP_ACR_CKOHS_MASK (0x7 << 12)
#define MXC_CRMAP_ACR_CKOHD (1 << 11)
#define MXC_CRMAP_ACR_CKOHDIV_MASK (0xF << 8)
#define MXC_CRMAP_ACR_CKOHDIV_OFFSET 8
#define MXC_CRMAP_ACR_CKOD (1 << 7)
#define MXC_CRMAP_ACR_CKOS_MASK (0x7 << 4)
/* AP Warm reset */
#define MXC_CRMAP_AMCR_SW_AP (1 << 14)
/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT 0x00000001
#define MXC_CRMAP_ACGCR_ACG0_STOP 0x00000003
#define MXC_CRMAP_ACGCR_ACG0_RUN 0x00000007
#define MXC_CRMAP_ACGCR_ACG0_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT 0x00000008
#define MXC_CRMAP_ACGCR_ACG1_STOP 0x00000018
#define MXC_CRMAP_ACGCR_ACG1_RUN 0x00000038
#define MXC_CRMAP_ACGCR_ACG1_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT 0x00000040
#define MXC_CRMAP_ACGCR_ACG2_STOP 0x000000C0
#define MXC_CRMAP_ACGCR_ACG2_RUN 0x000001C0
#define MXC_CRMAP_ACGCR_ACG2_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT 0x00000200
#define MXC_CRMAP_ACGCR_ACG3_STOP 0x00000600
#define MXC_CRMAP_ACGCR_ACG3_RUN 0x00000E00
#define MXC_CRMAP_ACGCR_ACG3_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT 0x00001000
#define MXC_CRMAP_ACGCR_ACG4_STOP 0x00003000
#define MXC_CRMAP_ACGCR_ACG4_RUN 0x00007000
#define MXC_CRMAP_ACGCR_ACG4_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT 0x00010000
#define MXC_CRMAP_ACGCR_ACG5_STOP 0x00030000
#define MXC_CRMAP_ACGCR_ACG5_RUN 0x00070000
#define MXC_CRMAP_ACGCR_ACG5_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT 0x00080000
#define MXC_CRMAP_ACGCR_ACG6_STOP 0x00180000
#define MXC_CRMAP_ACGCR_ACG6_RUN 0x00380000
#define MXC_CRMAP_ACGCR_ACG6_DISABLED 0x00000000
#define NUM_GATE_CTRL 6
/* CRM COM Register Offsets */
#define MXC_CRMCOM_CSCR (MXC_CRM_COM_BASE + 0x0C)
#define MXC_CRMCOM_CCCR (MXC_CRM_COM_BASE + 0x10)
/* CRM COM Bit Definitions */
#define MXC_CRMCOM_CSCR_PPD1 0x08000000
#define MXC_CRMCOM_CSCR_CKOHSEL (1 << 18)
#define MXC_CRMCOM_CSCR_CKOSEL (1 << 17)
#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET 8
#define MXC_CRMCOM_CCCR_CC_DIV_MASK (0x1F << 8)
#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET 0
#define MXC_CRMCOM_CCCR_CC_SEL_MASK 0x3
/* DSM Register Offsets */
#define MXC_DSM_SLEEP_TIME (MXC_DSM_BASE + 0x0c)
#define MXC_DSM_CONTROL0 (MXC_DSM_BASE + 0x20)
#define MXC_DSM_CONTROL1 (MXC_DSM_BASE + 0x24)
#define MXC_DSM_CTREN (MXC_DSM_BASE + 0x28)
#define MXC_DSM_WARM_PER (MXC_DSM_BASE + 0x40)
#define MXC_DSM_LOCK_PER (MXC_DSM_BASE + 0x44)
#define MXC_DSM_MGPER (MXC_DSM_BASE + 0x4c)
#define MXC_DSM_CRM_CONTROL (MXC_DSM_BASE + 0x50)
/* Bit definitions of various registers in DSM */
#define MXC_DSM_CRM_CTRL_DVFS_BYP 0x00000008
#define MXC_DSM_CRM_CTRL_DVFS_VCTRL 0x00000004
#define MXC_DSM_CRM_CTRL_LPMD1 0x00000002
#define MXC_DSM_CRM_CTRL_LPMD0 0x00000001
#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE 0x00000000
#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE 0x00000001
#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE 0x00000003
#define MXC_DSM_CONTROL0_STBY_COMMIT_EN 0x00000200
#define MXC_DSM_CONTROL0_MSTR_EN 0x00000001
#define MXC_DSM_CONTROL0_RESTART 0x00000010
/* Counter Block reset */
#define MXC_DSM_CONTROL1_CB_RST 0x00000002
/* State Machine reset */
#define MXC_DSM_CONTROL1_SM_RST 0x00000004
/* Bit needed to reset counter block */
#define MXC_CONTROL1_RST_CNT32 0x00000008
#define MXC_DSM_CONTROL1_RST_CNT32_EN 0x00000800
#define MXC_DSM_CONTROL1_SLEEP 0x00000100
#define MXC_DSM_CONTROL1_WAKEUP_DISABLE 0x00004000
#define MXC_DSM_CTREN_CNT32 0x00000001
/* Magic Fix enable bit */
#define MXC_DSM_MGPER_EN_MGFX 0x80000000
#define MXC_DSM_MGPER_PER_MASK 0x000003FF
#define MXC_DSM_MGPER_PER(n) (MXC_DSM_MGPER_PER_MASK & n)
/* Address offsets of the CLKCTL registers */
#define MXC_CLKCTL_GP_CTRL (MXC_CLKCTL_BASE + 0x00)
#define MXC_CLKCTL_GP_SER (MXC_CLKCTL_BASE + 0x04)
#define MXC_CLKCTL_GP_CER (MXC_CLKCTL_BASE + 0x08)
#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */

251
arch/arm/mach-mxc91231/devices.c
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@ -1,251 +0,0 @@
/*
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/imx-uart.h>
static struct resource uart0[] = {
{
.start = MXC91231_UART1_BASE_ADDR,
.end = MXC91231_UART1_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_UART1_RX,
.end = MXC91231_INT_UART1_RX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART1_TX,
.end = MXC91231_INT_UART1_TX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART1_MINT,
.end = MXC91231_INT_UART1_MINT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device0 = {
.name = "imx-uart",
.id = 0,
.resource = uart0,
.num_resources = ARRAY_SIZE(uart0),
};
static struct resource uart1[] = {
{
.start = MXC91231_UART2_BASE_ADDR,
.end = MXC91231_UART2_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_UART2_RX,
.end = MXC91231_INT_UART2_RX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART2_TX,
.end = MXC91231_INT_UART2_TX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART2_MINT,
.end = MXC91231_INT_UART2_MINT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device1 = {
.name = "imx-uart",
.id = 1,
.resource = uart1,
.num_resources = ARRAY_SIZE(uart1),
};
static struct resource uart2[] = {
{
.start = MXC91231_UART3_BASE_ADDR,
.end = MXC91231_UART3_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_UART3_RX,
.end = MXC91231_INT_UART3_RX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART3_TX,
.end = MXC91231_INT_UART3_TX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART3_MINT,
.end = MXC91231_INT_UART3_MINT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device2 = {
.name = "imx-uart",
.id = 2,
.resource = uart2,
.num_resources = ARRAY_SIZE(uart2),
};
/* GPIO port description */
static struct mxc_gpio_port mxc_gpio_ports[] = {
[0] = {
.chip.label = "gpio-0",
.base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR),
.irq = MXC91231_INT_GPIO1,
.virtual_irq_start = MXC_GPIO_IRQ_START,
},
[1] = {
.chip.label = "gpio-1",
.base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR),
.irq = MXC91231_INT_GPIO2,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
},
[2] = {
.chip.label = "gpio-2",
.base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR),
.irq = MXC91231_INT_GPIO3,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
},
[3] = {
.chip.label = "gpio-3",
.base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR),
.irq = MXC91231_INT_GPIO4,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
},
};
int __init mxc91231_register_gpios(void)
{
return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
}
static struct resource mxc_nand_resources[] = {
{
.start = MXC91231_NFC_BASE_ADDR,
.end = MXC91231_NFC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM
}, {
.start = MXC91231_INT_NANDFC,
.end = MXC91231_INT_NANDFC,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mxc_nand_device = {
.name = "mxc_nand",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_nand_resources),
.resource = mxc_nand_resources,
};
static struct resource mxc_sdhc0_resources[] = {
{
.start = MXC91231_MMC_SDHC1_BASE_ADDR,
.end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_MMC_SDHC1,
.end = MXC91231_INT_MMC_SDHC1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource mxc_sdhc1_resources[] = {
{
.start = MXC91231_MMC_SDHC2_BASE_ADDR,
.end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_MMC_SDHC2,
.end = MXC91231_INT_MMC_SDHC2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_sdhc_device0 = {
.name = "mxc-mmc",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_sdhc0_resources),
.resource = mxc_sdhc0_resources,
};
struct platform_device mxc_sdhc_device1 = {
.name = "mxc-mmc",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
.resource = mxc_sdhc1_resources,
};
static struct resource mxc_cspi0_resources[] = {
{
.start = MXC91231_CSPI1_BASE_ADDR,
.end = MXC91231_CSPI1_BASE_ADDR + 0x20,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_CSPI1,
.end = MXC91231_INT_CSPI1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_cspi_device0 = {
.name = "spi_imx",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_cspi0_resources),
.resource = mxc_cspi0_resources,
};
static struct resource mxc_cspi1_resources[] = {
{
.start = MXC91231_CSPI2_BASE_ADDR,
.end = MXC91231_CSPI2_BASE_ADDR + 0x20,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_CSPI2,
.end = MXC91231_INT_CSPI2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_cspi_device1 = {
.name = "spi_imx",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_cspi1_resources),
.resource = mxc_cspi1_resources,
};
static struct resource mxc_wdog0_resources[] = {
{
.start = MXC91231_WDOG1_BASE_ADDR,
.end = MXC91231_WDOG1_BASE_ADDR + 0x10,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_wdog_device0 = {
.name = "mxc-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_wdog0_resources),
.resource = mxc_wdog0_resources,
};

13
arch/arm/mach-mxc91231/devices.h
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@ -1,13 +0,0 @@
extern struct platform_device mxc_uart_device0;
extern struct platform_device mxc_uart_device1;
extern struct platform_device mxc_uart_device2;
extern struct platform_device mxc_nand_device;
extern struct platform_device mxc_sdhc_device0;
extern struct platform_device mxc_sdhc_device1;
extern struct platform_device mxc_cspi_device0;
extern struct platform_device mxc_cspi_device1;
extern struct platform_device mxc_wdog_device0;

177
arch/arm/mach-mxc91231/iomux.c
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@ -1,177 +0,0 @@
/*
* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/iomux-mxc91231.h>
/*
* IOMUX register (base) addresses
*/
#define IOMUX_AP_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR)
#define IOMUX_COM_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR)
#define IOMUXSW_AP_MUX_CTL (IOMUX_AP_BASE + 0x000)
#define IOMUXSW_SP_MUX_CTL (IOMUX_COM_BASE + 0x000)
#define IOMUXSW_PAD_CTL (IOMUX_COM_BASE + 0x200)
#define IOMUXINT_OBS1 (IOMUX_AP_BASE + 0x600)
#define IOMUXINT_OBS2 (IOMUX_AP_BASE + 0x004)
static DEFINE_SPINLOCK(gpio_mux_lock);
#define NB_PORTS ((PIN_MAX + 32) / 32)
#define PIN_GLOBAL_NUM(pin) \
(((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \
((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 + \
((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT))
unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
/*
* set the mode for a IOMUX pin.
*/
int mxc_iomux_mode(unsigned int pin_mode)
{
u32 side, field, l, mode, ret = 0;
void __iomem *reg;
side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT;
switch (side) {
case MUX_SIDE_AP:
reg = IOMUXSW_AP_MUX_CTL;
break;
case MUX_SIDE_SP:
reg = IOMUXSW_SP_MUX_CTL;
break;
default:
return -EINVAL;
}
reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4;
field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT;
mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
spin_lock(&gpio_mux_lock);
l = __raw_readl(reg);
l &= ~(0xff << (field * 8));
l |= mode << (field * 8);
__raw_writel(l, reg);
spin_unlock(&gpio_mux_lock);
return ret;
}
EXPORT_SYMBOL(mxc_iomux_mode);
/*
* This function configures the pad value for a IOMUX pin.
*/
void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
{
u32 padgrp, field, l;
void __iomem *reg;
padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT;
reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
field = (pin + 2) % 3;
pr_debug("%s: reg offset = 0x%x, field = %d\n",
__func__, (pin + 2) / 3, field);
spin_lock(&gpio_mux_lock);
l = __raw_readl(reg);
l &= ~(0x1ff << (field * 10));
l |= config << (field * 10);
__raw_writel(l, reg);
spin_unlock(&gpio_mux_lock);
}
EXPORT_SYMBOL(mxc_iomux_set_pad);
/*
* allocs a single pin:
* - reserves the pin so that it is not claimed by another driver
* - setups the iomux according to the configuration
*/
int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label)
{
unsigned pad = PIN_GLOBAL_NUM(pin_mode);
if (pad >= (PIN_MAX + 1)) {
printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
pad, label ? label : "?");
return -EINVAL;
}
if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
pad, label ? label : "?");
return -EBUSY;
}
mxc_iomux_mode(pin_mode);
return 0;
}
EXPORT_SYMBOL(mxc_iomux_alloc_pin);
int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
const char *label)
{
const unsigned int *p = pin_list;
int i;
int ret = -EINVAL;
for (i = 0; i < count; i++) {
ret = mxc_iomux_alloc_pin(*p, label);
if (ret)
goto setup_error;
p++;
}
return 0;
setup_error:
mxc_iomux_release_multiple_pins(pin_list, i);
return ret;
}
EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
void mxc_iomux_release_pin(unsigned int pin_mode)
{
unsigned pad = PIN_GLOBAL_NUM(pin_mode);
if (pad < (PIN_MAX + 1))
clear_bit(pad, mxc_pin_alloc_map);
}
EXPORT_SYMBOL(mxc_iomux_release_pin);
void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
{
const unsigned int *p = pin_list;
int i;
for (i = 0; i < count; i++) {
mxc_iomux_release_pin(*p);
p++;
}
}
EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);

62
arch/arm/mach-mxc91231/magx-zn5.c
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@ -1,62 +0,0 @@
/*
* Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
*
* This file is released under the GPLv2 or later.
*/
#include <linux/irq.h>
#include <linux/init.h>
#include <linux/device.h>
#include <asm/mach-types.h>
#include <asm/mach/time.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mxc91231.h>
#include <mach/mmc.h>
#include <mach/imx-uart.h>
#include "devices.h"
static struct imxuart_platform_data uart_pdata = {
};
static struct imxmmc_platform_data sdhc_pdata = {
};
static void __init zn5_init(void)
{
pm_power_off = mxc91231_power_off;
mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx");
mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx");
mxc_register_device(&mxc_uart_device1, &uart_pdata);
mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
mxc_register_device(&mxc_wdog_device0, NULL);
return;
}
static void __init zn5_timer_init(void)
{
mxc91231_clocks_init(26000000); /* 26mhz ckih */
}
struct sys_timer zn5_timer = {
.init = zn5_timer_init,
};
MACHINE_START(MAGX_ZN5, "Motorola Zn5")
.boot_params = MXC91231_PHYS_OFFSET + 0x100,
.map_io = mxc91231_map_io,
.init_early = mxc91231_init_early,
.init_irq = mxc91231_init_irq,
.timer = &zn5_timer,
.init_machine = zn5_init,
MACHINE_END

62
arch/arm/mach-mxc91231/mm.c
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@ -1,62 +0,0 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MXC specific definitions
* Copyright 2006 Motorola, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
/*
* This structure defines the MXC memory map.
*/
static struct map_desc mxc91231_io_desc[] __initdata = {
imx_map_entry(MXC91231, L2CC, MT_DEVICE),
imx_map_entry(MXC91231, X_MEMC, MT_DEVICE),
imx_map_entry(MXC91231, ROMP, MT_DEVICE),
imx_map_entry(MXC91231, AVIC, MT_DEVICE),
imx_map_entry(MXC91231, AIPS1, MT_DEVICE),
imx_map_entry(MXC91231, SPBA0, MT_DEVICE),
imx_map_entry(MXC91231, SPBA1, MT_DEVICE),
imx_map_entry(MXC91231, AIPS2, MT_DEVICE),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory map for
* the IO modules.
*/
void __init mxc91231_map_io(void)
{
iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
}
void __init mxc91231_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MXC91231);
}
int mxc91231_register_gpios(void);
void __init mxc91231_init_irq(void)
{
mxc91231_register_gpios();
mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
}

51
arch/arm/mach-mxc91231/system.c
View file

@ -1,51 +0,0 @@
/*
* Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
*
* This file is released under the GPLv2 or later.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/proc-fns.h>
#include <mach/hardware.h>
#include "crm_regs.h"
#define WDOG_WCR MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR)
#define WDOG_WCR_OUT_ENABLE (1 << 6)
#define WDOG_WCR_ASSERT (1 << 5)
void mxc91231_power_off(void)
{
u16 wcr;
wcr = __raw_readw(WDOG_WCR);
wcr |= WDOG_WCR_OUT_ENABLE;
wcr &= ~WDOG_WCR_ASSERT;
__raw_writew(wcr, WDOG_WCR);
}
void mxc91231_arch_reset(char mode, const char *cmd)
{
u32 amcr;
/* Reset the AP using CRM */
amcr = __raw_readl(MXC_CRMAP_AMCR);
amcr &= ~MXC_CRMAP_AMCR_SW_AP;
__raw_writel(amcr, MXC_CRMAP_AMCR);
mdelay(10);
cpu_reset(0);
}
void mxc91231_prepare_idle(void)
{
u32 crm_ctl;
/* Go to WAIT mode after WFI */
crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL);
crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1);
crm_ctl |= MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE;
__raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL);
}

2
arch/arm/mach-mxs/Kconfig
View file

@ -24,7 +24,6 @@ config MACH_MX23EVK
select MXS_HAVE_PLATFORM_AUART
select MXS_HAVE_PLATFORM_MXS_MMC
select MXS_HAVE_PLATFORM_MXSFB
default y
help
Include support for MX23EVK platform. This includes specific
configurations for the board and its peripherals.
@ -39,7 +38,6 @@ config MACH_MX28EVK
select MXS_HAVE_PLATFORM_MXS_MMC
select MXS_HAVE_PLATFORM_MXSFB
select MXS_OCOTP
default y
help
Include support for MX28EVK platform. This includes specific
configurations for the board and its peripherals.

2
arch/arm/mach-mxs/clock-mx23.c
View file

@ -446,6 +446,8 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("rtc", NULL, rtc_clk)
_REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
_REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
_REGISTER_CLOCK("mxs-mmc.0", NULL, ssp_clk)
_REGISTER_CLOCK("mxs-mmc.1", NULL, ssp_clk)
_REGISTER_CLOCK(NULL, "usb", usb_clk)
_REGISTER_CLOCK(NULL, "audio", audio_clk)
_REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)

2
arch/arm/mach-mxs/devices-mx28.h
View file

@ -34,7 +34,7 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
#define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata)
#define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata)
extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst;

5
arch/arm/mach-mxs/devices/platform-mxs-i2c.c
View file

@ -22,13 +22,14 @@
[_id] = mxs_i2c_data_entry_single(soc, _id)
#ifdef CONFIG_SOC_IMX28
const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
mxs_i2c_data_entry(MX28, 0),
mxs_i2c_data_entry(MX28, 1),
};
#endif
struct platform_device *__init mxs_add_mxs_i2c(const struct mxs_i2c_data *data)
struct platform_device *__init mxs_add_mxs_i2c(
const struct mxs_mxs_i2c_data *data)
{
struct resource res[] = {
{

5
arch/arm/mach-mxs/include/mach/devices-common.h
View file

@ -65,13 +65,14 @@ struct platform_device *__init mxs_add_flexcan(
const struct flexcan_platform_data *pdata);
/* i2c */
struct mxs_i2c_data {
struct mxs_mxs_i2c_data {
int id;
resource_size_t iobase;
resource_size_t errirq;
resource_size_t dmairq;
};
struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data);
struct platform_device * __init mxs_add_mxs_i2c(
const struct mxs_mxs_i2c_data *data);
/* mmc */
#include <mach/mmc.h>

2
arch/arm/mach-mxs/include/mach/mx23.h
View file

@ -57,7 +57,7 @@
#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000)
#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000)
#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000)
#define MX23_I2C0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000)
#define MX23_I2C_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000)
#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000)
#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000)
#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000)

2
arch/arm/mach-mxs/mach-mx23evk.c
View file

@ -148,7 +148,7 @@ static void __init mx23evk_init(void)
mx23_add_auart0();
/* power on mmc slot by writing 0 to the gpio */
ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT,
ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
"mmc0-slot-power");
if (ret)
pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);

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