From 5a8095e9d02da19f3bab738e82c0520ecd62d6af Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 11 Sep 2012 11:01:59 -0500 Subject: [PATCH 01/71] ARM: dts: Add omap3-beagle.dts Add a minimal dts for original OMAP3430/3530 version of the Beagle board. This version of the Beagle board has 256MB of DDR and features the same TWL4030 power management IC (PMIC) as the Beagle board XM. Given that the Beagle and Beagle-XM boards use the same PMIC, move the definition of the VSIM regulator into the TWL4030.dtsi file so that we do not need to duplicate in the Beagle board dts file. This has been boot tested on an OMAP3530 Beagle board and verifing that the SD/MMC interface is working with a SD card. V2 changes - Rebased upon of devel-dt - Corrected copyright date in omap3-beagle.dts file - Added LED support after verifing that Beagle and Beagle XM have the same LED configuration Signed-off-by: Jon Hunter Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/omap3-beagle-xm.dts | 6 --- arch/arm/boot/dts/omap3-beagle.dts | 67 +++++++++++++++++++++++++++ arch/arm/boot/dts/twl4030.dtsi | 6 +++ 4 files changed, 74 insertions(+), 6 deletions(-) create mode 100644 arch/arm/boot/dts/omap3-beagle.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f37cf9fa5fa0..e69c921d44a2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx28-m28evk.dtb \ imx28-tx28.dtb dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ + omap3-beagle.dtb \ omap3-beagle-xm.dtb \ omap3-evm.dtb \ omap3-tobi.dtb \ diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index c38cf76df81f..3705a81c1fc2 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -55,12 +55,6 @@ interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; - vsim: regulator-vsim { - compatible = "ti,twl4030-vsim"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - twl_audio: audio { compatible = "ti,twl4030-audio"; codec { diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts new file mode 100644 index 000000000000..f624dc85d441 --- /dev/null +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +/ { + model = "TI OMAP3 BeagleBoard"; + compatible = "ti,omap3-beagle", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + leds { + compatible = "gpio-leds"; + pmu_stat { + label = "beagleboard::pmu_stat"; + gpios = <&twl_gpio 19 0>; /* LEDB */ + }; + + heartbeat { + label = "beagleboard::usr0"; + gpios = <&gpio5 22 0>; /* 150 -> D6 LED */ + linux,default-trigger = "heartbeat"; + }; + + mmc { + label = "beagleboard::usr1"; + gpios = <&gpio5 21 0>; /* 149 -> D7 LED */ + linux,default-trigger = "mmc0"; + }; + }; + +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +/include/ "twl4030.dtsi" + +&mmc1 { + vmmc-supply = <&vmmc1>; + vmmc_aux-supply = <&vsim>; + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index ff000172c93c..c5337d4d073c 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi @@ -37,6 +37,12 @@ regulator-max-microvolt = <3150000>; }; + vsim: regulator-vsim { + compatible = "ti,twl4030-vsim"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + twl_gpio: gpio { compatible = "ti,twl4030-gpio"; gpio-controller; From efeedcf2a9137c9be0b833cb76b05315fe231197 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Fri, 31 Aug 2012 15:07:20 +0530 Subject: [PATCH 02/71] ARM: dts: AM33XX: Add device tree OPP table Add DT OPP table for AM33XX family of devices. This data is decoded by OF with of_init_opp_table() helper function. Also adds cpu0 supply name to the corresponding dts files. cpu0-supply name is used by cpufreq-cpu0 driver to get the regulator pointer for voltage modifications. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone.dts | 6 ++++++ arch/arm/boot/dts/am335x-evm.dts | 6 ++++++ arch/arm/boot/dts/am33xx.dtsi | 15 +++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index c634f87e230e..91eee97371ea 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -13,6 +13,12 @@ model = "TI AM335x BeagleBone"; compatible = "ti,am335x-bone", "ti,am33xx"; + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 185d6325a458..4707cda9e4fe 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -13,6 +13,12 @@ model = "TI AM335x EVM"; compatible = "ti,am335x-evm", "ti,am33xx"; + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index bb31bff01998..b4e3e4793b95 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -25,6 +25,21 @@ cpus { cpu@0 { compatible = "arm,cortex-a8"; + + /* + * To consider voltage drop between PMIC and SoC, + * tolerance value is reduced to 2% from 4% and + * voltage value is increased as a precaution. + */ + operating-points = < + /* kHz uV */ + 720000 1285000 + 600000 1225000 + 500000 1125000 + 275000 1125000 + >; + voltage-tolerance = <2>; /* 2 percentage */ + clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; From b552dfc44bf4a34196b949bc81e937de461f4898 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Thu, 20 Sep 2012 02:49:26 +0530 Subject: [PATCH 03/71] ARM: dts: AM33XX: Add basic pinctrl device tree data Adds basic pinctrl device tree data for AM33XX family of devices. This patch is based on the pinctrl-single driver. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index b4e3e4793b95..894fec6d9ef6 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -55,6 +55,15 @@ }; }; + am33xx_pinmux: pinmux@44e10800 { + compatible = "pinctrl-single"; + reg = <0x44e10800 0x0238>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + }; + /* * XXX: Use a flat representation of the AM33XX interconnect. * The real AM33XX interconnect network is quite complex.Since From 059b185d5345825519ee9fd4afcb349856c34363 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Thu, 20 Sep 2012 02:49:27 +0530 Subject: [PATCH 04/71] ARM: dts: AM33XX: Add D_CAN device tree data Add Bosch D_CAN controller device tree data to AM33XX dtsi file by adding d_can device nodes with all the necessary parameters. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 894fec6d9ef6..64c2efe3be92 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -234,5 +234,23 @@ interrupt-parent = <&intc>; interrupts = <91>; }; + + dcan0: d_can@481cc000 { + compatible = "bosch,d_can"; + ti,hwmods = "d_can0"; + reg = <0x481cc000 0x2000>; + interrupts = <52>; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + dcan1: d_can@481d0000 { + compatible = "bosch,d_can"; + ti,hwmods = "d_can1"; + reg = <0x481d0000 0x2000>; + interrupts = <55>; + interrupt-parent = <&intc>; + status = "disabled"; + }; }; }; From 492dd024e49e92c9bdbaa9c9b5564f1a505687a0 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Thu, 20 Sep 2012 02:49:29 +0530 Subject: [PATCH 05/71] ARM: dts: AM33XX: Add lis331dlh device tree data to am335x-evm Add lis331dlh device tree data to am335x-evm.dts. In AM335x EVM lis331dlh accelerometer is connected to I2C2 bus. So this patch change the status of I2C2 node to "okay" to use I2C2 bus. Also added all the required platform data to am335x-evm. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evm.dts | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 4707cda9e4fe..d25d1b3b58ac 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -37,6 +37,39 @@ reg = <0x2d>; }; }; + + i2c2: i2c@4802a000 { + status = "okay"; + clock-frequency = <400000>; + + lis331dlh: lis331dlh@18 { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x18>; + Vdd-supply = <&lis3_reg>; + Vdd_IO-supply = <&lis3_reg>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; + }; }; vbat: fixedregulator@0 { @@ -46,6 +79,12 @@ regulator-max-microvolt = <5000000>; regulator-boot-on; }; + + lis3_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "lis3_reg"; + regulator-boot-on; + }; }; /include/ "tps65910.dtsi" From bf078553e049b8874d3e26fc36e1e2cc14614187 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Thu, 20 Sep 2012 02:49:30 +0530 Subject: [PATCH 06/71] ARM: dts: AM33XX: Add temperature sensor device tree data to am335x-evm Add temperature sensor DT data to am335x-evm.dts. In AM335x EVM tmp275 temperature sensor is connected to I2C2 bus. So this patch adds child node inside i2c2 node with i2c slave address. This patch is tested on AM335x EVM. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evm.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index d25d1b3b58ac..a5c4c62530a4 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -69,6 +69,11 @@ st,max-limit-y = <550>; st,max-limit-z = <750>; }; + + tmp275: tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; }; }; From cd5cfac26d00b4e00f785ee22dc54fb3ea203f6f Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Fri, 21 Sep 2012 21:19:11 +0530 Subject: [PATCH 07/71] ARM: dts: AM33XX: Add tsl2550 ambient light sensor DT data In AM335x EVM tsl2550 ambient light sensor is connected to I2C2 bus. Add child node inside i2c2 node with i2c slave address. TAOS tsl2550 sensor is using a two-wire SMBus serial interface. Reduce I2C2 clock frequency to 100kHz from 400kHz because the maximum clock frequency of SMBus is 100kHz. Signed-off-by: AnilKumar Ch [b-cousson@ti.com: Clean the changelog] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evm.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index a5c4c62530a4..513284fc66b9 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -40,7 +40,7 @@ i2c2: i2c@4802a000 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; lis331dlh: lis331dlh@18 { compatible = "st,lis331dlh", "st,lis3lv02d"; @@ -70,6 +70,11 @@ st,max-limit-z = <750>; }; + tsl2550: tsl2550@39 { + compatible = "taos,tsl2550"; + reg = <0x39>; + }; + tmp275: tmp275@48 { compatible = "ti,tmp275"; reg = <0x48>; From 571ccb280a73dc39a5571f90ca5b845539d63950 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Mon, 15 Oct 2012 18:05:39 +0530 Subject: [PATCH 08/71] ARM: dts: Add am335x-evmsk.dts Add AM335X EVM-SK device tree source (am335x-sk.dts) file to use the am33xx.dtsi SoC file, along with the memory node information. Also adds support for tps65910 regulator and lis331dlh accelerometer. Following drivers/functionality were tested on AM335x-EVM-SK. * I2C * TPS65910 regulators * lis331dlh accelerometer AM335x EVM Starter Kit details can be accessed from: http://www.ti.com/tool/tmdssk3358 Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evmsk.dts | 166 +++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-evmsk.dts diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts new file mode 100644 index 000000000000..6f5387987865 --- /dev/null +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * AM335x Starter Kit + * http://www.ti.com/tool/tmdssk3358 + */ + +/dts-v1/; + +/include/ "am33xx.dtsi" + +/ { + model = "TI AM335x EVM-SK"; + compatible = "ti,am335x-evmsk", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + ocp { + uart1: serial@44e09000 { + status = "okay"; + }; + + i2c1: i2c@44e0b000 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + + lis331dlh: lis331dlh@18 { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x18>; + Vdd-supply = <&lis3_reg>; + Vdd_IO-supply = <&lis3_reg>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; + }; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + lis3_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "lis3_reg"; + regulator-boot-on; + }; +}; + +/include/ "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-always-on; + }; + }; +}; From 1c48ddbaa61aa017fefacac1bce233227933d18e Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Fri, 19 Oct 2012 12:28:56 +0530 Subject: [PATCH 09/71] Documentation: dt: i2c: Update trivial-devices list Update i2c trivial-devices list by adding the description for ti,tmp275 temperature sensor and taos,tsl2550 ambient light sensor. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- Documentation/devicetree/bindings/i2c/trivial-devices.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index 2f5322b119eb..446859fcdca4 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -55,5 +55,7 @@ st-micro,24c256 i2c serial eeprom (24cxx) stm,m41t00 Serial Access TIMEKEEPER stm,m41t62 Serial real-time clock (RTC) with alarm stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS +taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface ti,tsc2003 I2C Touch-Screen Controller ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface +ti,tmp275 Digital Temperature Sensor From 6ff862f6a8bd54184f81fa36b9231b641607d2c0 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 19 Sep 2012 15:02:06 +0530 Subject: [PATCH 10/71] ARM: dts: Add twl6030-usb data Add twl6030-usb data node in twl6030 device tree file. twl6030-usb is the comparator driver for USB that detects VBUS and ID events. The dt data is comprised of two interrupts, one for ID and one for VBUS and a phandle to the regulator. Acked-by: Felipe Balbi Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4-panda.dts | 4 ++++ arch/arm/boot/dts/omap4-sdp.dts | 4 ++++ arch/arm/boot/dts/twl6030.dtsi | 5 +++++ 3 files changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index e8f927cbb376..32baf65a7ea2 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts @@ -184,3 +184,7 @@ &dmic { status = "disabled"; }; + +&twl_usb_comparator { + usb-supply = <&vusb>; +}; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 5b7e04fbff50..0f57bdf7c2df 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -406,3 +406,7 @@ &mcbsp3 { status = "disabled"; }; + +&twl_usb_comparator { + usb-supply = <&vusb>; +}; diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi index 123e2c40218a..9996cfc5ee80 100644 --- a/arch/arm/boot/dts/twl6030.dtsi +++ b/arch/arm/boot/dts/twl6030.dtsi @@ -86,4 +86,9 @@ clk32kg: regulator-clk32kg { compatible = "ti,twl6030-clk32kg"; }; + + twl_usb_comparator: usb-comparator { + compatible = "ti,twl6030-usb"; + interrupts = <4>, <10>; + }; }; From c8de91a24d66507f7ed81d4077c27014d91ed4c6 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 19 Sep 2012 15:02:07 +0530 Subject: [PATCH 11/71] ARM: dts: Add twl4030-usb data Add twl4030-usb data node in twl4030 device tree file. twl4030-usb is the phy driver for MUSB used in omap3 chipsets. The dt data is comprised of two interrupts, one for ID and one for VBUS and three phandles to regulator. Acked-by: Felipe Balbi Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/twl4030.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index c5337d4d073c..63411b036932 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi @@ -37,6 +37,18 @@ regulator-max-microvolt = <3150000>; }; + vusb1v5: regulator-vusb1v5 { + compatible = "ti,twl4030-vusb1v5"; + }; + + vusb1v8: regulator-vusb1v8 { + compatible = "ti,twl4030-vusb1v8"; + }; + + vusb3v1: regulator-vusb3v1 { + compatible = "ti,twl4030-vusb3v1"; + }; + vsim: regulator-vsim { compatible = "ti,twl4030-vsim"; regulator-min-microvolt = <1800000>; @@ -50,4 +62,13 @@ interrupt-controller; #interrupt-cells = <1>; }; + + twl4030-usb { + compatible = "ti,twl4030-usb"; + interrupts = <10>, <4>; + usb1v5-supply = <&vusb1v5>; + usb1v8-supply = <&vusb1v8>; + usb3v1-supply = <&vusb3v1>; + usb_mode = <1>; + }; }; From 3ce0a99cd4c23762441f0efb18c0e0ef1e9d8bfc Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 19 Sep 2012 16:02:51 +0530 Subject: [PATCH 12/71] ARM: dts: OMAP4: add *reg* property for ocp2scp *reg* property for ocp2scp was previously obtained from ti,hwmods property. But that is now explicitly added to the dt node. Also updated the documentation with *reg* info. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson --- .../devicetree/bindings/bus/omap-ocp2scp.txt | 18 ++++++++++++++++++ arch/arm/boot/dts/omap4.dtsi | 3 ++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt index d2fe064a828b..63dd8051521c 100644 --- a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt +++ b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt @@ -2,9 +2,27 @@ properties: - compatible : Should be "ti,omap-ocp2scp" +- reg : Address and length of the register set for the device - #address-cells, #size-cells : Must be present if the device has sub-nodes - ranges : the child address space are mapped 1:1 onto the parent address space - ti,hwmods : must be "ocp2scp_usb_phy" Sub-nodes: All the devices connected to ocp2scp are described using sub-node to ocp2scp + +ocp2scp@4a0ad000 { + compatible = "ti,omap-ocp2scp"; + reg = <0x4a0ad000 0x1f>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "ocp2scp_usb_phy"; + + subnode1 { + ... + }; + + subnode2 { + ... + }; +}; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 3883f94fdbd0..812461efdea6 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -431,8 +431,9 @@ hw-caps-temp-alert; }; - ocp2scp { + ocp2scp@4a0ad000 { compatible = "ti,omap-ocp2scp"; + reg = <0x4a0ad000 0x1f>; #address-cells = <1>; #size-cells = <1>; ranges; From 4c94ac29b5c1f0cef2281df97609f2cbcc09cf9c Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Wed, 24 Oct 2012 10:47:52 +0200 Subject: [PATCH 13/71] ARM: dts: OMAP: Move interrupt-parent to the root node to avoid duplication The interrupt-parent attribute does not have to be added in each node since the fmwk will check for the parent as well to get it. Create an interrupt-parent for OMAP2, OMAP3, AM33xx and remove the attributes from every nodes that were using it. Signed-off-by: Benoit Cousson Cc: Vaibhav Hiremath Cc: Peter Ujfalusi Cc: Sebastien Guiriec --- arch/arm/boot/dts/am33xx.dtsi | 17 +---------------- arch/arm/boot/dts/omap2.dtsi | 1 + arch/arm/boot/dts/omap2420.dtsi | 2 -- arch/arm/boot/dts/omap2430.dtsi | 5 ----- arch/arm/boot/dts/omap3.dtsi | 6 +----- arch/arm/boot/dts/omap4.dtsi | 6 ------ arch/arm/boot/dts/omap5.dtsi | 5 ----- 7 files changed, 3 insertions(+), 39 deletions(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 64c2efe3be92..470926946ed6 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -12,6 +12,7 @@ / { compatible = "ti,am33xx"; + interrupt-parent = <&intc>; aliases { serial0 = &uart1; @@ -94,7 +95,6 @@ interrupt-controller; #interrupt-cells = <1>; reg = <0x44e07000 0x1000>; - interrupt-parent = <&intc>; interrupts = <96>; }; @@ -106,7 +106,6 @@ interrupt-controller; #interrupt-cells = <1>; reg = <0x4804c000 0x1000>; - interrupt-parent = <&intc>; interrupts = <98>; }; @@ -118,7 +117,6 @@ interrupt-controller; #interrupt-cells = <1>; reg = <0x481ac000 0x1000>; - interrupt-parent = <&intc>; interrupts = <32>; }; @@ -130,7 +128,6 @@ interrupt-controller; #interrupt-cells = <1>; reg = <0x481ae000 0x1000>; - interrupt-parent = <&intc>; interrupts = <62>; }; @@ -139,7 +136,6 @@ ti,hwmods = "uart1"; clock-frequency = <48000000>; reg = <0x44e09000 0x2000>; - interrupt-parent = <&intc>; interrupts = <72>; status = "disabled"; }; @@ -149,7 +145,6 @@ ti,hwmods = "uart2"; clock-frequency = <48000000>; reg = <0x48022000 0x2000>; - interrupt-parent = <&intc>; interrupts = <73>; status = "disabled"; }; @@ -159,7 +154,6 @@ ti,hwmods = "uart3"; clock-frequency = <48000000>; reg = <0x48024000 0x2000>; - interrupt-parent = <&intc>; interrupts = <74>; status = "disabled"; }; @@ -169,7 +163,6 @@ ti,hwmods = "uart4"; clock-frequency = <48000000>; reg = <0x481a6000 0x2000>; - interrupt-parent = <&intc>; interrupts = <44>; status = "disabled"; }; @@ -179,7 +172,6 @@ ti,hwmods = "uart5"; clock-frequency = <48000000>; reg = <0x481a8000 0x2000>; - interrupt-parent = <&intc>; interrupts = <45>; status = "disabled"; }; @@ -189,7 +181,6 @@ ti,hwmods = "uart6"; clock-frequency = <48000000>; reg = <0x481aa000 0x2000>; - interrupt-parent = <&intc>; interrupts = <46>; status = "disabled"; }; @@ -200,7 +191,6 @@ #size-cells = <0>; ti,hwmods = "i2c1"; reg = <0x44e0b000 0x1000>; - interrupt-parent = <&intc>; interrupts = <70>; status = "disabled"; }; @@ -211,7 +201,6 @@ #size-cells = <0>; ti,hwmods = "i2c2"; reg = <0x4802a000 0x1000>; - interrupt-parent = <&intc>; interrupts = <71>; status = "disabled"; }; @@ -222,7 +211,6 @@ #size-cells = <0>; ti,hwmods = "i2c3"; reg = <0x4819c000 0x1000>; - interrupt-parent = <&intc>; interrupts = <30>; status = "disabled"; }; @@ -231,7 +219,6 @@ compatible = "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; reg = <0x44e35000 0x1000>; - interrupt-parent = <&intc>; interrupts = <91>; }; @@ -240,7 +227,6 @@ ti,hwmods = "d_can0"; reg = <0x481cc000 0x2000>; interrupts = <52>; - interrupt-parent = <&intc>; status = "disabled"; }; @@ -249,7 +235,6 @@ ti,hwmods = "d_can1"; reg = <0x481d0000 0x2000>; interrupts = <55>; - interrupt-parent = <&intc>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index 581cb081cb0f..f366482216c0 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -12,6 +12,7 @@ / { compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; + interrupt-parent = <&intc>; aliases { serial0 = &uart1; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index bfd76b4a0ddc..4d5ce91416c3 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -30,7 +30,6 @@ interrupts = <59>, /* TX interrupt */ <60>; /* RX interrupt */ interrupt-names = "tx", "rx"; - interrupt-parent = <&intc>; ti,hwmods = "mcbsp1"; }; @@ -41,7 +40,6 @@ interrupts = <62>, /* TX interrupt */ <63>; /* RX interrupt */ interrupt-names = "tx", "rx"; - interrupt-parent = <&intc>; ti,hwmods = "mcbsp2"; }; }; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 4565d9750f4d..fa845324b642 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -32,7 +32,6 @@ <60>, /* RX interrupt */ <61>; /* RX overflow interrupt */ interrupt-names = "common", "tx", "rx", "rx_overflow"; - interrupt-parent = <&intc>; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; }; @@ -45,7 +44,6 @@ <62>, /* TX interrupt */ <63>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; - interrupt-parent = <&intc>; ti,buffer-size = <128>; ti,hwmods = "mcbsp2"; }; @@ -58,7 +56,6 @@ <89>, /* TX interrupt */ <90>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; - interrupt-parent = <&intc>; ti,buffer-size = <128>; ti,hwmods = "mcbsp3"; }; @@ -71,7 +68,6 @@ <54>, /* TX interrupt */ <55>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; - interrupt-parent = <&intc>; ti,buffer-size = <128>; ti,hwmods = "mcbsp4"; }; @@ -84,7 +80,6 @@ <81>, /* TX interrupt */ <82>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; - interrupt-parent = <&intc>; ti,buffer-size = <128>; ti,hwmods = "mcbsp5"; }; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 696e929d0304..fa155418eaad 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -12,6 +12,7 @@ / { compatible = "ti,omap3430", "ti,omap3"; + interrupt-parent = <&intc>; aliases { serial0 = &uart1; @@ -240,7 +241,6 @@ <59>, /* TX interrupt */ <60>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; - interrupt-parent = <&intc>; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; }; @@ -255,7 +255,6 @@ <63>, /* RX interrupt */ <4>; /* Sidetone */ interrupt-names = "common", "tx", "rx", "sidetone"; - interrupt-parent = <&intc>; ti,buffer-size = <1280>; ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; }; @@ -270,7 +269,6 @@ <90>, /* RX interrupt */ <5>; /* Sidetone */ interrupt-names = "common", "tx", "rx", "sidetone"; - interrupt-parent = <&intc>; ti,buffer-size = <128>; ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; }; @@ -283,7 +281,6 @@ <54>, /* TX interrupt */ <55>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; - interrupt-parent = <&intc>; ti,buffer-size = <128>; ti,hwmods = "mcbsp4"; }; @@ -296,7 +293,6 @@ <81>, /* TX interrupt */ <82>; /* RX interrupt */ interrupt-names = "common", "tx", "rx"; - interrupt-parent = <&intc>; ti,buffer-size = <128>; ti,hwmods = "mcbsp5"; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 812461efdea6..2ab6e68ccbf7 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -340,7 +340,6 @@ <0x49032000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = <0 112 0x4>; - interrupt-parent = <&gic>; ti,hwmods = "mcpdm"; }; @@ -350,7 +349,6 @@ <0x4902e000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = <0 114 0x4>; - interrupt-parent = <&gic>; ti,hwmods = "dmic"; }; @@ -361,7 +359,6 @@ reg-names = "mpu", "dma"; interrupts = <0 17 0x4>; interrupt-names = "common"; - interrupt-parent = <&gic>; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; }; @@ -373,7 +370,6 @@ reg-names = "mpu", "dma"; interrupts = <0 22 0x4>; interrupt-names = "common"; - interrupt-parent = <&gic>; ti,buffer-size = <128>; ti,hwmods = "mcbsp2"; }; @@ -385,7 +381,6 @@ reg-names = "mpu", "dma"; interrupts = <0 23 0x4>; interrupt-names = "common"; - interrupt-parent = <&gic>; ti,buffer-size = <128>; ti,hwmods = "mcbsp3"; }; @@ -396,7 +391,6 @@ reg-names = "mpu"; interrupts = <0 16 0x4>; interrupt-names = "common"; - interrupt-parent = <&gic>; ti,buffer-size = <128>; ti,hwmods = "mcbsp4"; }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 42c78beb4fdc..61a4f2ea7d3c 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -287,7 +287,6 @@ <0x49032000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = <0 112 0x4>; - interrupt-parent = <&gic>; ti,hwmods = "mcpdm"; }; @@ -297,7 +296,6 @@ <0x4902e000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = <0 114 0x4>; - interrupt-parent = <&gic>; ti,hwmods = "dmic"; }; @@ -308,7 +306,6 @@ reg-names = "mpu", "dma"; interrupts = <0 17 0x4>; interrupt-names = "common"; - interrupt-parent = <&gic>; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; }; @@ -320,7 +317,6 @@ reg-names = "mpu", "dma"; interrupts = <0 22 0x4>; interrupt-names = "common"; - interrupt-parent = <&gic>; ti,buffer-size = <128>; ti,hwmods = "mcbsp2"; }; @@ -332,7 +328,6 @@ reg-names = "mpu", "dma"; interrupts = <0 23 0x4>; interrupt-names = "common"; - interrupt-parent = <&gic>; ti,buffer-size = <128>; ti,hwmods = "mcbsp3"; }; From fab8ad0b2b5f2b6d25c6020a61bf3339e53fec61 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 19 Oct 2012 09:59:00 -0500 Subject: [PATCH 14/71] ARM: dts: OMAP: Add timer nodes Add the 12 GP timers nodes present in OMAP2. Add the 12 GP timers nodes present in OMAP3. Add the 11 GP timers nodes present in OMAP4. Add the 7 GP timers nodes present in AM33xx. Add documentation for timer properties specific to OMAP. Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified Vaibhav's original nodes adding information on which timers support a PWM output. V5 changes: - Updated timer register sizes for OMAP2/3/4. - Modified AM335x timer register size to be 1KB instead of 4KB to align with HWMOD. Signed-off-by: Jon Hunter Acked-Reviewed-&-Tested-By: Vaibhav Hiremath Signed-off-by: Benoit Cousson --- .../devicetree/bindings/arm/omap/timer.txt | 31 ++++++ arch/arm/boot/dts/am33xx.dtsi | 54 +++++++++++ arch/arm/boot/dts/omap2.dtsi | 85 +++++++++++++++++ arch/arm/boot/dts/omap2420.dtsi | 8 ++ arch/arm/boot/dts/omap2430.dtsi | 8 ++ arch/arm/boot/dts/omap3.dtsi | 95 +++++++++++++++++++ arch/arm/boot/dts/omap4.dtsi | 86 +++++++++++++++++ 7 files changed, 367 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/timer.txt diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt new file mode 100644 index 000000000000..8732d4d41f8b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/timer.txt @@ -0,0 +1,31 @@ +OMAP Timer bindings + +Required properties: +- compatible: Must be "ti,omap2-timer" for OMAP2+ controllers. +- reg: Contains timer register address range (base address and + length). +- interrupts: Contains the interrupt information for the timer. The + format is being dependent on which interrupt controller + the OMAP device uses. +- ti,hwmods: Name of the hwmod associated to the timer, "timer", + where is the instance number of the timer from the + HW spec. + +Optional properties: +- ti,timer-alwon: Indicates the timer is in an alway-on power domain. +- ti,timer-dsp: Indicates the timer can interrupt the on-chip DSP in + addition to the ARM CPU. +- ti,timer-pwm: Indicates the timer can generate a PWM output. +- ti,timer-secure: Indicates the timer is reserved on a secure OMAP device + and therefore cannot be used by the kernel. + +Example: + +timer12: timer@48304000 { + compatible = "ti,omap2-timer"; + reg = <0x48304000 0x400>; + interrupts = <95>; + ti,hwmods = "timer12" + ti,timer-alwon; + ti,timer-secure; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 470926946ed6..70d24b848c11 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -237,5 +237,59 @@ interrupts = <55>; status = "disabled"; }; + + timer1: timer@44e31000 { + compatible = "ti,omap2-timer"; + reg = <0x44e31000 0x400>; + interrupts = <67>; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; + + timer2: timer@48040000 { + compatible = "ti,omap2-timer"; + reg = <0x48040000 0x400>; + interrupts = <68>; + ti,hwmods = "timer2"; + }; + + timer3: timer@48042000 { + compatible = "ti,omap2-timer"; + reg = <0x48042000 0x400>; + interrupts = <69>; + ti,hwmods = "timer3"; + }; + + timer4: timer@48044000 { + compatible = "ti,omap2-timer"; + reg = <0x48044000 0x400>; + interrupts = <92>; + ti,hwmods = "timer4"; + ti,timer-pwm; + }; + + timer5: timer@48046000 { + compatible = "ti,omap2-timer"; + reg = <0x48046000 0x400>; + interrupts = <93>; + ti,hwmods = "timer5"; + ti,timer-pwm; + }; + + timer6: timer@48048000 { + compatible = "ti,omap2-timer"; + reg = <0x48048000 0x400>; + interrupts = <94>; + ti,hwmods = "timer6"; + ti,timer-pwm; + }; + + timer7: timer@4804a000 { + compatible = "ti,omap2-timer"; + reg = <0x4804a000 0x400>; + interrupts = <95>; + ti,hwmods = "timer7"; + ti,timer-pwm; + }; }; }; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index f366482216c0..761c4b69b25b 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -66,5 +66,90 @@ ti,hwmods = "uart3"; clock-frequency = <48000000>; }; + + timer2: timer@4802a000 { + compatible = "ti,omap2-timer"; + reg = <0x4802a000 0x400>; + interrupts = <38>; + ti,hwmods = "timer2"; + }; + + timer3: timer@48078000 { + compatible = "ti,omap2-timer"; + reg = <0x48078000 0x400>; + interrupts = <39>; + ti,hwmods = "timer3"; + }; + + timer4: timer@4807a000 { + compatible = "ti,omap2-timer"; + reg = <0x4807a000 0x400>; + interrupts = <40>; + ti,hwmods = "timer4"; + }; + + timer5: timer@4807c000 { + compatible = "ti,omap2-timer"; + reg = <0x4807c000 0x400>; + interrupts = <41>; + ti,hwmods = "timer5"; + ti,timer-dsp; + }; + + timer6: timer@4807e000 { + compatible = "ti,omap2-timer"; + reg = <0x4807e000 0x400>; + interrupts = <42>; + ti,hwmods = "timer6"; + ti,timer-dsp; + }; + + timer7: timer@48080000 { + compatible = "ti,omap2-timer"; + reg = <0x48080000 0x400>; + interrupts = <43>; + ti,hwmods = "timer7"; + ti,timer-dsp; + }; + + timer8: timer@48082000 { + compatible = "ti,omap2-timer"; + reg = <0x48082000 0x400>; + interrupts = <44>; + ti,hwmods = "timer8"; + ti,timer-dsp; + }; + + timer9: timer@48084000 { + compatible = "ti,omap2-timer"; + reg = <0x48084000 0x400>; + interrupts = <45>; + ti,hwmods = "timer9"; + ti,timer-pwm; + }; + + timer10: timer@48086000 { + compatible = "ti,omap2-timer"; + reg = <0x48086000 0x400>; + interrupts = <46>; + ti,hwmods = "timer10"; + ti,timer-pwm; + }; + + timer11: timer@48088000 { + compatible = "ti,omap2-timer"; + reg = <0x48088000 0x400>; + interrupts = <47>; + ti,hwmods = "timer11"; + ti,timer-pwm; + }; + + timer12: timer@4808a000 { + compatible = "ti,omap2-timer"; + reg = <0x4808a000 0x400>; + interrupts = <48>; + ti,hwmods = "timer12"; + ti,timer-pwm; + }; }; }; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 4d5ce91416c3..af5ee262d0cf 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -42,5 +42,13 @@ interrupt-names = "tx", "rx"; ti,hwmods = "mcbsp2"; }; + + timer1: timer@48028000 { + compatible = "ti,omap2-timer"; + reg = <0x48028000 0x400>; + interrupts = <37>; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; }; }; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index fa845324b642..688729840f14 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -83,5 +83,13 @@ ti,buffer-size = <128>; ti,hwmods = "mcbsp5"; }; + + timer1: timer@49018000 { + compatible = "ti,omap2-timer"; + reg = <0x49018000 0x400>; + interrupts = <37>; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; }; }; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index fa155418eaad..af9b1822ff84 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -296,5 +296,100 @@ ti,buffer-size = <128>; ti,hwmods = "mcbsp5"; }; + + timer1: timer@48318000 { + compatible = "ti,omap2-timer"; + reg = <0x48318000 0x400>; + interrupts = <37>; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; + + timer2: timer@49032000 { + compatible = "ti,omap2-timer"; + reg = <0x49032000 0x400>; + interrupts = <38>; + ti,hwmods = "timer2"; + }; + + timer3: timer@49034000 { + compatible = "ti,omap2-timer"; + reg = <0x49034000 0x400>; + interrupts = <39>; + ti,hwmods = "timer3"; + }; + + timer4: timer@49036000 { + compatible = "ti,omap2-timer"; + reg = <0x49036000 0x400>; + interrupts = <40>; + ti,hwmods = "timer4"; + }; + + timer5: timer@49038000 { + compatible = "ti,omap2-timer"; + reg = <0x49038000 0x400>; + interrupts = <41>; + ti,hwmods = "timer5"; + ti,timer-dsp; + }; + + timer6: timer@4903a000 { + compatible = "ti,omap2-timer"; + reg = <0x4903a000 0x400>; + interrupts = <42>; + ti,hwmods = "timer6"; + ti,timer-dsp; + }; + + timer7: timer@4903c000 { + compatible = "ti,omap2-timer"; + reg = <0x4903c000 0x400>; + interrupts = <43>; + ti,hwmods = "timer7"; + ti,timer-dsp; + }; + + timer8: timer@4903e000 { + compatible = "ti,omap2-timer"; + reg = <0x4903e000 0x400>; + interrupts = <44>; + ti,hwmods = "timer8"; + ti,timer-pwm; + ti,timer-dsp; + }; + + timer9: timer@49040000 { + compatible = "ti,omap2-timer"; + reg = <0x49040000 0x400>; + interrupts = <45>; + ti,hwmods = "timer9"; + ti,timer-pwm; + }; + + timer10: timer@48086000 { + compatible = "ti,omap2-timer"; + reg = <0x48086000 0x400>; + interrupts = <46>; + ti,hwmods = "timer10"; + ti,timer-pwm; + }; + + timer11: timer@48088000 { + compatible = "ti,omap2-timer"; + reg = <0x48088000 0x400>; + interrupts = <47>; + ti,hwmods = "timer11"; + ti,timer-pwm; + }; + + timer12: timer@48304000 { + compatible = "ti,omap2-timer"; + reg = <0x48304000 0x400>; + interrupts = <95>; + ti,hwmods = "timer12"; + ti,timer-alwon; + ti,timer-secure; + }; }; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 2ab6e68ccbf7..d3a82e0c3804 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -433,5 +433,91 @@ ranges; ti,hwmods = "ocp2scp_usb_phy"; }; + + timer1: timer@4a318000 { + compatible = "ti,omap2-timer"; + reg = <0x4a318000 0x80>; + interrupts = <0 37 0x4>; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; + + timer2: timer@48032000 { + compatible = "ti,omap2-timer"; + reg = <0x48032000 0x80>; + interrupts = <0 38 0x4>; + ti,hwmods = "timer2"; + }; + + timer3: timer@48034000 { + compatible = "ti,omap2-timer"; + reg = <0x48034000 0x80>; + interrupts = <0 39 0x4>; + ti,hwmods = "timer3"; + }; + + timer4: timer@48036000 { + compatible = "ti,omap2-timer"; + reg = <0x48036000 0x80>; + interrupts = <0 40 0x4>; + ti,hwmods = "timer4"; + }; + + timer5: timer@49038000 { + compatible = "ti,omap2-timer"; + reg = <0x49038000 0x80>; + interrupts = <0 41 0x4>; + ti,hwmods = "timer5"; + ti,timer-dsp; + }; + + timer6: timer@4903a000 { + compatible = "ti,omap2-timer"; + reg = <0x4903a000 0x80>; + interrupts = <0 42 0x4>; + ti,hwmods = "timer6"; + ti,timer-dsp; + }; + + timer7: timer@4903c000 { + compatible = "ti,omap2-timer"; + reg = <0x4903c000 0x80>; + interrupts = <0 43 0x4>; + ti,hwmods = "timer7"; + ti,timer-dsp; + }; + + timer8: timer@4903e000 { + compatible = "ti,omap2-timer"; + reg = <0x4903e000 0x80>; + interrupts = <0 44 0x4>; + ti,hwmods = "timer8"; + ti,timer-pwm; + ti,timer-dsp; + }; + + timer9: timer@4803e000 { + compatible = "ti,omap2-timer"; + reg = <0x4803e000 0x80>; + interrupts = <0 45 0x4>; + ti,hwmods = "timer9"; + ti,timer-pwm; + }; + + timer10: timer@48086000 { + compatible = "ti,omap2-timer"; + reg = <0x48086000 0x80>; + interrupts = <0 46 0x4>; + ti,hwmods = "timer10"; + ti,timer-pwm; + }; + + timer11: timer@48088000 { + compatible = "ti,omap2-timer"; + reg = <0x48088000 0x80>; + interrupts = <0 47 0x4>; + ti,hwmods = "timer11"; + ti,timer-pwm; + }; }; }; From 510c0ffdd408ced2654f073d0397f0fec410a235 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 25 Oct 2012 14:24:14 -0500 Subject: [PATCH 15/71] ARM: dts: OMAP: Add counter-32k nodes Adds the counter-32k timers nodes present in OMAP2/3/4 devices and device-tree binding documentation for OMAP counter-32k. Signed-off-by: Jon Hunter Signed-off-by: Benoit Cousson --- .../devicetree/bindings/arm/omap/counter.txt | 15 +++++++++++++++ arch/arm/boot/dts/omap2420.dtsi | 6 ++++++ arch/arm/boot/dts/omap2430.dtsi | 6 ++++++ arch/arm/boot/dts/omap3.dtsi | 6 ++++++ arch/arm/boot/dts/omap4.dtsi | 6 ++++++ 5 files changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/counter.txt diff --git a/Documentation/devicetree/bindings/arm/omap/counter.txt b/Documentation/devicetree/bindings/arm/omap/counter.txt new file mode 100644 index 000000000000..5bd8aa091315 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/counter.txt @@ -0,0 +1,15 @@ +OMAP Counter-32K bindings + +Required properties: +- compatible: Must be "ti,omap-counter32k" for OMAP controllers +- reg: Contains timer register address range (base address and length) +- ti,hwmods: Name of the hwmod associated to the counter, which is typically + "counter_32k" + +Example: + +counter32k: counter@4a304000 { + compatible = "ti,omap-counter32k"; + reg = <0x4a304000 0x20>; + ti,hwmods = "counter_32k"; +}; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index af5ee262d0cf..af6560908905 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -14,6 +14,12 @@ compatible = "ti,omap2420", "ti,omap2"; ocp { + counter32k: counter@48004000 { + compatible = "ti,omap-counter32k"; + reg = <0x48004000 0x20>; + ti,hwmods = "counter_32k"; + }; + omap2420_pmx: pinmux@48000030 { compatible = "ti,omap2420-padconf", "pinctrl-single"; reg = <0x48000030 0x0113>; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 688729840f14..c3924457c9b6 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -14,6 +14,12 @@ compatible = "ti,omap2430", "ti,omap2"; ocp { + counter32k: counter@49020000 { + compatible = "ti,omap-counter32k"; + reg = <0x49020000 0x20>; + ti,hwmods = "counter_32k"; + }; + omap2430_pmx: pinmux@49002030 { compatible = "ti,omap2430-padconf", "pinctrl-single"; reg = <0x49002030 0x0154>; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index af9b1822ff84..1acc26148ffc 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -61,6 +61,12 @@ ranges; ti,hwmods = "l3_main"; + counter32k: counter@48320000 { + compatible = "ti,omap-counter32k"; + reg = <0x48320000 0x20>; + ti,hwmods = "counter_32k"; + }; + intc: interrupt-controller@48200000 { compatible = "ti,omap2-intc"; interrupt-controller; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index d3a82e0c3804..23ee1498c98c 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -95,6 +95,12 @@ ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; + counter32k: counter@4a304000 { + compatible = "ti,omap-counter32k"; + reg = <0x4a304000 0x20>; + ti,hwmods = "counter_32k"; + }; + omap4_pmx_core: pinmux@4a100040 { compatible = "ti,omap4-padconf", "pinctrl-single"; reg = <0x4a100040 0x0196>; From f4b224f2b48e3a5203a25fe64ef46cc5c54e1604 Mon Sep 17 00:00:00 2001 From: Sebastien Guiriec Date: Tue, 23 Oct 2012 10:37:09 +0200 Subject: [PATCH 16/71] ARM: dts: omap5: Update GPIO with address space and interrupts Add base address and interrupt line inside Device Tree data for OMAP5. Signed-off-by: Sebastien Guiriec Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 61a4f2ea7d3c..4cd8acf32c6f 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -104,6 +104,8 @@ gpio1: gpio@4ae10000 { compatible = "ti,omap4-gpio"; + reg = <0x4ae10000 0x200>; + interrupts = <0 29 0x4>; ti,hwmods = "gpio1"; gpio-controller; #gpio-cells = <2>; @@ -113,6 +115,8 @@ gpio2: gpio@48055000 { compatible = "ti,omap4-gpio"; + reg = <0x48055000 0x200>; + interrupts = <0 30 0x4>; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; @@ -122,6 +126,8 @@ gpio3: gpio@48057000 { compatible = "ti,omap4-gpio"; + reg = <0x48057000 0x200>; + interrupts = <0 31 0x4>; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; @@ -131,6 +137,8 @@ gpio4: gpio@48059000 { compatible = "ti,omap4-gpio"; + reg = <0x48059000 0x200>; + interrupts = <0 32 0x4>; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; @@ -140,6 +148,8 @@ gpio5: gpio@4805b000 { compatible = "ti,omap4-gpio"; + reg = <0x4805b000 0x200>; + interrupts = <0 33 0x4>; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; @@ -149,6 +159,8 @@ gpio6: gpio@4805d000 { compatible = "ti,omap4-gpio"; + reg = <0x4805d000 0x200>; + interrupts = <0 34 0x4>; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; @@ -158,6 +170,8 @@ gpio7: gpio@48051000 { compatible = "ti,omap4-gpio"; + reg = <0x48051000 0x200>; + interrupts = <0 35 0x4>; ti,hwmods = "gpio7"; gpio-controller; #gpio-cells = <2>; @@ -167,6 +181,8 @@ gpio8: gpio@48053000 { compatible = "ti,omap4-gpio"; + reg = <0x48053000 0x200>; + interrupts = <0 121 0x4>; ti,hwmods = "gpio8"; gpio-controller; #gpio-cells = <2>; From d7118bbd5095982ddc179387e9fd7d0524fdcf10 Mon Sep 17 00:00:00 2001 From: Sebastien Guiriec Date: Tue, 23 Oct 2012 10:37:10 +0200 Subject: [PATCH 17/71] ARM: dts: omap5: Update I2C with address space and interrupts Add base address and interrupt line inside Device Tree data for OMAP5 Signed-off-by: Sebastien Guiriec Reviewed-by: Shubhrajyoti D Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 4cd8acf32c6f..9abcff75e8b7 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -192,6 +192,8 @@ i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; + reg = <0x48070000 0x100>; + interrupts = <0 56 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -199,6 +201,8 @@ i2c2: i2c@48072000 { compatible = "ti,omap4-i2c"; + reg = <0x48072000 0x100>; + interrupts = <0 57 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -206,20 +210,26 @@ i2c3: i2c@48060000 { compatible = "ti,omap4-i2c"; + reg = <0x48060000 0x100>; + interrupts = <0 61 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; }; - i2c4: i2c@4807A000 { + i2c4: i2c@4807a000 { compatible = "ti,omap4-i2c"; + reg = <0x4807a000 0x100>; + interrupts = <0 62 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; }; - i2c5: i2c@4807C000 { + i2c5: i2c@4807c000 { compatible = "ti,omap4-i2c"; + reg = <0x4807c000 0x100>; + interrupts = <0 60 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c5"; From 8e80f66069d54fd22e1a8e452a760f511f501b48 Mon Sep 17 00:00:00 2001 From: Sebastien Guiriec Date: Tue, 23 Oct 2012 10:37:11 +0200 Subject: [PATCH 18/71] ARM: dts: omap5: Update UART with address space and interrupts Add base address and interrupt line inside Device Tree data for OMAP5. Fix as well the wrong compatible string on UART5 & 6. Signed-off-by: Sebastien Guiriec Reviewed-by: Shubhrajyoti D [b-cousson@ti.com: Update the changelog to reflect the fixes done in the patch] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 9abcff75e8b7..7cc47ad849b3 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -237,36 +237,48 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial@4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; uart5: serial@48066000 { - compatible = "ti,omap5-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48066000 0x100>; + interrupts = <0 105 0x4>; ti,hwmods = "uart5"; clock-frequency = <48000000>; }; uart6: serial@48068000 { - compatible = "ti,omap6-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48068000 0x100>; + interrupts = <0 106 0x4>; ti,hwmods = "uart6"; clock-frequency = <48000000>; }; From 9a6423621df893512fd3aeb0e11ca9015c8fba15 Mon Sep 17 00:00:00 2001 From: Sebastien Guiriec Date: Tue, 23 Oct 2012 10:37:12 +0200 Subject: [PATCH 19/71] ARM: dts: omap5: Update MMC with address space and interrupts Add base address and interrupt line inside Device Tree data for OMAP5. Signed-off-by: Sebastien Guiriec Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 7cc47ad849b3..930dbfe3bcff 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -285,6 +285,8 @@ mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; + reg = <0x4809c000 0x400>; + interrupts = <0 83 0x4>; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; @@ -292,24 +294,32 @@ mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480b4000 0x400>; + interrupts = <0 86 0x4>; ti,hwmods = "mmc2"; ti,needs-special-reset; }; mmc3: mmc@480ad000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480ad000 0x400>; + interrupts = <0 94 0x4>; ti,hwmods = "mmc3"; ti,needs-special-reset; }; mmc4: mmc@480d1000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480d1000 0x400>; + interrupts = <0 96 0x4>; ti,hwmods = "mmc4"; ti,needs-special-reset; }; mmc5: mmc@480d5000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480d5000 0x400>; + interrupts = <0 59 0x4>; ti,hwmods = "mmc5"; ti,needs-special-reset; }; From 00cbdce75b62a56bf3e6baca68b5ddb5474495a2 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Wed, 24 Oct 2012 12:31:34 +0200 Subject: [PATCH 20/71] ARM: dts: OMAP: Rename pandaES and var_som for consistency Rename the files to have names consistent across OMAP boards. Update the Makefile to use the new name. Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/Makefile | 4 ++-- arch/arm/boot/dts/{omap4-pandaES.dts => omap4-panda-es.dts} | 0 arch/arm/boot/dts/{omap4-var_som.dts => omap4-var-som.dts} | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm/boot/dts/{omap4-pandaES.dts => omap4-panda-es.dts} (100%) rename arch/arm/boot/dts/{omap4-var_som.dts => omap4-var-som.dts} (100%) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e69c921d44a2..634bd4246574 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -68,8 +68,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap3-evm.dtb \ omap3-tobi.dtb \ omap4-panda.dtb \ - omap4-pandaES.dtb \ - omap4-var_som.dtb \ + omap4-panda-es.dtb \ + omap4-var-som.dtb \ omap4-sdp.dtb \ omap5-evm.dtb \ am335x-evm.dtb \ diff --git a/arch/arm/boot/dts/omap4-pandaES.dts b/arch/arm/boot/dts/omap4-panda-es.dts similarity index 100% rename from arch/arm/boot/dts/omap4-pandaES.dts rename to arch/arm/boot/dts/omap4-panda-es.dts diff --git a/arch/arm/boot/dts/omap4-var_som.dts b/arch/arm/boot/dts/omap4-var-som.dts similarity index 100% rename from arch/arm/boot/dts/omap4-var_som.dts rename to arch/arm/boot/dts/omap4-var-som.dts From 0d935c16b779db481715b9885f2fd3d20a70bf79 Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Tue, 30 Oct 2012 15:04:01 +0530 Subject: [PATCH 21/71] ARM: dts: AM33XX: Add rtc node Add am33xx rtc node. Signed-off-by: Afzal Mohammed [b-cousson@ti.com: Update the subject] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 70d24b848c11..97a7bd31229a 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -291,5 +291,13 @@ ti,hwmods = "timer7"; ti,timer-pwm; }; + + rtc@44e3e000 { + compatible = "ti,da830-rtc"; + reg = <0x44e3e000 0x1000>; + interrupts = <75 + 76>; + ti,hwmods = "rtc"; + }; }; }; From 9fd3c748aac9418cd377249ca463050783d2198f Mon Sep 17 00:00:00 2001 From: "Philip, Avinash" Date: Wed, 31 Oct 2012 16:21:09 +0530 Subject: [PATCH 22/71] ARM: dts: AM33XX: Add SPI node Add McSPI data node to AM33XX device tree file. The McSPI module (and so as the driver) is reused from OMAP4. Signed-off-by: Philip, Avinash Tested-by: Matt Porter [b-cousson@ti.com: Remove interrupt-parent] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 97a7bd31229a..5dfd6822e6f8 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -299,5 +299,27 @@ 76>; ti,hwmods = "rtc"; }; + + spi0: spi@48030000 { + compatible = "ti,omap4-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x48030000 0x400>; + interrupt = <65>; + ti,spi-num-cs = <2>; + ti,hwmods = "spi0"; + status = "disabled"; + }; + + spi1: spi@481a0000 { + compatible = "ti,omap4-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x481a0000 0x400>; + interrupt = <125>; + ti,spi-num-cs = <2>; + ti,hwmods = "spi1"; + status = "disabled"; + }; }; }; From d03a93bbec5edfe33f09d629d27c1afd50f043aa Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 1 Nov 2012 08:57:08 -0500 Subject: [PATCH 23/71] ARM: dts: OMAP4: Update timer addresses For OMAP4 devices, timers 5-8 have both a L3 bus address and a Cortex-A9 private bus address. Currently the device-tree source only contains the L3 bus address for these timers. Update these timers to include the Cortex-A9 private address and make the default address the Cortex-A9 private bus address to match the current HWMOD implementation. Signed-off-by: Jon Hunter Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4.dtsi | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 23ee1498c98c..739bb79e410e 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -469,33 +469,37 @@ ti,hwmods = "timer4"; }; - timer5: timer@49038000 { + timer5: timer@40138000 { compatible = "ti,omap2-timer"; - reg = <0x49038000 0x80>; + reg = <0x40138000 0x80>, + <0x49038000 0x80>; interrupts = <0 41 0x4>; ti,hwmods = "timer5"; ti,timer-dsp; }; - timer6: timer@4903a000 { + timer6: timer@4013a000 { compatible = "ti,omap2-timer"; - reg = <0x4903a000 0x80>; + reg = <0x4013a000 0x80>, + <0x4903a000 0x80>; interrupts = <0 42 0x4>; ti,hwmods = "timer6"; ti,timer-dsp; }; - timer7: timer@4903c000 { + timer7: timer@4013c000 { compatible = "ti,omap2-timer"; - reg = <0x4903c000 0x80>; + reg = <0x4013c000 0x80>, + <0x4903c000 0x80>; interrupts = <0 43 0x4>; ti,hwmods = "timer7"; ti,timer-dsp; }; - timer8: timer@4903e000 { + timer8: timer@4013e000 { compatible = "ti,omap2-timer"; - reg = <0x4903e000 0x80>; + reg = <0x4013e000 0x80>, + <0x4903e000 0x80>; interrupts = <0 44 0x4>; ti,hwmods = "timer8"; ti,timer-pwm; From df692a925185b08ab5e792d163ee997bd773cdb9 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 1 Nov 2012 09:09:51 -0500 Subject: [PATCH 24/71] ARM: dts: OMAP5: Add timer nodes Add the 11 timer nodes for OMAP5 devices. Signed-off-by: Jon Hunter Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 89 ++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 930dbfe3bcff..c8954f1f96e4 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -379,5 +379,94 @@ ti,buffer-size = <128>; ti,hwmods = "mcbsp3"; }; + + timer1: timer@4ae18000 { + compatible = "ti,omap2-timer"; + reg = <0x4ae18000 0x80>; + interrupts = <0 37 0x4>; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; + + timer2: timer@48032000 { + compatible = "ti,omap2-timer"; + reg = <0x48032000 0x80>; + interrupts = <0 38 0x4>; + ti,hwmods = "timer2"; + }; + + timer3: timer@48034000 { + compatible = "ti,omap2-timer"; + reg = <0x48034000 0x80>; + interrupts = <0 39 0x4>; + ti,hwmods = "timer3"; + }; + + timer4: timer@48036000 { + compatible = "ti,omap2-timer"; + reg = <0x48036000 0x80>; + interrupts = <0 40 0x4>; + ti,hwmods = "timer4"; + }; + + timer5: timer@40138000 { + compatible = "ti,omap2-timer"; + reg = <0x40138000 0x80>, + <0x49038000 0x80>; + interrupts = <0 41 0x4>; + ti,hwmods = "timer5"; + ti,timer-dsp; + }; + + timer6: timer@4013a000 { + compatible = "ti,omap2-timer"; + reg = <0x4013a000 0x80>, + <0x4903a000 0x80>; + interrupts = <0 42 0x4>; + ti,hwmods = "timer6"; + ti,timer-dsp; + ti,timer-pwm; + }; + + timer7: timer@4013c000 { + compatible = "ti,omap2-timer"; + reg = <0x4013c000 0x80>, + <0x4903c000 0x80>; + interrupts = <0 43 0x4>; + ti,hwmods = "timer7"; + ti,timer-dsp; + }; + + timer8: timer@4013e000 { + compatible = "ti,omap2-timer"; + reg = <0x4013e000 0x80>, + <0x4903e000 0x80>; + interrupts = <0 44 0x4>; + ti,hwmods = "timer8"; + ti,timer-dsp; + ti,timer-pwm; + }; + + timer9: timer@4803e000 { + compatible = "ti,omap2-timer"; + reg = <0x4803e000 0x80>; + interrupts = <0 45 0x4>; + ti,hwmods = "timer9"; + }; + + timer10: timer@48086000 { + compatible = "ti,omap2-timer"; + reg = <0x48086000 0x80>; + interrupts = <0 46 0x4>; + ti,hwmods = "timer10"; + }; + + timer11: timer@48088000 { + compatible = "ti,omap2-timer"; + reg = <0x48088000 0x80>; + interrupts = <0 47 0x4>; + ti,hwmods = "timer11"; + ti,timer-pwm; + }; }; }; From 3b3132f7e80e3d786f8ad5d5b97d4b6122be9aaa Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 1 Nov 2012 09:12:23 -0500 Subject: [PATCH 25/71] ARM: dts: OMAP5: Add counter node Add the 32kHz counter node for OMAP5 devices. Signed-off-by: Jon Hunter Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index c8954f1f96e4..ead74c85d999 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -77,6 +77,12 @@ ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; + counter32k: counter@4ae04000 { + compatible = "ti,omap-counter32k"; + reg = <0x4ae04000 0x40>; + ti,hwmods = "counter_32k"; + }; + omap5_pmx_core: pinmux@4a002840 { compatible = "ti,omap4-padconf", "pinctrl-single"; reg = <0x4a002840 0x01b6>; From ad24bde8f1025da014108493b595bed22d989efb Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 20 Jun 2012 15:55:24 -0500 Subject: [PATCH 26/71] ARM: OMAP3: Dynamically disable secure timer nodes for secure devices OMAP3 devices may or may not have security features enabled. Security enabled devices are known as high-secure (HS) and devices without security are known as general purpose (GP). For OMAP3 devices there are 12 general purpose timers available. On secure devices the 12th timer is reserved for secure usage and so cannot be used by the kernel, where as for a GP device it is available. We can detect the OMAP device type, secure or GP, at runtime via an on-chip register. Today, when not using DT, we do not register the 12th timer as a linux device if the device is secure. When using device tree, device tree is going to register all the timer devices it finds in the device tree blob. To prevent device tree from registering 12th timer on a secure OMAP3 device we can add a status property to the timer binding with the value "disabled" at boot time. Note that timer 12 on a OMAP3 device has a property "ti,timer-secure" to indicate that it will not be available on a secure device and so for secure OMAP3 devices, we search for timers with this property and then disable them. Using the prom_add_property() function to dynamically add a property was a recommended approach suggested by Rob Herring [1]. I have tested this on an OMAP3 GP device and faking it to pretend to be a secure device to ensure that any timers marked with "ti,timer-secure" are not registered on boot. I have also made sure that all timers are registered as expected on a GP device by default. [1] http://comments.gmane.org/gmane.linux.ports.arm.omap/79203 Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/timer.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 69e46631a7cd..def9a0ebe42d 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -144,6 +144,41 @@ static struct clock_event_device clockevent_gpt = { .set_mode = omap2_gp_timer_set_mode, }; +static struct property device_disabled = { + .name = "status", + .length = sizeof("disabled"), + .value = "disabled", +}; + +static struct of_device_id omap_timer_match[] __initdata = { + { .compatible = "ti,omap2-timer", }, + { } +}; + +/** + * omap_dmtimer_init - initialisation function when device tree is used + * + * For secure OMAP3 devices, timers with device type "timer-secure" cannot + * be used by the kernel as they are reserved. Therefore, to prevent the + * kernel registering these devices remove them dynamically from the device + * tree on boot. + */ +void __init omap_dmtimer_init(void) +{ + struct device_node *np; + + if (!cpu_is_omap34xx()) + return; + + /* If we are a secure device, remove any secure timer nodes */ + if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { + for_each_matching_node(np, omap_timer_match) { + if (of_get_property(np, "ti,timer-secure", NULL)) + prom_add_property(np, &device_disabled); + } + } +} + static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, int gptimer_id, const char *fck_source) @@ -437,6 +472,7 @@ static inline void __init realtime_counter_init(void) clksrc_nr, clksrc_src) \ static void __init omap##name##_timer_init(void) \ { \ + omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src); \ omap2_clocksource_init((clksrc_nr), clksrc_src); \ } From 373fe0bdf9911c4362942162a2b4d20e6f74da5b Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 6 Sep 2012 15:28:00 -0500 Subject: [PATCH 27/71] ARM: OMAP: Add function to request a timer by capability Currently OMAP timers can be requested by requesting any available or by a numerical device ID. If a specific timer is required because it has a particular capability, such as can interrupt the on-chip DSP in addition to the ARM CPU, then the user needs to know the device ID of the timer with this feature. Therefore, add a new API called omap_dm_timer_request_by_cap() that allows drivers to request a timer by capability. Signed-off-by: Jon Hunter --- arch/arm/plat-omap/dmtimer.c | 52 +++++++++++++++++++++++ arch/arm/plat-omap/include/plat/dmtimer.h | 1 + 2 files changed, 53 insertions(+) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 938b50a33439..2574b86ad2dc 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -237,6 +237,58 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) } EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); +/** + * omap_dm_timer_request_by_cap - Request a timer by capability + * @cap: Bit mask of capabilities to match + * + * Find a timer based upon capabilities bit mask. Callers of this function + * should use the definitions found in the plat/dmtimer.h file under the + * comment "timer capabilities used in hwmod database". Returns pointer to + * timer handle on success and a NULL pointer on failure. + */ +struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) +{ + struct omap_dm_timer *timer = NULL, *t; + unsigned long flags; + + if (!cap) + return NULL; + + spin_lock_irqsave(&dm_timer_lock, flags); + list_for_each_entry(t, &omap_timer_list, node) { + if ((!t->reserved) && ((t->capability & cap) == cap)) { + /* + * If timer is not NULL, we have already found one timer + * but it was not an exact match because it had more + * capabilites that what was required. Therefore, + * unreserve the last timer found and see if this one + * is a better match. + */ + if (timer) + timer->reserved = 0; + + timer = t; + timer->reserved = 1; + + /* Exit loop early if we find an exact match */ + if (t->capability == cap) + break; + } + } + spin_unlock_irqrestore(&dm_timer_lock, flags); + + if (timer && omap_dm_timer_prepare(timer)) { + timer->reserved = 0; + timer = NULL; + } + + if (!timer) + pr_debug("%s: timer request failed!\n", __func__); + + return timer; +} +EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap); + int omap_dm_timer_free(struct omap_dm_timer *timer) { if (unlikely(!timer)) diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 85868e98c11c..348f855d3dab 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -99,6 +99,7 @@ struct dmtimer_platform_data { int omap_dm_timer_reserve_systimer(int id); struct omap_dm_timer *omap_dm_timer_request(void); struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); +struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap); int omap_dm_timer_free(struct omap_dm_timer *timer); void omap_dm_timer_enable(struct omap_dm_timer *timer); void omap_dm_timer_disable(struct omap_dm_timer *timer); From 7dd9d502b6cb9f82c9726ea601276b666a93e95d Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 12 Sep 2012 11:40:58 -0500 Subject: [PATCH 28/71] ARM: OMAP3: Add generic machine descriptor for boards with OMAP3 GP devices OMAP3 devices may or may not have security features enabled. Security enabled devices are known as high-secure (HS) and devices without security are known as general purpose (GP). Some OMAP3 boards, such as the OMAP3 beagle board, only use GP devices and for GP devices there is a 12th timer available on-chip that can operate at 32kHz. The clock for 12th timer is generated by an internal oscillator and is unique this timer. Boards such as the beagle board use this timer as a 32kHz based clock-events timer because early versions of the board had a hardware problem preventing them from using other on-chip timers clocked by a external 32kHz clock. When booting with device-tree all OMAP3 devices use timer 1 by default for the clock-events timer. Therefore, add a generic machine descriptor for boards with OMAP3 GP devices so that they can use the 12th timer as the clock-events timer instead of the default. Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/board-generic.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 601ecdfb1cf9..d69018028d96 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -97,6 +97,23 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .dt_compat = omap3_boards_compat, .restart = omap_prcm_restart, MACHINE_END + +static const char *omap3_gp_boards_compat[] __initdata = { + "ti,omap3-beagle", + NULL, +}; + +DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)") + .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap3430_init_early, + .init_irq = omap_intc_of_init, + .handle_irq = omap3_intc_handle_irq, + .init_machine = omap_generic_init, + .timer = &omap3_secure_timer, + .dt_compat = omap3_gp_boards_compat, + .restart = omap_prcm_restart, +MACHINE_END #endif #ifdef CONFIG_SOC_AM33XX From 9725f4451a9ccd159b1d13f63e05896cd9bce07d Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Mon, 14 May 2012 10:41:37 -0500 Subject: [PATCH 29/71] ARM: OMAP: Add DT support for timer driver In order to add device-tree support to the timer driver the following changes were made ... 1. Allocate system timers (used for clock-events and clock-source) based upon timer properties rather than using an hard-coded timer instance ID. To allow this a new helper function called omap_dmtimer_find_by_property() has been added for finding a timer with the particular properties in the device-tree blob. Please note that this is an internal helper function for system timers only to find a timer in the device-tree blob. This cannot be used by device drivers, another API has been added for that (see below). Timers that are allocated for system timers are dynamically disabled at boot time by adding a status property with the value "disabled" to the timer's device-tree node. Please note that when allocating system timers we now pass a timer ID and timer property. The timer ID is only be used for allocating a timer when booting without device-tree. Once device-tree migration is complete, all the timer ID references will be removed. 2. System timer resources (memory and interrupts) are directly obtained from the device-tree timer node when booting with device-tree, so that system timers are no longer reliant upon the OMAP HWMOD framework to provide these resources. 3. If DT blob is present, then let device-tree create the timer devices dynamically. 4. When device-tree is present the "id" field in the platform_device structure (pdev->id) is initialised to -1 and hence cannot be used to identify a timer instance. Due to this the following changes were made ... a). The API omap_dm_timer_request_specific() is not supported when using device-tree, because it uses the device ID to request a specific timer. This function will return an error if called when device-tree is present. Users of this API should use omap_dm_timer_request_by_cap() instead. b). When removing the DMTIMER driver, the timer "id" was used to identify the timer instance. The remove function has been modified to use the device name instead of the "id". 5. When device-tree is present the platform_data structure will be NULL and so check for this. 6. The OMAP timer device tree binding has the following optional parameters ... a). ti,timer-alwon --> Timer is in an always-on power domain b). ti,timer-dsp --> Timer can generate an interrupt to the on-chip DSP c). ti,timer-pwm --> Timer can generate a PWM output d). ti,timer-secure --> Timer is reserved on a secure OMAP device Search for the above parameters and set the appropriate timer attribute flags. Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/timer.c | 145 ++++++++++++++++++++++++++--------- arch/arm/plat-omap/dmtimer.c | 41 ++++++++-- 2 files changed, 145 insertions(+), 41 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index def9a0ebe42d..92447cd7a41a 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -37,6 +37,8 @@ #include #include #include +#include +#include #include #include @@ -66,11 +68,13 @@ #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE #define OMAP3_SECURE_TIMER 12 +#define TIMER_PROP_SECURE "ti,timer-secure" #else #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE #define OMAP3_SECURE_TIMER 1 +#define TIMER_PROP_SECURE "ti,timer-alwon" #endif #define REALTIME_COUNTER_BASE 0x48243200 @@ -155,6 +159,40 @@ static struct of_device_id omap_timer_match[] __initdata = { { } }; +/** + * omap_get_timer_dt - get a timer using device-tree + * @match - device-tree match structure for matching a device type + * @property - optional timer property to match + * + * Helper function to get a timer during early boot using device-tree for use + * as kernel system timer. Optionally, the property argument can be used to + * select a timer with a specific property. Once a timer is found then mark + * the timer node in device-tree as disabled, to prevent the kernel from + * registering this timer as a platform device and so no one else can use it. + */ +static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, + const char *property) +{ + struct device_node *np; + + for_each_matching_node(np, match) { + if (!of_device_is_available(np)) { + of_node_put(np); + continue; + } + + if (property && !of_get_property(np, property, NULL)) { + of_node_put(np); + continue; + } + + prom_add_property(np, &device_disabled); + return np; + } + + return NULL; +} + /** * omap_dmtimer_init - initialisation function when device tree is used * @@ -172,43 +210,74 @@ void __init omap_dmtimer_init(void) /* If we are a secure device, remove any secure timer nodes */ if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { - for_each_matching_node(np, omap_timer_match) { - if (of_get_property(np, "ti,timer-secure", NULL)) - prom_add_property(np, &device_disabled); - } + np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); + if (np) + of_node_put(np); } } static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, int gptimer_id, - const char *fck_source) + const char *fck_source, + const char *property) { char name[10]; /* 10 = sizeof("gptXX_Xck0") */ + const char *oh_name; + struct device_node *np; struct omap_hwmod *oh; struct resource irq_rsrc, mem_rsrc; size_t size; int res = 0; int r; - sprintf(name, "timer%d", gptimer_id); - omap_hwmod_setup_one(name); - oh = omap_hwmod_lookup(name); + if (of_have_populated_dt()) { + np = omap_get_timer_dt(omap_timer_match, NULL); + if (!np) + return -ENODEV; + + of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); + if (!oh_name) + return -ENODEV; + + timer->irq = irq_of_parse_and_map(np, 0); + if (!timer->irq) + return -ENXIO; + + timer->io_base = of_iomap(np, 0); + + of_node_put(np); + } else { + if (omap_dm_timer_reserve_systimer(gptimer_id)) + return -ENODEV; + + sprintf(name, "timer%d", gptimer_id); + oh_name = name; + } + + omap_hwmod_setup_one(oh_name); + oh = omap_hwmod_lookup(oh_name); + if (!oh) return -ENODEV; - r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); - if (r) - return -ENXIO; - timer->irq = irq_rsrc.start; + if (!of_have_populated_dt()) { + r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, + &irq_rsrc); + if (r) + return -ENXIO; + timer->irq = irq_rsrc.start; - r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); - if (r) - return -ENXIO; - timer->phys_base = mem_rsrc.start; - size = mem_rsrc.end - mem_rsrc.start; + r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, + &mem_rsrc); + if (r) + return -ENXIO; + timer->phys_base = mem_rsrc.start; + size = mem_rsrc.end - mem_rsrc.start; + + /* Static mapping, never released */ + timer->io_base = ioremap(timer->phys_base, size); + } - /* Static mapping, never released */ - timer->io_base = ioremap(timer->phys_base, size); if (!timer->io_base) return -ENXIO; @@ -219,9 +288,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, omap_hwmod_enable(oh); - if (omap_dm_timer_reserve_systimer(gptimer_id)) - return -ENODEV; - + /* FIXME: Need to remove hard-coded test on timer ID */ if (gptimer_id != 12) { struct clk *src; @@ -231,8 +298,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, } else { res = __omap_dm_timer_set_source(timer->fclk, src); if (IS_ERR_VALUE(res)) - pr_warning("%s: timer%i cannot set source\n", - __func__, gptimer_id); + pr_warn("%s: %s cannot set source\n", + __func__, oh->name); clk_put(src); } } @@ -248,11 +315,12 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, } static void __init omap2_gp_clockevent_init(int gptimer_id, - const char *fck_source) + const char *fck_source, + const char *property) { int res; - res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); + res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property); BUG_ON(res); omap2_gp_timer_irq.dev_id = &clkev; @@ -356,7 +424,7 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id, { int res; - res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source); + res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL); BUG_ON(res); __omap_dm_timer_load_start(&clksrc, @@ -468,12 +536,12 @@ static inline void __init realtime_counter_init(void) {} #endif -#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ +#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ clksrc_nr, clksrc_src) \ static void __init omap##name##_timer_init(void) \ { \ omap_dmtimer_init(); \ - omap2_gp_clockevent_init((clkev_nr), clkev_src); \ + omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ omap2_clocksource_init((clksrc_nr), clksrc_src); \ } @@ -483,20 +551,23 @@ struct sys_timer omap##name##_timer = { \ }; #ifdef CONFIG_ARCH_OMAP2 -OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE) +OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, "ti,timer-alwon", + 2, OMAP2_MPU_SOURCE) OMAP_SYS_TIMER(2) #endif #ifdef CONFIG_ARCH_OMAP3 -OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE) +OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, "ti,timer-alwon", + 2, OMAP3_MPU_SOURCE) OMAP_SYS_TIMER(3) OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, - 2, OMAP3_MPU_SOURCE) + TIMER_PROP_SECURE, 2, OMAP3_MPU_SOURCE) OMAP_SYS_TIMER(3_secure) #endif #ifdef CONFIG_SOC_AM33XX -OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) +OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon", + 2, OMAP4_MPU_SOURCE) OMAP_SYS_TIMER(3_am33xx) #endif @@ -508,7 +579,7 @@ static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, static void __init omap4_timer_init(void) { - omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); + omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon"); omap2_clocksource_init(2, OMAP4_MPU_SOURCE); #ifdef CONFIG_LOCAL_TIMERS /* Local timers are not supprted on OMAP4430 ES1.0 */ @@ -534,7 +605,7 @@ static void __init omap5_timer_init(void) { int err; - omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); + omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon"); omap2_clocksource_init(2, OMAP4_MPU_SOURCE); realtime_counter_init(); @@ -619,6 +690,10 @@ static int __init omap2_dm_timer_init(void) { int ret; + /* If dtb is there, the devices will be created dynamically */ + if (of_have_populated_dt()) + return -ENODEV; + ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); if (unlikely(ret)) { pr_err("%s: device registration failed.\n", __func__); diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 2574b86ad2dc..b09e55632f4b 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -40,6 +40,8 @@ #include #include #include +#include +#include #include #include @@ -212,6 +214,13 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) unsigned long flags; int ret = 0; + /* Requesting timer by ID is not supported when device tree is used */ + if (of_have_populated_dt()) { + pr_warn("%s: Please use omap_dm_timer_request_by_cap()\n", + __func__); + return NULL; + } + spin_lock_irqsave(&dm_timer_lock, flags); list_for_each_entry(t, &omap_timer_list, node) { if (t->pdev->id == id && !t->reserved) { @@ -466,7 +475,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) * use the clock framework to set the parent clock. To be removed * once OMAP1 migrated to using clock framework for dmtimers */ - if (pdata->set_timer_src) + if (pdata && pdata->set_timer_src) return pdata->set_timer_src(timer->pdev, source); fclk = clk_get(&timer->pdev->dev, "fck"); @@ -747,7 +756,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct dmtimer_platform_data *pdata = pdev->dev.platform_data; - if (!pdata) { + if (!pdata && !dev->of_node) { dev_err(dev, "%s: no platform data.\n", __func__); return -ENODEV; } @@ -776,11 +785,23 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev) return -ENOMEM; } - timer->id = pdev->id; + if (dev->of_node) { + if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) + timer->capability |= OMAP_TIMER_ALWON; + if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) + timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; + if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) + timer->capability |= OMAP_TIMER_HAS_PWM; + if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) + timer->capability |= OMAP_TIMER_SECURE; + } else { + timer->id = pdev->id; + timer->capability = pdata->timer_capability; + timer->reserved = omap_dm_timer_reserved_systimer(timer->id); + } + timer->irq = irq->start; - timer->reserved = omap_dm_timer_reserved_systimer(timer->id); timer->pdev = pdev; - timer->capability = pdata->timer_capability; /* Skip pm_runtime_enable for OMAP1 */ if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { @@ -820,7 +841,8 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev) spin_lock_irqsave(&dm_timer_lock, flags); list_for_each_entry(timer, &omap_timer_list, node) - if (timer->pdev->id == pdev->id) { + if (!strcmp(dev_name(&timer->pdev->dev), + dev_name(&pdev->dev))) { list_del(&timer->node); ret = 0; break; @@ -830,11 +852,18 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev) return ret; } +static const struct of_device_id omap_timer_match[] = { + { .compatible = "ti,omap2-timer", }, + {}, +}; +MODULE_DEVICE_TABLE(of, omap_timer_match); + static struct platform_driver omap_dm_timer_driver = { .probe = omap_dm_timer_probe, .remove = __devexit_p(omap_dm_timer_remove), .driver = { .name = "omap_timer", + .of_match_table = of_match_ptr(omap_timer_match), }, }; From 9883f7c8dd21acb90697582ca331f3f8a66ac054 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 9 Oct 2012 14:12:26 -0500 Subject: [PATCH 30/71] ARM: OMAP2+: Add device-tree support for 32kHz counter For OMAP devices, the 32kHz counter is the default clock-source for the kernel. However, this is not the only possible clock-source the kernel can use for OMAP devices. When booting with device-tree, if the 32kHz counter is the desired clock-source for the kernel, then parse the device-tree blob to ensure that the counter is present and if so map memory for the counter using the device-tree of_iomap() function so we are no longer reliant on the OMAP HWMOD framework to do this for us. Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/timer.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 92447cd7a41a..0758bae3a57a 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -159,6 +159,11 @@ static struct of_device_id omap_timer_match[] __initdata = { { } }; +static struct of_device_id omap_counter_match[] __initdata = { + { .compatible = "ti,omap-counter32k", }, + { } +}; + /** * omap_get_timer_dt - get a timer using device-tree * @match - device-tree match structure for matching a device type @@ -377,10 +382,25 @@ static u32 notrace dmtimer_read_sched_clock(void) static int __init omap2_sync32k_clocksource_init(void) { int ret; + struct device_node *np = NULL; struct omap_hwmod *oh; void __iomem *vbase; const char *oh_name = "counter_32k"; + /* + * If device-tree is present, then search the DT blob + * to see if the 32kHz counter is supported. + */ + if (of_have_populated_dt()) { + np = omap_get_timer_dt(omap_counter_match, NULL); + if (!np) + return -ENODEV; + + of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); + if (!oh_name) + return -ENODEV; + } + /* * First check hwmod data is available for sync32k counter */ @@ -390,7 +410,13 @@ static int __init omap2_sync32k_clocksource_init(void) omap_hwmod_setup_one(oh_name); - vbase = omap_hwmod_get_mpu_rt_va(oh); + if (np) { + vbase = of_iomap(np, 0); + of_node_put(np); + } else { + vbase = omap_hwmod_get_mpu_rt_va(oh); + } + if (!vbase) { pr_warn("%s: failed to get counter_32k resource\n", __func__); return -ENXIO; From 45cbe6ca07c649fef67c550a84af6fd492d77893 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 5 Nov 2012 18:22:50 +0530 Subject: [PATCH 31/71] ARM: dts: omap5-evm: Fix size of memory defined for EVM Memory present for OMAP5-evm is 2GB. But in dts file it is specified as 1GB. Correcting the same. Signed-off-by: Lokesh Vutla Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts index c663eba73168..88d3d9b8c318 100644 --- a/arch/arm/boot/dts/omap5-evm.dts +++ b/arch/arm/boot/dts/omap5-evm.dts @@ -15,7 +15,7 @@ memory { device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ + reg = <0x80000000 0x80000000>; /* 2 GB */ }; vmmcsd_fixed: fixedregulator-mmcsd { From e6900ddf615438edbc53df4d35a37147459d4cd8 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 5 Nov 2012 18:22:51 +0530 Subject: [PATCH 32/71] ARM: dts: omap5: EMIF device tree data for OMAP5 boards Adding EMIF device tree data for OMAP5 boards. Signed-off-by: Lokesh Vutla Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index ead74c85d999..790bb2a4b343 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -474,5 +474,27 @@ ti,hwmods = "timer11"; ti,timer-pwm; }; + + emif1: emif@0x4c000000 { + compatible = "ti,emif-4d5"; + ti,hwmods = "emif1"; + phy-type = <2>; /* DDR PHY type: Intelli PHY */ + reg = <0x4c000000 0x400>; + interrupts = <0 110 0x4>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; + + emif2: emif@0x4d000000 { + compatible = "ti,emif-4d5"; + ti,hwmods = "emif2"; + phy-type = <2>; /* DDR PHY type: Intelli PHY */ + reg = <0x4d000000 0x400>; + interrupts = <0 111 0x4>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; }; }; From 4d2750f31935719453ac65829a09766cb22f9943 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 5 Nov 2012 18:22:52 +0530 Subject: [PATCH 33/71] ARM: dts: omap5-evm: LPDDR2 memory device details for EVM Samsung's K3PE0E000B memory part is used in OMAP5-evm board. Adding timings and geometry details for Samsung's memory part and attaching the same to device-handle of EMIF1/2. Signed-off-by: Lokesh Vutla Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-evm.dts | 11 ++++ arch/arm/boot/dts/samsung_k3pe0e000b.dtsi | 67 +++++++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 arch/arm/boot/dts/samsung_k3pe0e000b.dtsi diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts index 88d3d9b8c318..8722c15bbba2 100644 --- a/arch/arm/boot/dts/omap5-evm.dts +++ b/arch/arm/boot/dts/omap5-evm.dts @@ -8,6 +8,7 @@ /dts-v1/; /include/ "omap5.dtsi" +/include/ "samsung_k3pe0e000b.dtsi" / { model = "TI OMAP5 EVM board"; @@ -140,3 +141,13 @@ &mcbsp3 { status = "disabled"; }; + +&emif1 { + cs1-used; + device-handle = <&samsung_K3PE0E000B>; +}; + +&emif2 { + cs1-used; + device-handle = <&samsung_K3PE0E000B>; +}; diff --git a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi new file mode 100644 index 000000000000..9657a5cbc3ad --- /dev/null +++ b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi @@ -0,0 +1,67 @@ +/* + * Timings and Geometry for Samsung K3PE0E000B memory part + */ + +/ { + samsung_K3PE0E000B: lpddr2 { + compatible = "Samsung,K3PE0E000B","jedec,lpddr2-s4"; + density = <4096>; + io-width = <32>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <533333333>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + tDQSCK-max-derated = <6000>; + }; + + timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <266666666>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + tDQSCK-max-derated = <6000>; + }; + }; +}; From 5d9b66f278cb1f137dc6126ed461e747870d9058 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 6 Nov 2012 19:18:29 +0530 Subject: [PATCH 34/71] ARM: dts: AM33XX: Add pinmux configuration for matrix keypad to EVM Add pinmux configurations for gpio matrix keypad. In this patch, only single named mode/state is added and these pins are configured during pinctrl driver initialization. Default mode is nothing but the values required for the module during active state. With this configurations module is functional as expected. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evm.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 513284fc66b9..9199456cfac4 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -24,6 +24,21 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; + am33xx_pinmux: pinmux@44e10800 { + pinctrl-names = "default"; + pinctrl-0 = <&matrix_keypad_s0>; + + matrix_keypad_s0: matrix_keypad_s0 { + pinctrl-single,pins = < + 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */ + 0x58 0x7 /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */ + 0x64 0x27 /* gpmc_a9.gpio1_25, INPUT | MODE7 */ + 0x68 0x27 /* gpmc_a10.gpio1_26, INPUT | MODE7 */ + 0x6c 0x27 /* gpmc_a11.gpio1_27, INPUT | MODE7 */ + >; + }; + }; + ocp { uart1: serial@44e09000 { status = "okay"; From 2ca1d317aa78492f206d3e325965a990aa33a226 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 6 Nov 2012 19:18:30 +0530 Subject: [PATCH 35/71] ARM: dts: AM33XX: Add matrix keypad device tree data to am335x-evm Add matrix keypad device tree data to am335x-evm by adding all the necessary parameters like keymap, row & column gpios and etc. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evm.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 9199456cfac4..8076e66f9367 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -110,6 +110,26 @@ regulator-name = "lis3_reg"; regulator-boot-on; }; + + matrix_keypad: matrix_keypad@0 { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + row-gpios = <&gpio2 25 0 /* Bank1, pin25 */ + &gpio2 26 0 /* Bank1, pin26 */ + &gpio2 27 0>; /* Bank1, pin27 */ + + col-gpios = <&gpio2 21 0 /* Bank1, pin21 */ + &gpio2 22 0>; /* Bank1, pin22 */ + + linux,keymap = <0x0000008b /* MENU */ + 0x0100009e /* BACK */ + 0x02000069 /* LEFT */ + 0x0001006a /* RIGHT */ + 0x0101001c /* ENTER */ + 0x0201006c>; /* DOWN */ + }; }; /include/ "tps65910.dtsi" From 404aa0d71ddd82189ef3680d6c41f127dc89d29f Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 6 Nov 2012 19:18:31 +0530 Subject: [PATCH 36/71] ARM: dts: AM33XX: Add pinmux configuration for volume-keys to EVM Add pinmux configurations for gpio volume keys. In this patch, only single named mode/state is added and these pins are configured during pinctrl driver initialization. Default mode is nothing but the values required for the module during active state. With this configurations module is functional as expected. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evm.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 8076e66f9367..e087b8751e0c 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -26,7 +26,7 @@ am33xx_pinmux: pinmux@44e10800 { pinctrl-names = "default"; - pinctrl-0 = <&matrix_keypad_s0>; + pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>; matrix_keypad_s0: matrix_keypad_s0 { pinctrl-single,pins = < @@ -37,6 +37,13 @@ 0x6c 0x27 /* gpmc_a11.gpio1_27, INPUT | MODE7 */ >; }; + + volume_keys_s0: volume_keys_s0 { + pinctrl-single,pins = < + 0x150 0x27 /* spi0_sclk.gpio0_2, INPUT | MODE7 */ + 0x154 0x27 /* spi0_d0.gpio0_3, INPUT | MODE7 */ + >; + }; }; ocp { From 822c99367ead1e2fa2ba03d42d10aa7c5a84190b Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 6 Nov 2012 19:18:32 +0530 Subject: [PATCH 37/71] ARM: dts: AM33XX: Add volume-keys device tree data to am335x-evm Add gpio based volume keys device tree data to am335x-evm by adding all the required parameters like keycode, gpios and etc. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evm.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index e087b8751e0c..9f65f17ebdf8 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -137,6 +137,27 @@ 0x0101001c /* ENTER */ 0x0201006c>; /* DOWN */ }; + + gpio_keys: volume_keys@0 { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + switch@9 { + label = "volume-up"; + linux,code = <115>; + gpios = <&gpio1 2 1>; + gpio-key,wakeup; + }; + + switch@10 { + label = "volume-down"; + linux,code = <114>; + gpios = <&gpio1 3 1>; + gpio-key,wakeup; + }; + }; }; /include/ "tps65910.dtsi" From 7e782c41da0148af457e474b8744e002af869227 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 6 Nov 2012 19:18:33 +0530 Subject: [PATCH 38/71] ARM: dts: AM33XX: Add pinmux configuration for user-leds to BONE Add pinmux configurations for gpio based user-keys to am335x-bone. In this patch, only single named mode/state is added and these pins are configured during pinctrl driver initialization. Default mode is nothing but the values required for the module during active state. With this configurations module is functional as expected. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 91eee97371ea..1aac58bfb4a0 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -24,6 +24,20 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; + am33xx_pinmux: pinmux@44e10800 { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */ + 0x58 0x17 /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */ + 0x5c 0x7 /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */ + 0x60 0x17 /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */ + >; + }; + }; + ocp { uart1: serial@44e09000 { status = "okay"; From 5d4e17063fa8d0af63e356089a321c482cbd7603 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 6 Nov 2012 19:18:34 +0530 Subject: [PATCH 39/71] ARM: dts: AM33XX: Add user-leds device tree data to am335x-bone Add gpio-leds device tree data to am335x-bone device to enable gpio based user-leds (USR0, USR1, USR2 and USR3) present on BeagleBone. [koen@dominion.thruhere.net: led0, led1 suggested by koen] Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 1aac58bfb4a0..2c338889df1b 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -53,6 +53,36 @@ }; }; + + leds { + compatible = "gpio-leds"; + + led@2 { + label = "beaglebone:green:heartbeat"; + gpios = <&gpio2 21 0>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@3 { + label = "beaglebone:green:mmc0"; + gpios = <&gpio2 22 0>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@4 { + label = "beaglebone:green:usr2"; + gpios = <&gpio2 23 0>; + default-state = "off"; + }; + + led@5 { + label = "beaglebone:green:usr3"; + gpios = <&gpio2 24 0>; + default-state = "off"; + }; + }; }; /include/ "tps65217.dtsi" From 2647dd10fcd85aa1404878e8692a1cab928d3ec7 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 6 Nov 2012 19:18:35 +0530 Subject: [PATCH 40/71] ARM: dts: AM33XX: Add pinmux configuration for gpio-leds to EVMSK Add pinmux configurations for gpio based volume keys to am335x-evmsk. In this patch, only single named mode/state is added and these pins are configured during pinctrl driver initialization. Default mode is nothing but the values required for the module during active state. With this configurations module is functional as expected. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evmsk.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 6f5387987865..659ec5b73ab4 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -30,6 +30,20 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; + am33xx_pinmux: pinmux@44e10800 { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + 0x10 0x7 /* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */ + 0x14 0x7 /* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */ + 0x18 0x7 /* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */ + 0x1c 0x7 /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */ + >; + }; + }; + ocp { uart1: serial@44e09000 { status = "okay"; From 29b0b84381221e94063ceb4129f4e4bc1bce1215 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 6 Nov 2012 19:18:36 +0530 Subject: [PATCH 41/71] ARM: dts: AM33XX: Add user-leds device tree data to am335x-evmsk Add gpio-leds device tree data to am335x-evmsk device to enable gpio based user-leds (USR0, USR1, USR2 and USR3) present on am335x starter kit. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evmsk.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 659ec5b73ab4..7262fa83b8d1 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -100,6 +100,36 @@ regulator-name = "lis3_reg"; regulator-boot-on; }; + + leds { + compatible = "gpio-leds"; + + led@1 { + label = "evmsk:green:usr0"; + gpios = <&gpio2 4 0>; + default-state = "off"; + }; + + led@2 { + label = "evmsk:green:usr1"; + gpios = <&gpio2 5 0>; + default-state = "off"; + }; + + led@3 { + label = "evmsk:green:mmc0"; + gpios = <&gpio2 6 0>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@4 { + label = "evmsk:green:heartbeat"; + gpios = <&gpio2 7 0>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; }; /include/ "tps65910.dtsi" From d98258b81721d452d2da98e9fc83c57e6ef70667 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 6 Nov 2012 19:18:37 +0530 Subject: [PATCH 42/71] ARM: dts: AM33XX: Add pinmux configuration for gpio-keys to EVMSK Add pinmux configurations for gpio based keys to am335x-evmsk. In this patch, only single named mode/state is added and these pins are configured during pinctrl driver initialization. Default mode is nothing but the values required for the module during active state. With this configurations module is functional as expected. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evmsk.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 7262fa83b8d1..0f825dd2d178 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -32,7 +32,7 @@ am33xx_pinmux: pinmux@44e10800 { pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; + pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>; user_leds_s0: user_leds_s0 { pinctrl-single,pins = < @@ -42,6 +42,15 @@ 0x1c 0x7 /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */ >; }; + + gpio_keys_s0: gpio_keys_s0 { + pinctrl-single,pins = < + 0x94 0x27 /* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */ + 0x90 0x27 /* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */ + 0x70 0x27 /* gpmc_wait0.gpio0_30, INPUT | MODE7 */ + 0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */ + >; + }; }; ocp { From 00834b783ee3029a96489fae0c2eb3b1a198205d Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 6 Nov 2012 19:18:38 +0530 Subject: [PATCH 43/71] ARM: dts: AM33XX: Add push-buttons device tree data to am335x-evmsk Add gpio based push buttons device tree data to am335x-evmsk device by adding all the necessary parameters like key-code, gpios and etc. Signed-off-by: AnilKumar Ch Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evmsk.dts | 31 ++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 0f825dd2d178..f5a6162a4ff2 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -139,6 +139,37 @@ default-state = "off"; }; }; + + gpio_buttons: gpio_buttons@0 { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + switch@1 { + label = "button0"; + linux,code = <0x100>; + gpios = <&gpio3 3 0>; + }; + + switch@2 { + label = "button1"; + linux,code = <0x101>; + gpios = <&gpio3 2 0>; + }; + + switch@3 { + label = "button2"; + linux,code = <0x102>; + gpios = <&gpio1 30 0>; + gpio-key,wakeup; + }; + + switch@4 { + label = "button3"; + linux,code = <0x103>; + gpios = <&gpio3 5 0>; + }; + }; }; /include/ "tps65910.dtsi" From 35b47fbb12b42e6c577716b67a9172fe46e2f9b0 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Gupta Date: Tue, 6 Nov 2012 19:59:38 +0530 Subject: [PATCH 44/71] ARM: dts: AM33XX: Add usbss node Device tree node for usbss on AM33XX. There are two musb controllers on am33xx platform so have port0-mode and port1-mode data. Signed-off-by: Ajay Kumar Gupta Signed-off-by: Santhapuri, Damodar Signed-off-by: Ravi Babu [afzal@ti.com: reg & interrupt property addition] Signed-off-by: Afzal Mohammed Reviewed-by: Felipe Balbi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 5dfd6822e6f8..20a3f29a6bfe 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -321,5 +321,22 @@ ti,hwmods = "spi1"; status = "disabled"; }; + + usb@47400000 { + compatible = "ti,musb-am33xx"; + reg = <0x47400000 0x1000 /* usbss */ + 0x47401000 0x800 /* musb instance 0 */ + 0x47401800 0x800>; /* musb instance 1 */ + interrupts = <17 /* usbss */ + 18 /* musb instance 0 */ + 19>; /* musb instance 1 */ + multipoint = <1>; + num-eps = <16>; + ram-bits = <12>; + port0-mode = <3>; + port1-mode = <3>; + power = <250>; + ti,hwmods = "usb_otg_hs"; + }; }; }; From 7340dd530c5f72e63201953677b42c9e5fdb2b3d Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 6 Nov 2012 15:52:23 +0100 Subject: [PATCH 45/71] ARM: dts: Makefile: Add the am335x-evmsk target in dtbs list The EVMSK was not built with the 'make dtbs' command. Add the missing entry in the dts Makefile. Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 634bd4246574..2458b69e2be6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap4-sdp.dtb \ omap5-evm.dtb \ am335x-evm.dtb \ + am335x-evmsk.dtb \ am335x-bone.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_U8500) += snowball.dtb From 0d9250c4cb2387436c0ccc7a580f6cb4f3544e40 Mon Sep 17 00:00:00 2001 From: Ricardo Neri Date: Mon, 5 Nov 2012 15:14:14 +0200 Subject: [PATCH 46/71] ARM: dts: omap4-panda: Add pinmux configuration for HDMI Add the pinmux configuration for HDMI and TPD12S015A. Configure the gpios for the TPD12S015A and SDA, SCL and CEC for HDMI. Signed-off-by: Ricardo Neri Signed-off-by: Tomi Valkeinen Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4-panda-a4.dts | 17 +++++++++++++++++ arch/arm/boot/dts/omap4-panda-es.dts | 9 +++++++++ arch/arm/boot/dts/omap4-panda.dts | 18 ++++++++++++++++++ 3 files changed, 44 insertions(+) create mode 100644 arch/arm/boot/dts/omap4-panda-a4.dts diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts new file mode 100644 index 000000000000..75466d2abfb5 --- /dev/null +++ b/arch/arm/boot/dts/omap4-panda-a4.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/include/ "omap4-panda.dts" + +/* Pandaboard Rev A4+ have external pullups on SCL & SDA */ +&dss_hdmi_pins { + pinctrl-single,pins = < + 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ + 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */ + 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */ + >; +}; diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index d4ba43a48d9b..73bc1a67e444 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -22,3 +22,12 @@ "AFML", "Line In", "AFMR", "Line In"; }; + +/* PandaboardES has external pullups on SCL & SDA */ +&dss_hdmi_pins { + pinctrl-single,pins = < + 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ + 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */ + 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */ + >; +}; diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index 32baf65a7ea2..4122efe31cfd 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts @@ -65,6 +65,8 @@ &twl6040_pins &mcpdm_pins &mcbsp1_pins + &dss_hdmi_pins + &tpd12s015_pins >; twl6040_pins: pinmux_twl6040_pins { @@ -92,6 +94,22 @@ 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ >; }; + + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < + 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ + 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */ + 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */ + >; + }; + + tpd12s015_pins: pinmux_tpd12s015_pins { + pinctrl-single,pins = < + 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */ + 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */ + 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */ + >; + }; }; &i2c1 { From 347bf48f2b5d2b45a4e42b89dd61b27ca8baced4 Mon Sep 17 00:00:00 2001 From: Ricardo Neri Date: Mon, 5 Nov 2012 15:14:15 +0200 Subject: [PATCH 47/71] ARM: dts: omap4-sdp: Add pinmux configuration for HDMI Add the pinmux configuration for HDMI and TPD12S015A. Configure the gpios for the TPD12S015A and SDA, SCL and CEC for HDMI. Signed-off-by: Ricardo Neri Signed-off-by: Tomi Valkeinen Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4-sdp-es23plus.dts | 17 +++++++++++++++++ arch/arm/boot/dts/omap4-sdp.dts | 18 ++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 arch/arm/boot/dts/omap4-sdp-es23plus.dts diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts new file mode 100644 index 000000000000..b4a40ffbce31 --- /dev/null +++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/include/ "omap4-sdp.dts" + +/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */ +&dss_hdmi_pins { + pinctrl-single,pins = < + 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ + 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */ + 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */ + >; +}; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 0f57bdf7c2df..43e5258a9372 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -124,6 +124,8 @@ &dmic_pins &mcbsp1_pins &mcbsp2_pins + &dss_hdmi_pins + &tpd12s015_pins >; uart2_pins: pinmux_uart2_pins { @@ -194,6 +196,22 @@ 0xbc 0x100 /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */ >; }; + + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < + 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ + 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */ + 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */ + >; + }; + + tpd12s015_pins: pinmux_tpd12s015_pins { + pinctrl-single,pins = < + 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */ + 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */ + 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */ + >; + }; }; &i2c1 { From 5a2bc4c6607c709aa69f508502e33aebbf32f1f5 Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Tue, 6 Nov 2012 19:26:06 +0530 Subject: [PATCH 48/71] usb: musb: dsps: dt binding - add resources, example OMAP2+ family of devices are now obtaining resources via DT, earlier it was obtained from hwmod. Update binding document accrodingly, while at it add example. Signed-off-by: Afzal Mohammed Reviewed-by: Felipe Balbi Signed-off-by: Benoit Cousson --- .../devicetree/bindings/usb/am33xx-usb.txt | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/am33xx-usb.txt b/Documentation/devicetree/bindings/usb/am33xx-usb.txt index ca8fa56e9f03..707c1a2dae06 100644 --- a/Documentation/devicetree/bindings/usb/am33xx-usb.txt +++ b/Documentation/devicetree/bindings/usb/am33xx-usb.txt @@ -1,5 +1,7 @@ AM33XX MUSB GLUE - compatible : Should be "ti,musb-am33xx" + - reg : offset and length of register sets, first usbss, then for musb instances + - interrupts : usbss, musb instance interrupts in order - ti,hwmods : must be "usb_otg_hs" - multipoint : Should be "1" indicating the musb controller supports multipoint. This is a MUSB configuration-specific setting. @@ -12,3 +14,22 @@ AM33XX MUSB GLUE represents PERIPHERAL. - power : Should be "250". This signifies the controller can supply upto 500mA when operating in host mode. + +Example: + +usb@47400000 { + compatible = "ti,musb-am33xx"; + reg = <0x47400000 0x1000 /* usbss */ + 0x47401000 0x800 /* musb instance 0 */ + 0x47401800 0x800>; /* musb instance 1 */ + interrupts = <17 /* usbss */ + 18 /* musb instance 0 */ + 19>; /* musb instance 1 */ + multipoint = <1>; + num-eps = <16>; + ram-bits = <12>; + port0-mode = <3>; + port1-mode = <3>; + power = <250>; + ti,hwmods = "usb_otg_hs"; +}; From 971d0254480572bc6dc5574c28ef8fe014660a31 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 27 Sep 2012 11:49:45 -0500 Subject: [PATCH 49/71] ARM: OMAP: Add DMTIMER definitions for posted mode For OMAP2+ devices, when using DMTIMERs for system timers (clock-events and clock-source) the posted mode configuration of the timers is used. To allow the compiler to optimise the functions for configuring and reading the system timers, the posted flag variable is hard-coded with the value 1. To make it clear that posted mode is being used add some definitions so that it is more readable. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/mach-omap2/timer.c | 17 ++++++++++------- arch/arm/plat-omap/include/plat/dmtimer.h | 4 ++++ 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 684d2fc3d485..a135d28e202c 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -108,7 +108,7 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, - 0xffffffff - cycles, 1); + 0xffffffff - cycles, OMAP_TIMER_POSTED); return 0; } @@ -118,7 +118,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, { u32 period; - __omap_dm_timer_stop(&clkev, 1, clkev.rate); + __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: @@ -126,10 +126,10 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, period -= 1; /* Looks like we need to first set the load value separately */ __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, - 0xffffffff - period, 1); + 0xffffffff - period, OMAP_TIMER_POSTED); __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, - 0xffffffff - period, 1); + 0xffffffff - period, OMAP_TIMER_POSTED); break; case CLOCK_EVT_MODE_ONESHOT: break; @@ -359,7 +359,8 @@ static bool use_gptimer_clksrc; */ static cycle_t clocksource_read_cycles(struct clocksource *cs) { - return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); + return (cycle_t)__omap_dm_timer_read_counter(&clksrc, + OMAP_TIMER_POSTED); } static struct clocksource clocksource_gpt = { @@ -373,7 +374,8 @@ static struct clocksource clocksource_gpt = { static u32 notrace dmtimer_read_sched_clock(void) { if (clksrc.reserved) - return __omap_dm_timer_read_counter(&clksrc, 1); + return __omap_dm_timer_read_counter(&clksrc, + OMAP_TIMER_POSTED); return 0; } @@ -455,7 +457,8 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id, BUG_ON(res); __omap_dm_timer_load_start(&clksrc, - OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); + OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, + OMAP_TIMER_POSTED); setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index f8943c8f9dbf..1bee0ac88760 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -55,6 +55,10 @@ #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 +/* posted mode types */ +#define OMAP_TIMER_NONPOSTED 0x00 +#define OMAP_TIMER_POSTED 0x01 + /* timer capabilities used in hwmod database */ #define OMAP_TIMER_SECURE 0x80000000 #define OMAP_TIMER_ALWON 0x40000000 From bfd6d021120d5994c4cc94d87ec03642be1540e7 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 27 Sep 2012 12:47:43 -0500 Subject: [PATCH 50/71] ARM: OMAP3+: Implement timer workaround for errata i103 and i767 Errata Titles: i103: Delay needed to read some GP timer, WD timer and sync timer registers after wakeup (OMAP3/4) i767: Delay needed to read some GP timer registers after wakeup (OMAP5) Description (i103/i767): If a General Purpose Timer (GPTimer) is in posted mode (TSICR [2].POSTED=1), due to internal resynchronizations, values read in TCRR, TCAR1 and TCAR2 registers right after the timer interface clock (L4) goes from stopped to active may not return the expected values. The most common event leading to this situation occurs upon wake up from idle. GPTimer non-posted synchronization mode is not impacted by this limitation. Workarounds: 1). Disable posted mode 2). Use static dependency between timer clock domain and MPUSS clock domain 3). Use no-idle mode when the timer is active Workarounds #2 and #3 are not pratical from a power standpoint and so workaround #1 has been implemented. Disabling posted mode adds some CPU overhead for configuring and reading the timers as the CPU has to wait for accesses to be re-synchronised within the timer. However, disabling posted mode guarantees correct operation. Please note that it is safe to use posted mode for timers if the counter (TCRR) and capture (TCARx) registers will never be read. An example of this is the clock-event system timer. This is used by the kernel to schedule events however, the timers counter is never read and capture registers are not used. Given that the kernel configures this timer often yet never reads the counter register it is safe to enable posted mode in this case. Hence, for the timer used for kernel clock-events, posted mode is enabled by overriding the errata for devices that are impacted by this defect. For drivers using the timers that do not read the counter or capture registers and wish to use posted mode, can override the errata and enable posted mode by making the following function calls. __omap_dm_timer_override_errata(timer, OMAP_TIMER_ERRATA_I103_I767); __omap_dm_timer_enable_posted(timer); Both dmtimers and watchdogs are impacted by this defect this patch only implements the workaround for the dmtimer. Currently the watchdog driver does not read the counter register and so no workaround is necessary. Posted mode will be disabled for all OMAP2+ devices (including AM33xx) using a GP timer as a clock-source timer to guarantee correct operation. This is not necessary for OMAP24xx devices but the default clock-source timer for OMAP24xx devices is the 32k-sync timer and not the GP timer and so should not have any impact. This should be re-visited for future devices if this errata is fixed. Confirmed with Vaibhav Hiremath that this bug also impacts AM33xx devices. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/mach-omap2/timer.c | 49 +++++++++++++++++---- arch/arm/plat-omap/dmtimer.c | 3 +- arch/arm/plat-omap/include/plat/dmtimer.h | 52 ++++++++++++++++++++++- 3 files changed, 93 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index a135d28e202c..63229c5287e6 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -222,10 +222,24 @@ void __init omap_dmtimer_init(void) } } +/** + * omap_dm_timer_get_errata - get errata flags for a timer + * + * Get the timer errata flags that are specific to the OMAP device being used. + */ +u32 __init omap_dm_timer_get_errata(void) +{ + if (cpu_is_omap24xx()) + return 0; + + return OMAP_TIMER_ERRATA_I103_I767; +} + static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, int gptimer_id, const char *fck_source, - const char *property) + const char *property, + int posted) { char name[10]; /* 10 = sizeof("gptXX_Xck0") */ const char *oh_name; @@ -311,10 +325,15 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, } __omap_dm_timer_init_regs(timer); __omap_dm_timer_reset(timer, 1, 1); - timer->posted = 1; + + if (posted) + __omap_dm_timer_enable_posted(timer); + + /* Check that the intended posted configuration matches the actual */ + if (posted != timer->posted) + return -EINVAL; timer->rate = clk_get_rate(timer->fclk); - timer->reserved = 1; return res; @@ -326,7 +345,17 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, { int res; - res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property); + clkev.errata = omap_dm_timer_get_errata(); + + /* + * For clock-event timers we never read the timer counter and + * so we are not impacted by errata i103 and i767. Therefore, + * we can safely ignore this errata for clock-event timers. + */ + __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); + + res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property, + OMAP_TIMER_POSTED); BUG_ON(res); omap2_gp_timer_irq.dev_id = &clkev; @@ -360,7 +389,7 @@ static bool use_gptimer_clksrc; static cycle_t clocksource_read_cycles(struct clocksource *cs) { return (cycle_t)__omap_dm_timer_read_counter(&clksrc, - OMAP_TIMER_POSTED); + OMAP_TIMER_NONPOSTED); } static struct clocksource clocksource_gpt = { @@ -375,7 +404,7 @@ static u32 notrace dmtimer_read_sched_clock(void) { if (clksrc.reserved) return __omap_dm_timer_read_counter(&clksrc, - OMAP_TIMER_POSTED); + OMAP_TIMER_NONPOSTED); return 0; } @@ -453,12 +482,15 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id, { int res; - res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL); + clksrc.errata = omap_dm_timer_get_errata(); + + res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL, + OMAP_TIMER_NONPOSTED); BUG_ON(res); __omap_dm_timer_load_start(&clksrc, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, - OMAP_TIMER_POSTED); + OMAP_TIMER_NONPOSTED); setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) @@ -696,6 +728,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) if (timer_dev_attr) pdata->timer_capability = timer_dev_attr->timer_capability; + pdata->timer_errata = omap_dm_timer_get_errata(); pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 9dca23e4d6b0..381a612e6a1d 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -128,8 +128,8 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer) } __omap_dm_timer_reset(timer, 0, 0); + __omap_dm_timer_enable_posted(timer); omap_dm_timer_disable(timer); - timer->posted = 1; } int omap_dm_timer_prepare(struct omap_dm_timer *timer) @@ -797,6 +797,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev) timer->capability |= OMAP_TIMER_SECURE; } else { timer->id = pdev->id; + timer->errata = pdata->timer_errata; timer->capability = pdata->timer_capability; timer->reserved = omap_dm_timer_reserved_systimer(timer->id); timer->get_context_loss_count = pdata->get_context_loss_count; diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 1bee0ac88760..ac16f1e9d0e0 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -66,6 +66,16 @@ #define OMAP_TIMER_NEEDS_RESET 0x10000000 #define OMAP_TIMER_HAS_DSP_IRQ 0x08000000 +/* + * timer errata flags + * + * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This + * errata prevents us from using posted mode on these devices, unless the + * timer counter register is never read. For more details please refer to + * the OMAP3/4/5 errata documents. + */ +#define OMAP_TIMER_ERRATA_I103_I767 0x80000000 + struct omap_timer_capability_dev_attr { u32 timer_capability; }; @@ -97,6 +107,7 @@ struct timer_regs { struct dmtimer_platform_data { /* set_timer_src - Only used for OMAP1 devices */ int (*set_timer_src)(struct platform_device *pdev, int source); + u32 timer_errata; u32 timer_capability; int (*get_context_loss_count)(struct device *); }; @@ -273,6 +284,7 @@ struct omap_dm_timer { int ctx_loss_count; int revision; u32 capability; + u32 errata; struct platform_device *pdev; struct list_head node; }; @@ -344,10 +356,46 @@ static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer, l |= 1 << 2; __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); +} + +/* + * __omap_dm_timer_enable_posted - enables write posted mode + * @timer: pointer to timer instance handle + * + * Enables the write posted mode for the timer. When posted mode is enabled + * writes to certain timer registers are immediately acknowledged by the + * internal bus and hence prevents stalling the CPU waiting for the write to + * complete. Enabling this feature can improve performance for writing to the + * timer registers. + */ +static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer) +{ + if (timer->posted) + return; + + if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) + return; - /* Match hardware reset default of posted mode */ __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, - OMAP_TIMER_CTRL_POSTED, 0); + OMAP_TIMER_CTRL_POSTED, 0); + timer->context.tsicr = OMAP_TIMER_CTRL_POSTED; + timer->posted = OMAP_TIMER_POSTED; +} + +/** + * __omap_dm_timer_override_errata - override errata flags for a timer + * @timer: pointer to timer handle + * @errata: errata flags to be ignored + * + * For a given timer, override a timer errata by clearing the flags + * specified by the errata argument. A specific erratum should only be + * overridden for a timer if the timer is used in such a way the erratum + * has no impact. + */ +static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer, + u32 errata) +{ + timer->errata &= ~errata; } static inline int __omap_dm_timer_set_source(struct clk *timer_fck, From 7b44cf2c15f81caf5c3a4ac59f0677edd64b9aeb Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 6 Jul 2012 16:45:04 -0500 Subject: [PATCH 51/71] ARM: OMAP: Fix timer posted mode support Currently the dmtimer posted mode is being enabled when the function omap_dm_timer_enable_posted() is called. This function is only being called for OMAP1 timers and OMAP2+ timers that are being used as system timers. Hence, for OMAP2+ timers that are NOT being used as a system timer, posted mode is not enabled but the "timer->posted" variable is still set (incorrectly) in the omap_dm_timer_prepare() function. This is a regression introduced by commit 3392cdd3 (ARM: OMAP: dmtimer: switch-over to platform device driver) which was before the omap_dm_timer_enable_posted() function was introduced. Although this is a regression from the original code it only impacts performance and so is not needed for stable. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/plat-omap/dmtimer.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 381a612e6a1d..10ec31b8a3a2 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -121,21 +121,16 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) static void omap_dm_timer_reset(struct omap_dm_timer *timer) { - omap_dm_timer_enable(timer); if (timer->pdev->id != 1) { omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); omap_dm_timer_wait_for_reset(timer); } __omap_dm_timer_reset(timer, 0, 0); - __omap_dm_timer_enable_posted(timer); - omap_dm_timer_disable(timer); } int omap_dm_timer_prepare(struct omap_dm_timer *timer) { - int ret; - /* * FIXME: OMAP1 devices do not use the clock framework for dmtimers so * do not call clk_get() for these devices. @@ -149,13 +144,15 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer) } } + omap_dm_timer_enable(timer); + if (timer->capability & OMAP_TIMER_NEEDS_RESET) omap_dm_timer_reset(timer); - ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); + __omap_dm_timer_enable_posted(timer); + omap_dm_timer_disable(timer); - timer->posted = 1; - return ret; + return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); } static inline u32 omap_dm_timer_reserved_systimer(int id) From 725a8fe3126e3d384cb51fc1029a4a92b0b8e5f5 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 28 Aug 2012 12:49:39 -0500 Subject: [PATCH 52/71] ARM: OMAP3: Correct HWMOD DMTIMER SYSC register declarations Currently, the OMAP3 HWMOD data defines two TIOCP_CFG register structures (referred to as the SYSC register in the HWMOD data) where timers 1, 2 and 10 use one of the defintions and the other timers use the other definition. For OMAP3 devices the structure of the DMTIMER TIOCP_CFG register is the same for all 12 instances of the DMTIMER. Please note that this is a difference between OMAP3 and OMAP4 and could be the source of the confusion. For OMAP3 devices, the DMTIMER TIOCP_CFG register has the fields, clock-activity, emufree, idlemode, enwakeup, softreset and autoidle for all 12 timers. Therefore, remove one of the SYSC register definitions for the DMTIMERs and ensure the appropriate register fields are defined for all DMTIMERs. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 27 +++++----------------- 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index abe66ced903f..fac255058c81 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -153,28 +153,13 @@ static struct omap_hwmod omap3xxx_debugss_hwmod = { }; /* timer class */ -static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { - .name = "timer", - .sysc = &omap3xxx_timer_1ms_sysc, -}; - static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { .rev_offs = 0x0000, .sysc_offs = 0x0010, .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), .sysc_fields = &omap_hwmod_sysc_type1, }; @@ -224,7 +209,7 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .class = &omap3xxx_timer_1ms_hwmod_class, + .class = &omap3xxx_timer_hwmod_class, }; /* timer2 */ @@ -241,7 +226,7 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, }, }, - .class = &omap3xxx_timer_1ms_hwmod_class, + .class = &omap3xxx_timer_hwmod_class, }; /* timer3 */ @@ -383,7 +368,7 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .class = &omap3xxx_timer_1ms_hwmod_class, + .class = &omap3xxx_timer_hwmod_class, }; /* timer11 */ From f3a13e7246f92e0cf4e9e3baee3145693ba41a8d Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 28 Aug 2012 12:55:27 -0500 Subject: [PATCH 53/71] ARM: OMAP2/3: Define HWMOD software reset status for DMTIMERs For OMAP2/3 devices, the HWMOD data does not define a software reset status field for the DMTIMERs. Therefore, when HWMOD performs a soft-reset of the DMTIMER we don't check and wait for the reset to complete. For OMAP2/3 devices, the software reset status for a DMTIMER can be read from bit 0 of the DMTIMER TISTAT register (referred to as the SYSS register in HWMOD). Add the appropriate HWMOD definitions so that HWMOD will check the software reset status when performing a software reset of the DMTIMER. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 2 +- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index a0116d08cf45..067fd0ae4b07 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -58,7 +58,7 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { .syss_offs = 0x0014, .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), .sysc_fields = &omap_hwmod_sysc_type1, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index fac255058c81..fcce693a1edc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -159,7 +159,8 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { .syss_offs = 0x0014, .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), .sysc_fields = &omap_hwmod_sysc_type1, }; From 10759e823c83e6c88b58264daa791bb82c7ebad9 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 11 Jul 2012 13:00:13 -0500 Subject: [PATCH 54/71] ARM: OMAP2+: Don't use __omap_dm_timer_reset() Currently OMAP2+ devices are using the function __omap_dm_timer_reset() to configure the clock-activity, idle, wakeup-enable and auto-idle fields in the timer OCP_CFG register. The name of the function is mis-leading because this function does not actually perform a reset of the timer. For OMAP2+ devices, HWMOD is responsible for reseting and configuring the timer OCP_CFG register. Therefore, do not use __omap_dm_timer_reset() for OMAP2+ devices and rely on HWMOD. Furthermore, some timer instances do not have the fields clock-activity, wakeup-enable and auto-idle and so this function could configure the OCP_CFG register incorrectly. Currently HWMOD is not configuring the clock-activity field in the OCP_CFG register for timers that have this field. Commit 0f0d080 (ARM: OMAP: DMTimer: Use posted mode) configures the clock-activity field to keep the f-clk enabled so that the wake-up capability is enabled. Therefore, add the appropriate flags to the timer HWMOD structures to configure this field in the same way. For OMAP2/3 devices all dmtimers have the clock-activity field, where as for OMAP4 devices, only dmtimer 1, 2 and 10 have the clock-activity field. Verified on OMAP2420 H4, OMAP3430 Beagle and OMAP4430 Panda that HWMOD is configuring the dmtimer OCP_CFG register as expected for clock-events timer. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 13 +++++++++++++ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 13 +++++++++++++ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 4 ++++ arch/arm/mach-omap2/timer.c | 1 - 4 files changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 067fd0ae4b07..0db8f450bad9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -60,6 +60,7 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .clockact = CLOCKACT_TEST_ICLK, .sysc_fields = &omap_hwmod_sysc_type1, }; @@ -268,6 +269,7 @@ struct omap_hwmod omap2xxx_timer1_hwmod = { }, .dev_attr = &capability_alwon_dev_attr, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer2 */ @@ -286,6 +288,7 @@ struct omap_hwmod omap2xxx_timer2_hwmod = { }, }, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer3 */ @@ -304,6 +307,7 @@ struct omap_hwmod omap2xxx_timer3_hwmod = { }, }, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer4 */ @@ -322,6 +326,7 @@ struct omap_hwmod omap2xxx_timer4_hwmod = { }, }, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer5 */ @@ -341,6 +346,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = { }, .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer6 */ @@ -360,6 +366,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = { }, .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer7 */ @@ -379,6 +386,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = { }, .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer8 */ @@ -398,6 +406,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = { }, .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer9 */ @@ -417,6 +426,7 @@ struct omap_hwmod omap2xxx_timer9_hwmod = { }, .dev_attr = &capability_pwm_dev_attr, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer10 */ @@ -436,6 +446,7 @@ struct omap_hwmod omap2xxx_timer10_hwmod = { }, .dev_attr = &capability_pwm_dev_attr, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer11 */ @@ -455,6 +466,7 @@ struct omap_hwmod omap2xxx_timer11_hwmod = { }, .dev_attr = &capability_pwm_dev_attr, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer12 */ @@ -474,6 +486,7 @@ struct omap_hwmod omap2xxx_timer12_hwmod = { }, .dev_attr = &capability_pwm_dev_attr, .class = &omap2xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* wd_timer2 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index fcce693a1edc..addc1c24ca2e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -162,6 +162,7 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .clockact = CLOCKACT_TEST_ICLK, .sysc_fields = &omap_hwmod_sysc_type1, }; @@ -211,6 +212,7 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = { }, .dev_attr = &capability_alwon_dev_attr, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer2 */ @@ -228,6 +230,7 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = { }, }, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer3 */ @@ -245,6 +248,7 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = { }, }, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer4 */ @@ -262,6 +266,7 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = { }, }, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer5 */ @@ -280,6 +285,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = { }, .dev_attr = &capability_dsp_dev_attr, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer6 */ @@ -298,6 +304,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = { }, .dev_attr = &capability_dsp_dev_attr, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer7 */ @@ -316,6 +323,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = { }, .dev_attr = &capability_dsp_dev_attr, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer8 */ @@ -334,6 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = { }, .dev_attr = &capability_dsp_pwm_dev_attr, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer9 */ @@ -352,6 +361,7 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = { }, .dev_attr = &capability_pwm_dev_attr, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer10 */ @@ -370,6 +380,7 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = { }, .dev_attr = &capability_pwm_dev_attr, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer11 */ @@ -388,6 +399,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { }, .dev_attr = &capability_pwm_dev_attr, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* timer12 */ @@ -411,6 +423,7 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = { }, .dev_attr = &capability_secure_dev_attr, .class = &omap3xxx_timer_hwmod_class, + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 7a6132848f5d..399f4ce9cab1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -3067,6 +3067,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .clockact = CLOCKACT_TEST_ICLK, .sysc_fields = &omap_hwmod_sysc_type1, }; @@ -3120,6 +3121,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { .name = "timer1", .class = &omap44xx_timer_1ms_hwmod_class, .clkdm_name = "l4_wkup_clkdm", + .flags = HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_timer1_irqs, .main_clk = "timer1_fck", .prcm = { @@ -3142,6 +3144,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { .name = "timer2", .class = &omap44xx_timer_1ms_hwmod_class, .clkdm_name = "l4_per_clkdm", + .flags = HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_timer2_irqs, .main_clk = "timer2_fck", .prcm = { @@ -3316,6 +3319,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { .name = "timer10", .class = &omap44xx_timer_1ms_hwmod_class, .clkdm_name = "l4_per_clkdm", + .flags = HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_timer10_irqs, .main_clk = "timer10_fck", .prcm = { diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 63229c5287e6..19765bd96c8e 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -324,7 +324,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, } } __omap_dm_timer_init_regs(timer); - __omap_dm_timer_reset(timer, 1, 1); if (posted) __omap_dm_timer_enable_posted(timer); From ffc957bd83b623fa6ead068bf1a444decce2cc00 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 6 Jul 2012 16:46:35 -0500 Subject: [PATCH 55/71] ARM: OMAP: Fix dmtimer reset for timer1 In commit e32f7ec2 (ARM: OMAP: Fix 32 kHz timer and modify GP timer to use GPT1) a fix was added to prevent timer1 being reset in the function omap_dm_timer_reset() because timer1 was being used as the system timer for OMAP2 devices. Although timer1 is still used by most OMAP2+ devices as a system timer, the function omap_dm_timer_reset() is now only being called for OMAP1 devices and OMAP1 does not use timer1 as a system timer. Therefore, remove the check in omap_dm_timer_reset() so that timer1 is reset for OMAP1 devices. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/plat-omap/dmtimer.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 10ec31b8a3a2..d4f95410539f 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -121,11 +121,8 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) static void omap_dm_timer_reset(struct omap_dm_timer *timer) { - if (timer->pdev->id != 1) { - omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); - omap_dm_timer_wait_for_reset(timer); - } - + omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); + omap_dm_timer_wait_for_reset(timer); __omap_dm_timer_reset(timer, 0, 0); } From d3004bb43de180c2f6e965716a3abe9b43c8b861 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 28 Sep 2012 16:09:03 -0500 Subject: [PATCH 56/71] ARM: OMAP: Don't restore of DMTIMER TISTAT register The timer TISTAT register is a read-only register and therefore restoring the context is not needed. Furthermore, the context of TISTAT is never saved anywhere in the current code. The TISTAT register is read-only for all OMAP devices from OMAP1 to OMAP4. OMAP5 timers no longer have this register. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/plat-omap/dmtimer.c | 3 --- arch/arm/plat-omap/include/plat/dmtimer.h | 1 - 2 files changed, 4 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index d4f95410539f..320d10381715 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -83,9 +83,6 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, static void omap_timer_restore_context(struct omap_dm_timer *timer) { - if (timer->revision == 1) - __raw_writel(timer->context.tistat, timer->sys_stat); - __raw_writel(timer->context.tisr, timer->irq_stat); omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer); diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index ac16f1e9d0e0..2f9fd1d27aef 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -84,7 +84,6 @@ struct omap_dm_timer; struct timer_regs { u32 tidr; - u32 tistat; u32 tisr; u32 tier; u32 twer; From 1eaff71017d97ce2bc8e22b9a5cf11e5c6dd6c78 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 4 Oct 2012 17:01:14 -0500 Subject: [PATCH 57/71] ARM: OMAP: Don't restore DMTIMER interrupt status register Restoring the timer interrupt status is not possible because writing a 1 to any bit in the register clears that bit if set and writing a 0 has no affect. Furthermore, if an interrupt is pending when someone attempts to disable a timer, the timer will fail to transition to the idle state and hence it's context will not be lost. Users should take care to service all interrupts before disabling the timer. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/plat-omap/dmtimer.c | 5 +---- arch/arm/plat-omap/include/plat/dmtimer.h | 1 - 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 320d10381715..f0a3c4c72a42 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -83,7 +83,6 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, static void omap_timer_restore_context(struct omap_dm_timer *timer) { - __raw_writel(timer->context.tisr, timer->irq_stat); omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer); omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, @@ -440,7 +439,6 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer) */ timer->context.tclr = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); - timer->context.tisr = __raw_readl(timer->irq_stat); omap_dm_timer_disable(timer); return 0; } @@ -684,8 +682,7 @@ int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) return -EINVAL; __omap_dm_timer_write_status(timer, value); - /* Save the context */ - timer->context.tisr = value; + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 2f9fd1d27aef..0c07e3753470 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -84,7 +84,6 @@ struct omap_dm_timer; struct timer_regs { u32 tidr; - u32 tisr; u32 tier; u32 twer; u32 tclr; From 991ad16a927c721b301f27aa9b61a13a24b54dda Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 4 Oct 2012 18:17:42 -0500 Subject: [PATCH 58/71] ARM: OMAP: Fix spurious interrupts when using timer match feature The OMAP DMTIMERs can generate an interrupt when the timer counter value matches the value stored in the timer's match register. When using this feature spurious interrupts were seen, because the compare logic is being enabled before the match value is loaded and according to the documentation the match value must be loaded before the compare logic is enable. The reset value for the timer counter and match registers is 0 and hence, by enabling the compare logic before the actual match value is loaded a spurious interrupt can be generated as the reset values match. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/plat-omap/dmtimer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index f0a3c4c72a42..a38e8964c820 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -584,8 +584,8 @@ int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, l |= OMAP_TIMER_CTRL_CE; else l &= ~OMAP_TIMER_CTRL_CE; - omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); + omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); /* Save the context */ timer->context.tclr = l; From 4249d96ca35a765c25a70b7d29df5b6d80987c7f Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 13 Jul 2012 14:03:18 -0500 Subject: [PATCH 59/71] ARM: OMAP: Add dmtimer interrupt disable function The OMAP dmtimer driver does not currently have a function to disable the timer interrupts. For some timer instances the timer interrupt enable function can be used to disable the interrupts because the same interrupt enable register is used to disable interrupts. However, some timer instances have separate interrupt enable/disable registers and so this will not work. Therefore, add a dedicated function to disable interrupts. This change is required for OMAP4+ devices. For OMAP4, all timers apart from 1, 2 and 10 need this function and for OMAP5 all timers need this function. Please note that the interrupt disable function has been written so that it can be used by all OMAP devices. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/plat-omap/dmtimer.c | 31 +++++++++++++++++++++++ arch/arm/plat-omap/include/plat/dmtimer.h | 3 ++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index a38e8964c820..b4e6634380e5 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -661,6 +661,37 @@ int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, } EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); +/** + * omap_dm_timer_set_int_disable - disable timer interrupts + * @timer: pointer to timer handle + * @mask: bit mask of interrupts to be disabled + * + * Disables the specified timer interrupts for a timer. + */ +int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) +{ + u32 l = mask; + + if (unlikely(!timer)) + return -EINVAL; + + omap_dm_timer_enable(timer); + + if (timer->revision == 1) + l = __raw_readl(timer->irq_ena) & ~mask; + + __raw_writel(l, timer->irq_dis); + l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; + omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); + + /* Save the context */ + timer->context.tier &= ~mask; + timer->context.twer &= ~mask; + omap_dm_timer_disable(timer); + return 0; +} +EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable); + unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) { unsigned int l; diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 0c07e3753470..769efb6f30d5 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -135,6 +135,7 @@ int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, i int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); +int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask); unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer); int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); @@ -321,7 +322,7 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) OMAP_TIMER_V1_SYS_STAT_OFFSET; timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; - timer->irq_dis = NULL; + timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; timer->func_base = timer->io_base; } else { From d7aba5540d3f1aa2d7248d2f81506d994b25b327 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 18 Jul 2012 20:10:12 -0500 Subject: [PATCH 60/71] ARM: OMAP: Remove unnecessary call to clk_get() Whenever we call the function omap_dm_timer_set_source() to set the clock source of a dmtimer we look-up the dmtimer functional clock source by calling clk_get(). This is not necessary because on requesting a dmtimer we look-up the functional clock source and store it in the omap_dm_timer structure. So instead of looking up the clock again used the clock handle that stored in the omap_dm_timer structure. Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/plat-omap/dmtimer.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index b4e6634380e5..305faf539465 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -448,7 +448,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) { int ret; char *parent_name = NULL; - struct clk *fclk, *parent; + struct clk *parent; struct dmtimer_platform_data *pdata; if (unlikely(!timer)) @@ -467,11 +467,8 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) if (pdata && pdata->set_timer_src) return pdata->set_timer_src(timer->pdev, source); - fclk = clk_get(&timer->pdev->dev, "fck"); - if (IS_ERR_OR_NULL(fclk)) { - pr_err("%s: fck not found\n", __func__); + if (!timer->fclk) return -EINVAL; - } switch (source) { case OMAP_TIMER_SRC_SYS_CLK: @@ -490,18 +487,15 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) parent = clk_get(&timer->pdev->dev, parent_name); if (IS_ERR_OR_NULL(parent)) { pr_err("%s: %s not found\n", __func__, parent_name); - ret = -EINVAL; - goto out; + return -EINVAL; } - ret = clk_set_parent(fclk, parent); + ret = clk_set_parent(timer->fclk, parent); if (IS_ERR_VALUE(ret)) pr_err("%s: failed to set %s as parent\n", __func__, parent_name); clk_put(parent); -out: - clk_put(fclk); return ret; } From b1538832191d59e29b1077e64cf416a7617b45bc Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 28 Sep 2012 11:43:30 -0500 Subject: [PATCH 61/71] ARM: OMAP: Remove __omap_dm_timer_set_source function The __omap_dm_timer_set_source() function is only used by the system timer (clock-events and clock-source) code for OMAP2+ devices. Therefore, we can remove this code from the dmtimer driver and move it to the system timer code for OMAP2+ devices. The current __omap_dm_timer_set_source() function calls clk_disable() before calling clk_set_parent() and clk_enable() afterwards. We can avoid these calls to clk_disable/enable by moving the calls to omap_hwmod_setup_one() and omap_hwmod_enable() to after the call to clk_set_parent() in omap_dm_timer_init_one(). The function omap_hwmod_setup_one() will enable the timers functional clock and therefore increment the use-count of the functional clock to 1. clk_set_parent() will fail if the use-count is not 0 when called. Hence, if omap_hwmod_setup_one() is called before clk_set_parent(), we will need to call clk_disable() before calling clk_set_parent() to decrement the use-count. Hence, avoid these extra calls to disable and enable the functional clock by moving the calls to omap_hwmod_setup_one() and omap_hwmod_enable() to after clk_set_parent(). We can also remove the delay from the __omap_dm_timer_set_source() function because enabling the clock will now be handled via the HWMOD framework by calling omap_hwmod_setup_one(). Therefore, by moving the calls to omap_hwmod_setup_one() and omap_hwmod_enable() to after the call to clk_set_parent(), we can simply replace __omap_dm_timer_set_source() with clk_set_parent(). It should be safe to move these hwmod calls to later in the omap_dm_timer_init_one() because other calls to the hwmod layer that occur before are just requesting resource information. Testing includes boot testing on OMAP2420 H4, OMAP3430 SDP and OMAP4430 Blaze with the following configurations: 1. CONFIG_OMAP_32K_TIMER=y 2. CONFIG_OMAP_32K_TIMER=y and boot parameter "clocksource=gp_timer" 3. CONFIG_OMAP_32K_TIMER not set 4. CONFIG_OMAP_32K_TIMER not set and boot parameter "clocksource=gp_timer" Signed-off-by: Jon Hunter Acked-by: Santosh Shilimkar --- arch/arm/mach-omap2/timer.c | 9 ++++----- arch/arm/plat-omap/dmtimer.c | 1 + arch/arm/plat-omap/include/plat/dmtimer.h | 19 ------------------- 3 files changed, 5 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 19765bd96c8e..099e4060afe9 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -274,9 +274,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, oh_name = name; } - omap_hwmod_setup_one(oh_name); oh = omap_hwmod_lookup(oh_name); - if (!oh) return -ENODEV; @@ -306,8 +304,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, if (IS_ERR(timer->fclk)) return -ENODEV; - omap_hwmod_enable(oh); - /* FIXME: Need to remove hard-coded test on timer ID */ if (gptimer_id != 12) { struct clk *src; @@ -316,13 +312,16 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, if (IS_ERR(src)) { res = -EINVAL; } else { - res = __omap_dm_timer_set_source(timer->fclk, src); + res = clk_set_parent(timer->fclk, src); if (IS_ERR_VALUE(res)) pr_warn("%s: %s cannot set source\n", __func__, oh->name); clk_put(src); } } + + omap_hwmod_setup_one(oh_name); + omap_hwmod_enable(oh); __omap_dm_timer_init_regs(timer); if (posted) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 305faf539465..9deeb3064d33 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -35,6 +35,7 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ +#include #include #include #include diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 769efb6f30d5..05a36e16f3f4 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -32,7 +32,6 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include #include #include #include @@ -397,24 +396,6 @@ static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer, timer->errata &= ~errata; } -static inline int __omap_dm_timer_set_source(struct clk *timer_fck, - struct clk *parent) -{ - int ret; - - clk_disable(timer_fck); - ret = clk_set_parent(timer_fck, parent); - clk_enable(timer_fck); - - /* - * When the functional clock disappears, too quick writes seem - * to cause an abort. XXX Is this still necessary? - */ - __delay(300000); - - return ret; -} - static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer, int posted, unsigned long rate) { From ae6672cb47c8a7652e9aff182eb85a15994c9487 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 11 Jul 2012 13:47:38 -0500 Subject: [PATCH 62/71] ARM: OMAP: Clean-up dmtimer reset code Only OMAP1 devices use the omap_dm_timer_reset() and so require the omap_dm_timer_wait_for_reset() and __omap_dm_timer_reset() functions. Therefore combine these into a single function called omap_dm_timer_reset() and simplify the code. The omap_dm_timer_reset() function is now the only place that is using the omap_dm_timer structure member "sys_stat". Therefore, remove this member and just use the register offset definition to simplify and clean-up the code. The TISTAT register is only present on revision 1 timers and so check for this in the omap_dm_timer_reset() function. Please note that for OMAP1 devices, the TIOCP_CFG register does not have the clock-activity field and so when we reset the timer for an OMAP1 device we only need to configure the idle-mode field in the TIOCP_CFG register. Signed-off-by: Jon Hunter --- arch/arm/plat-omap/dmtimer.c | 52 ++++++++++++++--------- arch/arm/plat-omap/include/plat/dmtimer.h | 23 ---------- 2 files changed, 32 insertions(+), 43 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 9deeb3064d33..4c28452ba078 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -99,32 +99,39 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer) timer->context.tclr); } -static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) +static int omap_dm_timer_reset(struct omap_dm_timer *timer) { - int c; + u32 l, timeout = 100000; - if (!timer->sys_stat) - return; + if (timer->revision != 1) + return -EINVAL; - c = 0; - while (!(__raw_readl(timer->sys_stat) & 1)) { - c++; - if (c > 100000) { - printk(KERN_ERR "Timer failed to reset\n"); - return; - } - } -} - -static void omap_dm_timer_reset(struct omap_dm_timer *timer) -{ omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); - omap_dm_timer_wait_for_reset(timer); - __omap_dm_timer_reset(timer, 0, 0); + + do { + l = __omap_dm_timer_read(timer, + OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); + } while (!l && timeout--); + + if (!timeout) { + dev_err(&timer->pdev->dev, "Timer failed to reset\n"); + return -ETIMEDOUT; + } + + /* Configure timer for smart-idle mode */ + l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); + l |= 0x2 << 0x3; + __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); + + timer->posted = 0; + + return 0; } int omap_dm_timer_prepare(struct omap_dm_timer *timer) { + int rc; + /* * FIXME: OMAP1 devices do not use the clock framework for dmtimers so * do not call clk_get() for these devices. @@ -140,8 +147,13 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer) omap_dm_timer_enable(timer); - if (timer->capability & OMAP_TIMER_NEEDS_RESET) - omap_dm_timer_reset(timer); + if (timer->capability & OMAP_TIMER_NEEDS_RESET) { + rc = omap_dm_timer_reset(timer); + if (rc) { + omap_dm_timer_disable(timer); + return rc; + } + } __omap_dm_timer_enable_posted(timer); omap_dm_timer_disable(timer); diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 05a36e16f3f4..c5c890dabca4 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -267,7 +267,6 @@ struct omap_dm_timer { struct clk *fclk; void __iomem *io_base; - void __iomem *sys_stat; /* TISTAT timer status */ void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */ void __iomem *irq_ena; /* irq enable */ void __iomem *irq_dis; /* irq disable, only on v2 ip */ @@ -317,8 +316,6 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) tidr = __raw_readl(timer->io_base); if (!(tidr >> 16)) { timer->revision = 1; - timer->sys_stat = timer->io_base + - OMAP_TIMER_V1_SYS_STAT_OFFSET; timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; @@ -326,7 +323,6 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) timer->func_base = timer->io_base; } else { timer->revision = 2; - timer->sys_stat = NULL; timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS; timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR; @@ -337,25 +333,6 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) } } -/* Assumes the source clock has been set by caller */ -static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer, - int autoidle, int wakeup) -{ - u32 l; - - l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); - l |= 0x02 << 3; /* Set to smart-idle mode */ - l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */ - - if (autoidle) - l |= 0x1 << 0; - - if (wakeup) - l |= 1 << 2; - - __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); -} - /* * __omap_dm_timer_enable_posted - enables write posted mode * @timer: pointer to timer instance handle From b0cadb3c86fc99553b1f5c38c7770be1ad52aa26 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 28 Sep 2012 12:21:09 -0500 Subject: [PATCH 63/71] ARM: OMAP: Define omap_dm_timer_prepare function as static The omap_dm_timer_prepare function is a local function only used in the dmtimer.c file. Therefore, make this a static function and remove its declaration from the dmtimer.h file. Signed-off-by: Jon Hunter --- arch/arm/plat-omap/dmtimer.c | 2 +- arch/arm/plat-omap/include/plat/dmtimer.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 4c28452ba078..efe47744b491 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -128,7 +128,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *timer) return 0; } -int omap_dm_timer_prepare(struct omap_dm_timer *timer) +static int omap_dm_timer_prepare(struct omap_dm_timer *timer) { int rc; diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index c5c890dabca4..40383b68a099 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -286,8 +286,6 @@ struct omap_dm_timer { struct list_head node; }; -int omap_dm_timer_prepare(struct omap_dm_timer *timer); - static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, int posted) { From 61b001c564b75bfb47bfb84b33008fc2a35c9a84 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 28 Sep 2012 18:03:29 -0500 Subject: [PATCH 64/71] ARM: OMAP: Don't store timers physical address The OMAP2+ system timer code stores the physical address of the timer but never uses it. Remove this and clean-up the code by removing the local variable "size" and changing the names of the local variables mem_rsrc and irq_rsrc to mem and irq, respectively. Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/timer.c | 13 +++++-------- arch/arm/plat-omap/include/plat/dmtimer.h | 1 - 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 099e4060afe9..e9fcc5faff5c 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -245,8 +245,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, const char *oh_name; struct device_node *np; struct omap_hwmod *oh; - struct resource irq_rsrc, mem_rsrc; - size_t size; + struct resource irq, mem; int res = 0; int r; @@ -280,20 +279,18 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, if (!of_have_populated_dt()) { r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, - &irq_rsrc); + &irq); if (r) return -ENXIO; - timer->irq = irq_rsrc.start; + timer->irq = irq.start; r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, - &mem_rsrc); + &mem); if (r) return -ENXIO; - timer->phys_base = mem_rsrc.start; - size = mem_rsrc.end - mem_rsrc.start; /* Static mapping, never released */ - timer->io_base = ioremap(timer->phys_base, size); + timer->io_base = ioremap(mem.start, mem.end - mem.start); } if (!timer->io_base) diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 40383b68a099..b60e2b66ad18 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -261,7 +261,6 @@ int omap_dm_timers_active(void); (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) struct omap_dm_timer { - unsigned long phys_base; int id; int irq; struct clk *fclk; From f88095ba07c312fd4b309545553e1492cb227227 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 9 Nov 2012 17:07:39 -0600 Subject: [PATCH 65/71] ARM: OMAP2+: Remove unnecessary local variable in timer code The function omap_dm_timer_init_one() declares two local variables of type int that are used to store the return value of functions called. One such local variable is sufficient and so remove one of these local variables. Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/timer.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index e9fcc5faff5c..1a662dfdda11 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -246,8 +246,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, struct device_node *np; struct omap_hwmod *oh; struct resource irq, mem; - int res = 0; - int r; + int r = 0; if (of_have_populated_dt()) { np = omap_get_timer_dt(omap_timer_match, NULL); @@ -307,10 +306,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, src = clk_get(NULL, fck_source); if (IS_ERR(src)) { - res = -EINVAL; + r = -EINVAL; } else { - res = clk_set_parent(timer->fclk, src); - if (IS_ERR_VALUE(res)) + r = clk_set_parent(timer->fclk, src); + if (IS_ERR_VALUE(r)) pr_warn("%s: %s cannot set source\n", __func__, oh->name); clk_put(src); @@ -331,7 +330,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, timer->rate = clk_get_rate(timer->fclk); timer->reserved = 1; - return res; + return r; } static void __init omap2_gp_clockevent_init(int gptimer_id, From 755ae860f71cb37fbd3cc8da007e0d8de33419f0 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 28 Sep 2012 17:40:22 -0500 Subject: [PATCH 66/71] ARM: OMAP: Remove unnecessary omap_dm_timer structure declaration Remove unnecessary declaration of structure omap_dm_timer from dmtimer.h and move the actual declaration of structure omap_dm_timer towards top of dmtimer.h to avoid any compilation errors. Signed-off-by: Jon Hunter --- arch/arm/plat-omap/include/plat/dmtimer.h | 52 +++++++++++------------ 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index b60e2b66ad18..b3cd91b60a2e 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -79,8 +79,6 @@ struct omap_timer_capability_dev_attr { u32 timer_capability; }; -struct omap_dm_timer; - struct timer_regs { u32 tidr; u32 tier; @@ -101,6 +99,31 @@ struct timer_regs { u32 towr; }; +struct omap_dm_timer { + int id; + int irq; + struct clk *fclk; + + void __iomem *io_base; + void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */ + void __iomem *irq_ena; /* irq enable */ + void __iomem *irq_dis; /* irq disable, only on v2 ip */ + void __iomem *pend; /* write pending */ + void __iomem *func_base; /* function register base */ + + unsigned long rate; + unsigned reserved:1; + unsigned posted:1; + struct timer_regs context; + int (*get_context_loss_count)(struct device *); + int ctx_loss_count; + int revision; + u32 capability; + u32 errata; + struct platform_device *pdev; + struct list_head node; +}; + struct dmtimer_platform_data { /* set_timer_src - Only used for OMAP1 devices */ int (*set_timer_src)(struct platform_device *pdev, int source); @@ -260,31 +283,6 @@ int omap_dm_timers_active(void); #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) -struct omap_dm_timer { - int id; - int irq; - struct clk *fclk; - - void __iomem *io_base; - void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */ - void __iomem *irq_ena; /* irq enable */ - void __iomem *irq_dis; /* irq disable, only on v2 ip */ - void __iomem *pend; /* write pending */ - void __iomem *func_base; /* function register base */ - - unsigned long rate; - unsigned reserved:1; - unsigned posted:1; - struct timer_regs context; - int (*get_context_loss_count)(struct device *); - int ctx_loss_count; - int revision; - u32 capability; - u32 errata; - struct platform_device *pdev; - struct list_head node; -}; - static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, int posted) { From 40fc3bb56ed125aa22c0a85c816ae0f923519146 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 28 Sep 2012 11:34:49 -0500 Subject: [PATCH 67/71] ARM: OMAP: Add platform data header for DMTIMERs Move definition of dmtimer platform data structure in to its own header under . Signed-off-by: Jon Hunter --- arch/arm/mach-omap1/timer.c | 1 + arch/arm/mach-omap2/timer.c | 2 ++ arch/arm/plat-omap/dmtimer.c | 2 ++ arch/arm/plat-omap/include/plat/dmtimer.h | 8 ------ include/linux/platform_data/dmtimer-omap.h | 31 ++++++++++++++++++++++ 5 files changed, 36 insertions(+), 8 deletions(-) create mode 100644 include/linux/platform_data/dmtimer-omap.h diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index cdeb9d3ef640..bde7a35e5000 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -25,6 +25,7 @@ #include #include #include +#include #include diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 1a662dfdda11..4daa8b41c522 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -39,6 +39,8 @@ #include #include #include +#include +#include #include #include diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index efe47744b491..89585c293554 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -43,6 +43,8 @@ #include #include #include +#include +#include #include diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index b3cd91b60a2e..a3fbc48c332e 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -124,14 +124,6 @@ struct omap_dm_timer { struct list_head node; }; -struct dmtimer_platform_data { - /* set_timer_src - Only used for OMAP1 devices */ - int (*set_timer_src)(struct platform_device *pdev, int source); - u32 timer_errata; - u32 timer_capability; - int (*get_context_loss_count)(struct device *); -}; - int omap_dm_timer_reserve_systimer(int id); struct omap_dm_timer *omap_dm_timer_request(void); struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); diff --git a/include/linux/platform_data/dmtimer-omap.h b/include/linux/platform_data/dmtimer-omap.h new file mode 100644 index 000000000000..a19b78d826e9 --- /dev/null +++ b/include/linux/platform_data/dmtimer-omap.h @@ -0,0 +1,31 @@ +/* + * DMTIMER platform data for TI OMAP platforms + * + * Copyright (C) 2012 Texas Instruments + * Author: Jon Hunter + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef __PLATFORM_DATA_DMTIMER_OMAP_H__ +#define __PLATFORM_DATA_DMTIMER_OMAP_H__ + +struct dmtimer_platform_data { + /* set_timer_src - Only used for OMAP1 devices */ + int (*set_timer_src)(struct platform_device *pdev, int source); + u32 timer_capability; + u32 timer_errata; + int (*get_context_loss_count)(struct device *); +}; + +#endif /* __PLATFORM_DATA_DMTIMER_OMAP_H__ */ From f7863f7924951f64068eb5214a3dbecde3807a9a Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Mon, 1 Oct 2012 15:12:29 -0500 Subject: [PATCH 68/71] ARM: OMAP: Remove unnecessary inclusion of dmtimer.h Some source files are including dmtimer.h but not actually using any dmtimer definitions or functions. Therefore, remove the inclusion dmtimer.h from these source files. Signed-off-by: Jon Hunter Acked-by: Omar Ramirez Luna --- arch/arm/mach-omap1/timer32k.c | 1 - arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 - arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 - arch/arm/mach-omap2/pm-debug.c | 1 - drivers/staging/tidspbridge/core/ue_deh.c | 1 - 5 files changed, 5 deletions(-) diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c index 89368195bf08..41152fadd4c0 100644 --- a/arch/arm/mach-omap1/timer32k.c +++ b/arch/arm/mach-omap1/timer32k.c @@ -51,7 +51,6 @@ #include #include -#include #include diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a8b3368dca3d..e8efe3d1da6c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -17,7 +17,6 @@ #include #include -#include #include "omap_hwmod.h" #include "l3_2xxx.h" diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index dc768c50e523..32d17e3fd727 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -18,7 +18,6 @@ #include #include -#include #include "omap_hwmod.h" #include "mmc.h" diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 3cf4fdfd7ab0..e2c291f52f92 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -30,7 +30,6 @@ #include "clock.h" #include "powerdomain.h" #include "clockdomain.h" -#include #include "omap-pm.h" #include "soc.h" diff --git a/drivers/staging/tidspbridge/core/ue_deh.c b/drivers/staging/tidspbridge/core/ue_deh.c index 3d28b2345fbd..6aea6f1b4982 100644 --- a/drivers/staging/tidspbridge/core/ue_deh.c +++ b/drivers/staging/tidspbridge/core/ue_deh.c @@ -19,7 +19,6 @@ #include #include -#include #include #include From 258e84af9799b8c81cf856dcbd8e2d4cc082741d Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 15 Nov 2012 13:09:03 -0600 Subject: [PATCH 69/71] ARM: OMAP2+: Fix compiler warning for 32k timer Commit "ARM: OMAP2+: Add device-tree support for 32kHz counter" added structure omap_counter_match to the OMAP2 timer code. When CONFIG_OMAP_32K_TIMER is not defined this structure generates the following as it is not used. CC arch/arm/mach-omap2/timer.o arch/arm/mach-omap2/timer.c:163:28: warning: 'omap_counter_match' defined but not used [-Wunused-variable] Move the definition of omap_counter_match to avoid this warning when CONFIG_OMAP_32K_TIMER is not set. Thanks to Kevin Hilman for tracking down and reporting this problem. Reported-by: Kevin Hilam Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/timer.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 4daa8b41c522..b7f43a28e41f 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -162,11 +162,6 @@ static struct of_device_id omap_timer_match[] __initdata = { { } }; -static struct of_device_id omap_counter_match[] __initdata = { - { .compatible = "ti,omap-counter32k", }, - { } -}; - /** * omap_get_timer_dt - get a timer using device-tree * @match - device-tree match structure for matching a device type @@ -406,6 +401,11 @@ static u32 notrace dmtimer_read_sched_clock(void) } #ifdef CONFIG_OMAP_32K_TIMER +static struct of_device_id omap_counter_match[] __initdata = { + { .compatible = "ti,omap-counter32k", }, + { } +}; + /* Setup free-running counter for clocksource */ static int __init omap2_sync32k_clocksource_init(void) { From 6f80b3bb8a0ae4ae376dbdc69acf1fca8b4e2c9c Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Tue, 20 Nov 2012 09:17:15 +0200 Subject: [PATCH 70/71] ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER CONFIG_OMAP_32K_TIMER is kind of standing on the single zImage way. Make OMAP2+ timer code independant from the CONFIG_OMAP_32K_TIMER setting. To remove the dependancy, several conversions/additions had to be done: 1) Timer initialization functions are named by the platform name and the clock source in use. This also makes it possible to define and use the GPTIMER as the clock source instead of the 32K timer on platforms that do not have the 32K timer ip block or the 32K timer is not wired on the board. Currently, the the timer is chosen in the machine_desc structure on per board basis. Later, DT should be used to choose the timer. 2) Settings under the CONFIG_OMAP_32K_TIMER option are used as defaults and those under !CONFIG_OMAP_32K_TIMER are removed. This removes the CONFIG_OMAP_32K_TIMER on OMAP2+ timer code. 3) Since we have all the timers defined inside machine_desc structure and we no longer need the fallback to gp_timer clock source in case 32k_timer clock source is unavailable (namely on AM33xx), we no longer need the #ifdef around omap2_sync32k_clocksource_init() function. Remove the #ifdef CONFIG_OMAP_32K_TIMER around the omap2_sync32k_clocksource_init() function. Signed-off-by: Igor Grinberg Cc: Jon Hunter Cc: Santosh Shilimkar Cc: Vaibhav Hiremath Acked-by: Santosh Shilimkar Reviewed-by: Jon Hunter --- arch/arm/mach-omap2/timer.c | 130 +++++++++++++++--------------------- arch/arm/plat-omap/Kconfig | 6 ++ 2 files changed, 59 insertions(+), 77 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index b7f43a28e41f..bbe3cc2c1fca 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -66,20 +66,6 @@ #define OMAP3_32K_SOURCE "omap_32k_fck" #define OMAP4_32K_SOURCE "sys_32k_ck" -#ifdef CONFIG_OMAP_32K_TIMER -#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE -#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE -#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE -#define OMAP3_SECURE_TIMER 12 -#define TIMER_PROP_SECURE "ti,timer-secure" -#else -#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE -#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE -#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE -#define OMAP3_SECURE_TIMER 1 -#define TIMER_PROP_SECURE "ti,timer-alwon" -#endif - #define REALTIME_COUNTER_BASE 0x48243200 #define INCREMENTER_NUMERATOR_OFFSET 0x10 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 @@ -400,7 +386,6 @@ static u32 notrace dmtimer_read_sched_clock(void) return 0; } -#ifdef CONFIG_OMAP_32K_TIMER static struct of_device_id omap_counter_match[] __initdata = { { .compatible = "ti,omap-counter32k", }, { } @@ -466,12 +451,6 @@ static int __init omap2_sync32k_clocksource_init(void) return ret; } -#else -static inline int omap2_sync32k_clocksource_init(void) -{ - return -ENODEV; -} -#endif static void __init omap2_gptimer_clocksource_init(int gptimer_id, const char *fck_source) @@ -497,25 +476,6 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id, gptimer_id, clksrc.rate); } -static void __init omap2_clocksource_init(int gptimer_id, - const char *fck_source) -{ - /* - * First give preference to kernel parameter configuration - * by user (clocksource="gp_timer"). - * - * In case of missing kernel parameter for clocksource, - * first check for availability for 32k-sync timer, in case - * of failure in finding 32k_counter module or registering - * it as clocksource, execution will fallback to gp-timer. - */ - if (use_gptimer_clksrc == true) - omap2_gptimer_clocksource_init(gptimer_id, fck_source); - else if (omap2_sync32k_clocksource_init()) - /* Fall back to gp-timer code */ - omap2_gptimer_clocksource_init(gptimer_id, fck_source); -} - #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER /* * The realtime counter also called master counter, is a free-running @@ -594,52 +554,62 @@ static inline void __init realtime_counter_init(void) {} #endif -#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ - clksrc_nr, clksrc_src) \ -static void __init omap##name##_timer_init(void) \ +#define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ + clksrc_nr, clksrc_src) \ +static void __init omap##name##_gptimer_timer_init(void) \ { \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ - omap2_clocksource_init((clksrc_nr), clksrc_src); \ + omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \ } -#define OMAP_SYS_TIMER(name) \ +#define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ + clksrc_nr, clksrc_src) \ +static void __init omap##name##_sync32k_timer_init(void) \ +{ \ + omap_dmtimer_init(); \ + omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ + /* Enable the use of clocksource="gp_timer" kernel parameter */ \ + if (use_gptimer_clksrc) \ + omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\ + else \ + omap2_sync32k_clocksource_init(); \ +} + +#define OMAP_SYS_TIMER(name, clksrc) \ struct sys_timer omap##name##_timer = { \ - .init = omap##name##_timer_init, \ + .init = omap##name##_##clksrc##_timer_init, \ }; #ifdef CONFIG_ARCH_OMAP2 -OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, "ti,timer-alwon", - 2, OMAP2_MPU_SOURCE) -OMAP_SYS_TIMER(2) -#endif +OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon", + 2, OMAP2_MPU_SOURCE); +OMAP_SYS_TIMER(2, sync32k); +#endif /* CONFIG_ARCH_OMAP2 */ #ifdef CONFIG_ARCH_OMAP3 -OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, "ti,timer-alwon", - 2, OMAP3_MPU_SOURCE) -OMAP_SYS_TIMER(3) -OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, - TIMER_PROP_SECURE, 2, OMAP3_MPU_SOURCE) -OMAP_SYS_TIMER(3_secure) -#endif +OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon", + 2, OMAP3_MPU_SOURCE); +OMAP_SYS_TIMER(3, sync32k); +OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure", + 2, OMAP3_MPU_SOURCE); +OMAP_SYS_TIMER(3_secure, sync32k); +#endif /* CONFIG_ARCH_OMAP3 */ #ifdef CONFIG_SOC_AM33XX -OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon", - 2, OMAP4_MPU_SOURCE) -OMAP_SYS_TIMER(3_am33xx) -#endif +OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon", + 2, OMAP4_MPU_SOURCE); +OMAP_SYS_TIMER(3_am33xx, gptimer); +#endif /* CONFIG_SOC_AM33XX */ #ifdef CONFIG_ARCH_OMAP4 +OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", + 2, OMAP4_MPU_SOURCE); #ifdef CONFIG_LOCAL_TIMERS -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, - OMAP44XX_LOCAL_TWD_BASE, 29); -#endif - -static void __init omap4_timer_init(void) +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); +static void __init omap4_local_timer_init(void) { - omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon"); - omap2_clocksource_init(2, OMAP4_MPU_SOURCE); -#ifdef CONFIG_LOCAL_TIMERS + omap4_sync32k_timer_init(); /* Local timers are not supprted on OMAP4430 ES1.0 */ if (omap_rev() != OMAP4430_REV_ES1_0) { int err; @@ -653,26 +623,32 @@ static void __init omap4_timer_init(void) if (err) pr_err("twd_local_timer_register failed %d\n", err); } -#endif } -OMAP_SYS_TIMER(4) -#endif +#else /* CONFIG_LOCAL_TIMERS */ +static inline void omap4_local_timer_init(void) +{ + omap4_sync32_timer_init(); +} +#endif /* CONFIG_LOCAL_TIMERS */ +OMAP_SYS_TIMER(4, local); +#endif /* CONFIG_ARCH_OMAP4 */ #ifdef CONFIG_SOC_OMAP5 -static void __init omap5_timer_init(void) +OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", + 2, OMAP4_MPU_SOURCE); +static void __init omap5_realtime_timer_init(void) { int err; - omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon"); - omap2_clocksource_init(2, OMAP4_MPU_SOURCE); + omap5_sync32k_timer_init(); realtime_counter_init(); err = arch_timer_of_register(); if (err) pr_err("%s: arch_timer_register failed %d\n", __func__, err); } -OMAP_SYS_TIMER(5) -#endif +OMAP_SYS_TIMER(5, realtime); +#endif /* CONFIG_SOC_OMAP5 */ /** * omap_timer_init - build and register timer device with an diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 82fcb206b5b2..665870dce3c8 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -154,6 +154,12 @@ config OMAP_32K_TIMER intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5. + On OMAP2PLUS this value is only used for CONFIG_HZ and + CLOCK_TICK_RATE compile time calculation. + The actual timer selection is done in the board file + through the (DT_)MACHINE_START structure. + + config OMAP3_L2_AUX_SECURE_SAVE_RESTORE bool "OMAP3 HS/EMU save and restore for L2 AUX control register" depends on ARCH_OMAP3 && PM From 26f01998b0657a61167a819f1c37cb9f9e9d674b Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Sun, 18 Nov 2012 17:06:41 +0200 Subject: [PATCH 71/71] ARM: OMAP3: cm-t3517: use GPTIMER for system clock cm-t3517 starting from revision 1.2 does not have the 32K oscilator wired to the AM3517 SoC. Therefore switch to use the GPTIMER for system clock. Signed-off-by: Igor Grinberg Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-cm-t3517.c | 2 +- arch/arm/mach-omap2/common.h | 1 + arch/arm/mach-omap2/timer.c | 3 +++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 278664731d2c..54930c9a3b18 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -297,6 +297,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517") .handle_irq = omap3_intc_handle_irq, .init_machine = cm_t3517_init, .init_late = am35xx_init_late, - .timer = &omap3_timer, + .timer = &omap3_gp_timer, .restart = omap_prcm_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 426fcfcfd821..3f781d245cc6 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -138,6 +138,7 @@ extern void omap2_init_common_infrastructure(void); extern struct sys_timer omap2_timer; extern struct sys_timer omap3_timer; extern struct sys_timer omap3_secure_timer; +extern struct sys_timer omap3_gp_timer; extern struct sys_timer omap3_am33xx_timer; extern struct sys_timer omap4_timer; extern struct sys_timer omap5_timer; diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index bbe3cc2c1fca..b9cff72ceaec 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -594,6 +594,9 @@ OMAP_SYS_TIMER(3, sync32k); OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure", 2, OMAP3_MPU_SOURCE); OMAP_SYS_TIMER(3_secure, sync32k); +OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon", + 2, OMAP3_MPU_SOURCE); +OMAP_SYS_TIMER(3_gp, gptimer); #endif /* CONFIG_ARCH_OMAP3 */ #ifdef CONFIG_SOC_AM33XX