Blackfin: simplify BF561 coreb driver greatly
Since 90% of this driver can be handled in user space, move it to the corebld user space application. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
b9ccf14bc5
commit
c8f36dc3c1
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@ -9,22 +9,9 @@ if (!SMP)
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comment "Core B Support"
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config BF561_COREB
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bool "Enable Core B support"
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bool "Enable Core B loader"
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default y
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config BF561_COREB_RESET
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bool "Enable Core B reset support"
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default n
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help
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This requires code in the application that is loaded
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into Core B. In order to reset, the application needs
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to install an interrupt handler for Supplemental
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Interrupt 0, that sets RETI to 0xff600000 and writes
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bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0.
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This causes Core B to stall when Supplemental Interrupt
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0 is set, and will reset PC to 0xff600000 when
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COREB_SRAM_INIT is cleared.
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endif
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comment "Interrupt Priority Assignment"
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@ -1,406 +1,74 @@
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/*
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* File: arch/blackfin/mach-bf561/coreb.c
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* Based on:
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* Author:
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/* Load firmware into Core B on a BF561
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*
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* Created:
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* Description: Handle CoreB on a BF561
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Copyright 2004-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* The Core B reset func requires code in the application that is loaded into
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* Core B. In order to reset, the application needs to install an interrupt
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* handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and
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* writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core
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* B to stall when Supplemental Interrupt 0 is set, and will reset PC to
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* 0xff600000 when COREB_SRAM_INIT is cleared.
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*/
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#include <linux/mm.h>
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#include <linux/miscdevice.h>
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#include <linux/device.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/uaccess.h>
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#include <linux/fs.h>
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#include <asm/dma.h>
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#include <asm/cacheflush.h>
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#include <linux/kernel.h>
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#include <linux/miscdevice.h>
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#include <linux/module.h>
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#define MODULE_VER "v0.1"
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static spinlock_t coreb_lock;
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static wait_queue_head_t coreb_dma_wait;
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#define COREB_IS_OPEN 0x00000001
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#define COREB_IS_RUNNING 0x00000010
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#define CMD_COREB_INDEX 1
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#define CMD_COREB_START 2
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#define CMD_COREB_STOP 3
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#define CMD_COREB_RESET 4
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#define COREB_MINOR 229
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static unsigned long coreb_status = 0;
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static unsigned long coreb_base = 0xff600000;
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static unsigned long coreb_size = 0x4000;
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int coreb_dma_done;
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static loff_t coreb_lseek(struct file *file, loff_t offset, int origin);
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static ssize_t coreb_read(struct file *file, char *buf, size_t count,
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loff_t * ppos);
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static ssize_t coreb_write(struct file *file, const char *buf, size_t count,
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loff_t * ppos);
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static int coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
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unsigned long arg);
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static int coreb_open(struct inode *inode, struct file *file);
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static int coreb_release(struct inode *inode, struct file *file);
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static irqreturn_t coreb_dma_interrupt(int irq, void *dev_id)
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static int
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coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
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{
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clear_dma_irqstat(CH_MEM_STREAM2_DEST);
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coreb_dma_done = 1;
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wake_up_interruptible(&coreb_dma_wait);
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return IRQ_HANDLED;
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}
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int ret = 0;
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static ssize_t coreb_write(struct file *file, const char *buf, size_t count,
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loff_t * ppos)
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{
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unsigned long p = *ppos;
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ssize_t wrote = 0;
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if (p + count > coreb_size)
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return -EFAULT;
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while (count > 0) {
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int len = count;
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if (len > PAGE_SIZE)
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len = PAGE_SIZE;
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coreb_dma_done = 0;
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flush_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
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/* Source Channel */
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set_dma_start_addr(CH_MEM_STREAM2_SRC, (unsigned long)buf);
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set_dma_x_count(CH_MEM_STREAM2_SRC, len);
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set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
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set_dma_config(CH_MEM_STREAM2_SRC, 0);
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/* Destination Channel */
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set_dma_start_addr(CH_MEM_STREAM2_DEST, coreb_base + p);
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set_dma_x_count(CH_MEM_STREAM2_DEST, len);
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set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char));
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set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN);
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enable_dma(CH_MEM_STREAM2_SRC);
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enable_dma(CH_MEM_STREAM2_DEST);
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wait_event_interruptible(coreb_dma_wait, coreb_dma_done);
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disable_dma(CH_MEM_STREAM2_SRC);
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disable_dma(CH_MEM_STREAM2_DEST);
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count -= len;
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wrote += len;
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buf += len;
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p += len;
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}
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*ppos = p;
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return wrote;
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}
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static ssize_t coreb_read(struct file *file, char *buf, size_t count,
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loff_t * ppos)
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{
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unsigned long p = *ppos;
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ssize_t read = 0;
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if ((p + count) > coreb_size)
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return -EFAULT;
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while (count > 0) {
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int len = count;
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if (len > PAGE_SIZE)
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len = PAGE_SIZE;
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coreb_dma_done = 0;
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invalidate_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
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/* Source Channel */
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set_dma_start_addr(CH_MEM_STREAM2_SRC, coreb_base + p);
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set_dma_x_count(CH_MEM_STREAM2_SRC, len);
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set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
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set_dma_config(CH_MEM_STREAM2_SRC, 0);
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/* Destination Channel */
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set_dma_start_addr(CH_MEM_STREAM2_DEST, (unsigned long)buf);
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set_dma_x_count(CH_MEM_STREAM2_DEST, len);
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set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char));
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set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN);
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enable_dma(CH_MEM_STREAM2_SRC);
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enable_dma(CH_MEM_STREAM2_DEST);
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wait_event_interruptible(coreb_dma_wait, coreb_dma_done);
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disable_dma(CH_MEM_STREAM2_SRC);
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disable_dma(CH_MEM_STREAM2_DEST);
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count -= len;
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read += len;
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buf += len;
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p += len;
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}
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return read;
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}
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static loff_t coreb_lseek(struct file *file, loff_t offset, int origin)
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{
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loff_t ret;
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mutex_lock(&file->f_dentry->d_inode->i_mutex);
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switch (origin) {
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case 0 /* SEEK_SET */ :
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if (offset < coreb_size) {
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file->f_pos = offset;
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ret = file->f_pos;
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} else
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ret = -EINVAL;
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switch (cmd) {
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case CMD_COREB_START:
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bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
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break;
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case CMD_COREB_STOP:
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bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
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bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
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break;
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case CMD_COREB_RESET:
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bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
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break;
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case 1 /* SEEK_CUR */ :
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if ((offset + file->f_pos) < coreb_size) {
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file->f_pos += offset;
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ret = file->f_pos;
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} else
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ret = -EINVAL;
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default:
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ret = -EINVAL;
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break;
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}
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mutex_unlock(&file->f_dentry->d_inode->i_mutex);
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CSYNC();
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return ret;
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}
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/* No BKL needed here */
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static int coreb_open(struct inode *inode, struct file *file)
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{
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spin_lock_irq(&coreb_lock);
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if (coreb_status & COREB_IS_OPEN)
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goto out_busy;
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coreb_status |= COREB_IS_OPEN;
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spin_unlock_irq(&coreb_lock);
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return 0;
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out_busy:
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spin_unlock_irq(&coreb_lock);
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return -EBUSY;
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}
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static int coreb_release(struct inode *inode, struct file *file)
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{
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spin_lock_irq(&coreb_lock);
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coreb_status &= ~COREB_IS_OPEN;
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spin_unlock_irq(&coreb_lock);
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return 0;
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}
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static int coreb_ioctl(struct inode *inode, struct file *file,
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unsigned int cmd, unsigned long arg)
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{
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int retval = 0;
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int coreb_index = 0;
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switch (cmd) {
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case CMD_COREB_INDEX:
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if (copy_from_user(&coreb_index, (int *)arg, sizeof(int))) {
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retval = -EFAULT;
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break;
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}
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spin_lock_irq(&coreb_lock);
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switch (coreb_index) {
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case 0:
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coreb_base = 0xff600000;
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coreb_size = 0x4000;
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break;
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case 1:
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coreb_base = 0xff610000;
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coreb_size = 0x4000;
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break;
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case 2:
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coreb_base = 0xff500000;
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coreb_size = 0x8000;
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break;
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case 3:
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coreb_base = 0xff400000;
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coreb_size = 0x8000;
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break;
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default:
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retval = -EINVAL;
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break;
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}
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spin_unlock_irq(&coreb_lock);
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mutex_lock(&file->f_dentry->d_inode->i_mutex);
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file->f_pos = 0;
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mutex_unlock(&file->f_dentry->d_inode->i_mutex);
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break;
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case CMD_COREB_START:
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spin_lock_irq(&coreb_lock);
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if (coreb_status & COREB_IS_RUNNING) {
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retval = -EBUSY;
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break;
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}
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printk(KERN_INFO "Starting Core B\n");
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coreb_status |= COREB_IS_RUNNING;
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bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
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SSYNC();
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spin_unlock_irq(&coreb_lock);
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break;
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#if defined(CONFIG_BF561_COREB_RESET)
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case CMD_COREB_STOP:
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spin_lock_irq(&coreb_lock);
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printk(KERN_INFO "Stopping Core B\n");
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bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
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bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
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coreb_status &= ~COREB_IS_RUNNING;
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spin_unlock_irq(&coreb_lock);
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break;
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case CMD_COREB_RESET:
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printk(KERN_INFO "Resetting Core B\n");
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bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
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break;
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#endif
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}
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return retval;
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}
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static struct file_operations coreb_fops = {
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.owner = THIS_MODULE,
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.llseek = coreb_lseek,
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.read = coreb_read,
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.write = coreb_write,
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.ioctl = coreb_ioctl,
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.open = coreb_open,
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.release = coreb_release
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.owner = THIS_MODULE,
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.ioctl = coreb_ioctl,
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};
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static struct miscdevice coreb_dev = {
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COREB_MINOR,
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"coreb",
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&coreb_fops
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.minor = MISC_DYNAMIC_MINOR,
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.name = "coreb",
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.fops = &coreb_fops,
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};
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static ssize_t coreb_show_status(struct device *dev, struct device_attribute *attr, char *buf)
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static int __init bf561_coreb_init(void)
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{
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return sprintf(buf,
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"Base Address:\t0x%08lx\n"
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"Core B is %s\n"
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"SICA_SYSCR:\t%04x\n"
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"SICB_SYSCR:\t%04x\n"
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"\n"
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"IRQ Status:\tCore A\t\tCore B\n"
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"ISR0:\t\t%08x\t\t%08x\n"
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"ISR1:\t\t%08x\t\t%08x\n"
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"IMASK0:\t\t%08x\t\t%08x\n"
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"IMASK1:\t\t%08x\t\t%08x\n",
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coreb_base,
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coreb_status & COREB_IS_RUNNING ? "running" : "stalled",
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bfin_read_SICA_SYSCR(), bfin_read_SICB_SYSCR(),
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bfin_read_SICA_ISR0(), bfin_read_SICB_ISR0(),
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bfin_read_SICA_ISR1(), bfin_read_SICB_ISR0(),
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bfin_read_SICA_IMASK0(), bfin_read_SICB_IMASK0(),
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bfin_read_SICA_IMASK1(), bfin_read_SICB_IMASK1());
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return misc_register(&coreb_dev);
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}
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static DEVICE_ATTR(coreb_status, S_IRUGO, coreb_show_status, NULL);
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int __init bf561_coreb_init(void)
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{
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init_waitqueue_head(&coreb_dma_wait);
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spin_lock_init(&coreb_lock);
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/* Request the core memory regions for Core B */
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if (request_mem_region(0xff600000, 0x4000,
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"Core B - Instruction SRAM") == NULL)
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goto exit;
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if (request_mem_region(0xFF610000, 0x4000,
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"Core B - Instruction SRAM") == NULL)
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goto release_instruction_a_sram;
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if (request_mem_region(0xFF500000, 0x8000,
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"Core B - Data Bank B SRAM") == NULL)
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goto release_instruction_b_sram;
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if (request_mem_region(0xff400000, 0x8000,
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"Core B - Data Bank A SRAM") == NULL)
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goto release_data_b_sram;
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if (request_dma(CH_MEM_STREAM2_DEST, "Core B - DMA Destination") < 0)
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goto release_data_a_sram;
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if (request_dma(CH_MEM_STREAM2_SRC, "Core B - DMA Source") < 0)
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goto release_dma_dest;
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set_dma_callback(CH_MEM_STREAM2_DEST, coreb_dma_interrupt, NULL);
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misc_register(&coreb_dev);
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if (device_create_file(coreb_dev.this_device, &dev_attr_coreb_status))
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goto release_dma_src;
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printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER);
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return 0;
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release_dma_src:
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free_dma(CH_MEM_STREAM2_SRC);
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release_dma_dest:
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free_dma(CH_MEM_STREAM2_DEST);
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release_data_a_sram:
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release_mem_region(0xff400000, 0x8000);
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release_data_b_sram:
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release_mem_region(0xff500000, 0x8000);
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release_instruction_b_sram:
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release_mem_region(0xff610000, 0x4000);
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release_instruction_a_sram:
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release_mem_region(0xff600000, 0x4000);
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exit:
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return -ENOMEM;
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}
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void __exit bf561_coreb_exit(void)
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{
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device_remove_file(coreb_dev.this_device, &dev_attr_coreb_status);
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misc_deregister(&coreb_dev);
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release_mem_region(0xff610000, 0x4000);
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release_mem_region(0xff600000, 0x4000);
|
||||
release_mem_region(0xff500000, 0x8000);
|
||||
release_mem_region(0xff400000, 0x8000);
|
||||
|
||||
free_dma(CH_MEM_STREAM2_DEST);
|
||||
free_dma(CH_MEM_STREAM2_SRC);
|
||||
}
|
||||
|
||||
module_init(bf561_coreb_init);
|
||||
|
||||
static void __exit bf561_coreb_exit(void)
|
||||
{
|
||||
misc_deregister(&coreb_dev);
|
||||
}
|
||||
module_exit(bf561_coreb_exit);
|
||||
|
||||
MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>");
|
||||
|
|
|
|||
Loading…
Reference in New Issue