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bnx2x: Using the new FW

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The new FW improves the packets per second rate. It required a lot of change in
the FW which implies many changes in the driver to support it. It is now also
possible for the driver to use a separate MSI-X vector for Rx and Tx - this also
add some to the complicity of this change.

All things said - after this patch, practically all performance matrixes show
improvement.
Though Vladislav Zolotarov is not signed on this patch, he did most of the job
and deserves credit for that.

Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Eilon Greenstein 2009-08-12 22:53:28 -07:00 committed by David S. Miller
parent 6200f09036
commit ca00392cb8
6 changed files with 1081 additions and 666 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

45
drivers/net/bnx2x.h
View file

@ -142,6 +142,9 @@ struct sw_rx_bd {
struct sw_tx_bd { struct sw_tx_bd {
struct sk_buff *skb; struct sk_buff *skb;
u16 first_bd; u16 first_bd;
u8 flags;
/* Set on the first BD descriptor when there is a split BD */
#define BNX2X_TSO_SPLIT_BD (1<<0)
}; };
struct sw_rx_page { struct sw_rx_page {
@ -149,6 +152,11 @@ struct sw_rx_page {
DECLARE_PCI_UNMAP_ADDR(mapping) DECLARE_PCI_UNMAP_ADDR(mapping)
}; };
union db_prod {
struct doorbell_set_prod data;
u32 raw;
};
/* MC hsi */ /* MC hsi */
#define BCM_PAGE_SHIFT 12 #define BCM_PAGE_SHIFT 12
@ -234,15 +242,14 @@ struct bnx2x_fastpath {
struct napi_struct napi; struct napi_struct napi;
u8 is_rx_queue;
struct host_status_block *status_blk; struct host_status_block *status_blk;
dma_addr_t status_blk_mapping; dma_addr_t status_blk_mapping;
struct eth_tx_db_data *hw_tx_prods;
dma_addr_t tx_prods_mapping;
struct sw_tx_bd *tx_buf_ring; struct sw_tx_bd *tx_buf_ring;
struct eth_tx_bd *tx_desc_ring; union eth_tx_bd_types *tx_desc_ring;
dma_addr_t tx_desc_mapping; dma_addr_t tx_desc_mapping;
struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
@ -272,6 +279,8 @@ struct bnx2x_fastpath {
u8 cl_id; /* eth client id */ u8 cl_id; /* eth client id */
u8 sb_id; /* status block number in HW */ u8 sb_id; /* status block number in HW */
union db_prod tx_db;
u16 tx_pkt_prod; u16 tx_pkt_prod;
u16 tx_pkt_cons; u16 tx_pkt_cons;
u16 tx_bd_prod; u16 tx_bd_prod;
@ -309,21 +318,24 @@ struct bnx2x_fastpath {
struct xstorm_per_client_stats old_xclient; struct xstorm_per_client_stats old_xclient;
struct bnx2x_eth_q_stats eth_q_stats; struct bnx2x_eth_q_stats eth_q_stats;
char name[IFNAMSIZ]; /* The size is calculated using the following:
sizeof name field from netdev structure +
4 ('-Xx-' string) +
4 (for the digits and to make it DWORD aligned) */
#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
char name[FP_NAME_SIZE];
struct bnx2x *bp; /* parent */ struct bnx2x *bp; /* parent */
}; };
#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
#define BNX2X_HAS_WORK(fp) (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))
/* MC hsi */ /* MC hsi */
#define MAX_FETCH_BD 13 /* HW max BDs per packet */ #define MAX_FETCH_BD 13 /* HW max BDs per packet */
#define RX_COPY_THRESH 92 #define RX_COPY_THRESH 92
#define NUM_TX_RINGS 16 #define NUM_TX_RINGS 16
#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd)) #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
#define MAX_TX_BD (NUM_TX_BD - 1) #define MAX_TX_BD (NUM_TX_BD - 1)
@ -395,7 +407,7 @@ struct bnx2x_fastpath {
#define DPM_TRIGER_TYPE 0x40 #define DPM_TRIGER_TYPE 0x40
#define DOORBELL(bp, cid, val) \ #define DOORBELL(bp, cid, val) \
do { \ do { \
writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \ writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
DPM_TRIGER_TYPE); \ DPM_TRIGER_TYPE); \
} while (0) } while (0)
@ -902,8 +914,6 @@ struct bnx2x {
u16 rx_quick_cons_trip; u16 rx_quick_cons_trip;
u16 rx_ticks_int; u16 rx_ticks_int;
u16 rx_ticks; u16 rx_ticks;
/* Maximal coalescing timeout in us */
#define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
u32 lin_cnt; u32 lin_cnt;
@ -985,19 +995,20 @@ struct bnx2x {
}; };
#define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT / E1HVN_MAX) : \ #define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/(2 * E1HVN_MAX)) \
MAX_CONTEXT) : (MAX_CONTEXT/2))
#define BNX2X_NUM_QUEUES(bp) max(bp->num_rx_queues, bp->num_tx_queues) #define BNX2X_NUM_QUEUES(bp) (bp->num_rx_queues + bp->num_tx_queues)
#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 2)
#define for_each_rx_queue(bp, var) \ #define for_each_rx_queue(bp, var) \
for (var = 0; var < bp->num_rx_queues; var++) for (var = 0; var < bp->num_rx_queues; var++)
#define for_each_tx_queue(bp, var) \ #define for_each_tx_queue(bp, var) \
for (var = 0; var < bp->num_tx_queues; var++) for (var = bp->num_rx_queues; \
var < BNX2X_NUM_QUEUES(bp); var++)
#define for_each_queue(bp, var) \ #define for_each_queue(bp, var) \
for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
#define for_each_nondefault_queue(bp, var) \ #define for_each_nondefault_queue(bp, var) \
for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) for (var = 1; var < bp->num_rx_queues; var++)
void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);

389
drivers/net/bnx2x_fw_defs.h
View file

@ -12,48 +12,117 @@
(IS_E1H_OFFSET ? 0x7000 : 0x1000) (IS_E1H_OFFSET ? 0x7000 : 0x1000)
#define CSTORM_ASSERT_LIST_OFFSET(idx) \ #define CSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ #define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \ (IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \
((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \ ((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \
0x40) + (index * 0x4))) 0x40) + (index * 0x4)))
#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ #define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \ (IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \
((function&1) * 0x100)) : (0x1900 + (function * 0x40))) ((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \
#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ 0x80) + (index * 0x4)))
(IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \ #define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \
((function&1) * 0x100)) : (0x1908 + (function * 0x40))) (IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \
((function&1) * 0x100)) : (0x3540 + (function * 0x40)))
#define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \
((function&1) * 0x200)) : (0x35c0 + (function * 0x80)))
#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \
((function&1) * 0x100)) : (0x3548 + (function * 0x40)))
#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \
((function&1) * 0x200)) : (0x35c8 + (function * 0x80)))
#define CSTORM_FUNCTION_MODE_OFFSET \ #define CSTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x11e8 : 0xffffffff) (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
#define CSTORM_HC_BTR_OFFSET(port) \ #define CSTORM_HC_BTR_C_OFFSET(port) \
(IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) (IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0)))
#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ #define CSTORM_HC_BTR_U_OFFSET(port) \
(IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \ (IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0)))
(index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ #define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \
(function * 0x8)))
#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \
(function * 0x8)))
#define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2410 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2414 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x241c + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2427 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2412 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2426 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \
(IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \
(0x2424 + (function * 0xc0) + (eqIdx * 0x18)))
#define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \
(function * 0x8)))
#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \
(function * 0x8)))
#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \
(function * 0x8)))
#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \
(function * 0x8)))
#define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4))) (index * 0x4)))
#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ #define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \ (IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \
(index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ (index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \
(index * 0x4))) (index * 0x4)))
#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ #define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \ (IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \
(0x1400 + (port * 0x280) + (cpu_id * 0x28))) (index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \
#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ (index * 0x4)))
(IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \ #define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \
(0x1408 + (port * 0x280) + (cpu_id * 0x28))) (IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \
(index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \
(index * 0x4)))
#define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \
(0x3040 + (port * 0x280) + (cpu_id * 0x28)))
#define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \
(0x4000 + (port * 0x800) + (cpu_id * 0x80)))
#define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \
(0x3048 + (port * 0x280) + (cpu_id * 0x28)))
#define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \
(0x4008 + (port * 0x800) + (cpu_id * 0x80)))
#define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10
#define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60
#define CSTORM_STATS_FLAGS_OFFSET(function) \ #define CSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \ (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
(function * 0x8))) (function * 0x8)))
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \ #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
(IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff) (IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff)
#define TSTORM_ASSERT_LIST_INDEX_OFFSET \ #define TSTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET ? 0xa000 : 0x1000) (IS_E1H_OFFSET ? 0xa000 : 0x1000)
#define TSTORM_ASSERT_LIST_OFFSET(idx) \ #define TSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
(IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \ (IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \
: (0x9c0 + (port * 0x130) + (client_id * 0x10))) : (0x9c0 + (port * 0x120) + (client_id * 0x10)))
#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \ #define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
(IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff) (IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff)
#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
(IS_E1H_OFFSET ? 0x1eda : 0xffffffff)
#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \ (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
@ -65,95 +134,133 @@
(IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \ (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \ (IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \
(function * 0x8))) (function * 0x8)))
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \ #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \ (IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \
(function * 0x38))) (function * 0x40)))
#define TSTORM_FUNCTION_MODE_OFFSET \ #define TSTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff) (IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff)
#define TSTORM_HC_BTR_OFFSET(port) \ #define TSTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18))) (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \ #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \ (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
(function * 0x80))) (function * 0x80)))
#define TSTORM_INDIRECTION_TABLE_SIZE 0x80 #define TSTORM_INDIRECTION_TABLE_SIZE 0x80
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \ #define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \
(IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \ (IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \
(function * 0x38))) : (0x4c30 + (function * 0x40) + (pblEntry * 0x8)))
#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \ (IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \
0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50)))
#define TSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
(function * 0x8))) (function * 0x8)))
#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20) #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10) (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \
#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200) (function * 0x8)))
#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \
(function * 0x8)))
#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \
(function * 0x8)))
#define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \
(function * 0x8)))
#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \
(function * 0x8)))
#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \
(function * 0x8)))
#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \
(function * 0x8)))
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \
(function * 0x40)))
#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
(IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \
0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40)))
#define TSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \
(function * 0x8)))
#define TSTORM_TCP_MAX_CWND_OFFSET(function) \
(IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \
(function * 0x8)))
#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000)
#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000)
#define USTORM_ASSERT_LIST_INDEX_OFFSET \ #define USTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET ? 0x8960 : 0x1000) (IS_E1H_OFFSET ? 0x8000 : 0x1000)
#define USTORM_ASSERT_LIST_OFFSET(idx) \ #define USTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
(IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \ (IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \
(0x5330 + (port * 0x260) + (clientId * 0x20))) (0x4010 + (port * 0x360) + (clientId * 0x30)))
#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ #define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \
(IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \ (IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \
((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \ (0x4028 + (port * 0x360) + (clientId * 0x30)))
0x40) + (index * 0x4))) #define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \
#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
(IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \
((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
(IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \
((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \ #define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \
(IS_E1H_OFFSET ? (0x8020 + (port * 0x4b0) + (clientId * 0x30)) : \ (IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \
0xffffffff) 0xffffffff)
#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ #define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1d98 + \ (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \
(function * 0x8))) (function * 0x8)))
#define USTORM_FUNCTION_MODE_OFFSET \ #define USTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x2448 : 0xffffffff) (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
#define USTORM_HC_BTR_OFFSET(port) \ #define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) (IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \
#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ (function * 0x8)))
(IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \ #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
(0x5328 + (port * 0x260) + (clientId * 0x20))) (IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ (function * 0x8)))
(IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \ #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \
(function * 0x8)))
#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \
(function * 0x8)))
#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \
(function * 0x8)))
#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \
(function * 0x8)))
#define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \
(function * 0x8)))
#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \
(function * 0x8)))
#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \
(function * 0x8)))
#define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \
(function * 0x8)))
#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
(IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \
(0x4018 + (port * 0x360) + (clientId * 0x30)))
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \
(function * 0x8))) (function * 0x8)))
#define USTORM_PAUSE_ENABLED_OFFSET(port) \
(IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ #define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
(IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \ (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
0x28)) : (0x4740 + (port * 0x2d0) + (stats_counter_id * 0x28))) 0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28)))
#define USTORM_RX_PRODS_OFFSET(port, client_id) \ #define USTORM_RX_PRODS_OFFSET(port, client_id) \
(IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \ (IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \
: (0x5318 + (port * 0x260) + (client_id * 0x20))) : (0x4000 + (port * 0x360) + (client_id * 0x30)))
#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)))
#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)))
#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
(0x1400 + (port * 0x280) + (cpu_id * 0x28)))
#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
(0x1408 + (port * 0x280) + (cpu_id * 0x28)))
#define USTORM_STATS_FLAGS_OFFSET(function) \ #define USTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1d80 + \ (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \
(function * 0x8))) (function * 0x8)))
#define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095)
#define USTORM_TPA_BTR_SIZE 0x1
#define XSTORM_ASSERT_LIST_INDEX_OFFSET \ #define XSTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET ? 0x9000 : 0x1000) (IS_E1H_OFFSET ? 0x9000 : 0x1000)
#define XSTORM_ASSERT_LIST_OFFSET(idx) \ #define XSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
(IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50))) (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50)))
#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \ (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
@ -165,22 +272,73 @@
(IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \ (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
#define XSTORM_E1HOV_OFFSET(function) \ #define XSTORM_E1HOV_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff) (IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff)
#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \ (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \
(function * 0x8))) (function * 0x8)))
#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \ (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \
(function * 0x90))) (function * 0x90)))
#define XSTORM_FUNCTION_MODE_OFFSET \ #define XSTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x2c20 : 0xffffffff) (IS_E1H_OFFSET ? 0x2c50 : 0xffffffff)
#define XSTORM_HC_BTR_OFFSET(port) \ #define XSTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
#define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \
(function * 0x8)))
#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \
(function * 0x8)))
#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \
(function * 0x8)))
#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \
(function * 0x8)))
#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \
(function * 0x8)))
#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \
(function * 0x8)))
#define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \
(function * 0x8)))
#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \
(function * 0x8)))
#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \
(function * 0x8)))
#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \
(function * 0x8)))
#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \
(IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \
(function * 0x8)))
#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
(IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \ (IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \
0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38))) 0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30)))
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \ (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \
(function * 0x90))) (function * 0x90)))
#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \ (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
@ -189,8 +347,15 @@
(IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \ (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
(function * 0x10))) (function * 0x10)))
#define XSTORM_STATS_FLAGS_OFFSET(function) \ #define XSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \ (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \
(function * 0x8))) (function * 0x8)))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \
(IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8)))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \
(IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8)))
#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \
(IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \
* 0x4)) : (0x1978 + (function * 0x4)))
#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
/** /**
@ -211,6 +376,9 @@
#define TCP_IPV4_HASH_TYPE 2 #define TCP_IPV4_HASH_TYPE 2
#define IPV6_HASH_TYPE 3 #define IPV6_HASH_TYPE 3
#define TCP_IPV6_HASH_TYPE 4 #define TCP_IPV6_HASH_TYPE 4
#define VLAN_PRI_HASH_TYPE 5
#define E1HOV_PRI_HASH_TYPE 6
#define DSCP_HASH_TYPE 7
/* Ethernet Ring parameters */ /* Ethernet Ring parameters */
@ -218,30 +386,26 @@
#define FIRST_BD_IN_PKT 0 #define FIRST_BD_IN_PKT 0
#define PARSE_BD_INDEX 1 #define PARSE_BD_INDEX 1
#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) #define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
#define U_ETH_NUM_OF_SGES_TO_FETCH 8
#define U_ETH_MAX_SGES_FOR_PACKET 3
/* Rx ring params */ /* Rx ring params */
#define U_ETH_LOCAL_BD_RING_SIZE 16 #define U_ETH_LOCAL_BD_RING_SIZE 8
#define U_ETH_LOCAL_SGE_RING_SIZE 12 #define U_ETH_LOCAL_SGE_RING_SIZE 10
#define U_ETH_SGL_SIZE 8 #define U_ETH_SGL_SIZE 8
#define U_ETH_BDS_PER_PAGE_MASK \
((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
#define U_ETH_CQE_PER_PAGE_MASK \
((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
#define U_ETH_SGES_PER_PAGE_MASK \
((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
(0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
#define TU_ETH_CQES_PER_PAGE \
(PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
#define U_ETH_UNDEFINED_Q 0xFF #define U_ETH_UNDEFINED_Q 0xFF
/* values of command IDs in the ramrod message */ /* values of command IDs in the ramrod message */
@ -266,8 +430,8 @@
#define T_ETH_CRC32_HASH_SEED 0x00000000 #define T_ETH_CRC32_HASH_SEED 0x00000000
/* Maximal L2 clients supported */ /* Maximal L2 clients supported */
#define ETH_MAX_RX_CLIENTS_E1 19 #define ETH_MAX_RX_CLIENTS_E1 18
#define ETH_MAX_RX_CLIENTS_E1H 25 #define ETH_MAX_RX_CLIENTS_E1H 26
/* Maximal aggregation queues supported */ /* Maximal aggregation queues supported */
#define ETH_MAX_AGGREGATION_QUEUES_E1 32 #define ETH_MAX_AGGREGATION_QUEUES_E1 32
@ -276,6 +440,9 @@
/* ETH RSS modes */ /* ETH RSS modes */
#define ETH_RSS_MODE_DISABLED 0 #define ETH_RSS_MODE_DISABLED 0
#define ETH_RSS_MODE_REGULAR 1 #define ETH_RSS_MODE_REGULAR 1
#define ETH_RSS_MODE_VLAN_PRI 2
#define ETH_RSS_MODE_E1HOV_PRI 3
#define ETH_RSS_MODE_IP_DSCP 4
/** /**
@ -332,12 +499,14 @@
#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3 #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4 #define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5 #define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
#define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6
#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0 #define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1 #define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2 #define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3 #define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
#define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4
#define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5
/* used by the driver to get the SB offset */ /* used by the driver to get the SB offset */
#define USTORM_ID 0 #define USTORM_ID 0

361
drivers/net/bnx2x_hsi.h
View file

@ -1218,9 +1218,9 @@ struct host_func_stats {
}; };
#define BCM_5710_FW_MAJOR_VERSION 4 #define BCM_5710_FW_MAJOR_VERSION 5
#define BCM_5710_FW_MINOR_VERSION 8 #define BCM_5710_FW_MINOR_VERSION 0
#define BCM_5710_FW_REVISION_VERSION 53 #define BCM_5710_FW_REVISION_VERSION 21
#define BCM_5710_FW_ENGINEERING_VERSION 0 #define BCM_5710_FW_ENGINEERING_VERSION 0
#define BCM_5710_FW_COMPILE_FLAGS 1 #define BCM_5710_FW_COMPILE_FLAGS 1
@ -1269,6 +1269,22 @@ struct doorbell {
}; };
/*
* doorbell message sent to the chip
*/
struct doorbell_set_prod {
#if defined(__BIG_ENDIAN)
u16 prod;
u8 zero_fill1;
struct doorbell_hdr header;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr header;
u8 zero_fill1;
u16 prod;
#endif
};
/* /*
* IGU driver acknowledgement register * IGU driver acknowledgement register
*/ */
@ -1303,6 +1319,62 @@ struct igu_ack_register {
}; };
/*
* IGU driver acknowledgement register
*/
struct igu_backward_compatible {
u32 sb_id_and_flags;
#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
u32 reserved_2;
};
/*
* IGU driver acknowledgement register
*/
struct igu_regular {
u32 sb_id_and_flags;
#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
#define IGU_REGULAR_SB_INDEX_SHIFT 0
#define IGU_REGULAR_RESERVED0 (0x1<<20)
#define IGU_REGULAR_RESERVED0_SHIFT 20
#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
#define IGU_REGULAR_BUPDATE (0x1<<24)
#define IGU_REGULAR_BUPDATE_SHIFT 24
#define IGU_REGULAR_ENABLE_INT (0x3<<25)
#define IGU_REGULAR_ENABLE_INT_SHIFT 25
#define IGU_REGULAR_RESERVED_1 (0x1<<27)
#define IGU_REGULAR_RESERVED_1_SHIFT 27
#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
#define IGU_REGULAR_CLEANUP_SET (0x1<<30)
#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
#define IGU_REGULAR_BCLEANUP (0x1<<31)
#define IGU_REGULAR_BCLEANUP_SHIFT 31
u32 reserved_2;
};
/*
* IGU driver acknowledgement register
*/
union igu_consprod_reg {
struct igu_regular regular;
struct igu_backward_compatible backward_compatible;
};
/* /*
* Parser parsing flags field * Parser parsing flags field
*/ */
@ -1434,12 +1506,10 @@ struct ustorm_eth_st_context_config {
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2) #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3) #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4) #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
u8 status_block_id; u8 status_block_id;
u8 clientId; u8 clientId;
u8 sb_index_numbers; u8 sb_index_numbers;
@ -1462,12 +1532,10 @@ struct ustorm_eth_st_context_config {
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2) #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3) #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4) #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
#endif #endif
#if defined(__BIG_ENDIAN) #if defined(__BIG_ENDIAN)
u16 bd_buff_size; u16 bd_buff_size;
@ -1487,11 +1555,36 @@ struct ustorm_eth_st_context_config {
u8 __local_bd_prod; u8 __local_bd_prod;
u8 __local_sge_prod; u8 __local_sge_prod;
#endif #endif
u32 reserved; #if defined(__BIG_ENDIAN)
u16 __sdm_bd_expected_counter;
u8 cstorm_agg_int;
u8 __expected_bds_on_ram;
#elif defined(__LITTLE_ENDIAN)
u8 __expected_bds_on_ram;
u8 cstorm_agg_int;
u16 __sdm_bd_expected_counter;
#endif
#if defined(__BIG_ENDIAN)
u16 __ring_data_ram_addr;
u16 __hc_cstorm_ram_addr;
#elif defined(__LITTLE_ENDIAN)
u16 __hc_cstorm_ram_addr;
u16 __ring_data_ram_addr;
#endif
#if defined(__BIG_ENDIAN)
u8 reserved1;
u8 max_sges_for_packet;
u16 __bd_ring_ram_addr;
#elif defined(__LITTLE_ENDIAN)
u16 __bd_ring_ram_addr;
u8 max_sges_for_packet;
u8 reserved1;
#endif
u32 bd_page_base_lo; u32 bd_page_base_lo;
u32 bd_page_base_hi; u32 bd_page_base_hi;
u32 sge_page_base_lo; u32 sge_page_base_lo;
u32 sge_page_base_hi; u32 sge_page_base_hi;
struct regpair reserved2;
}; };
/* /*
@ -1514,8 +1607,8 @@ struct eth_rx_sge {
* Local BDs and SGEs rings (in ETH) * Local BDs and SGEs rings (in ETH)
*/ */
struct eth_local_rx_rings { struct eth_local_rx_rings {
struct eth_rx_bd __local_bd_ring[16]; struct eth_rx_bd __local_bd_ring[8];
struct eth_rx_sge __local_sge_ring[12]; struct eth_rx_sge __local_sge_ring[10];
}; };
/* /*
@ -1607,13 +1700,13 @@ struct xstorm_eth_extra_ag_context_section {
*/ */
struct xstorm_eth_ag_context { struct xstorm_eth_ag_context {
#if defined(__BIG_ENDIAN) #if defined(__BIG_ENDIAN)
u16 __bd_prod; u16 agg_val1;
u8 __agg_vars1; u8 __agg_vars1;
u8 __state; u8 __state;
#elif defined(__LITTLE_ENDIAN) #elif defined(__LITTLE_ENDIAN)
u8 __state; u8 __state;
u8 __agg_vars1; u8 __agg_vars1;
u16 __bd_prod; u16 agg_val1;
#endif #endif
#if defined(__BIG_ENDIAN) #if defined(__BIG_ENDIAN)
u8 cdu_reserved; u8 cdu_reserved;
@ -1626,7 +1719,7 @@ struct xstorm_eth_ag_context {
u8 __agg_vars4; u8 __agg_vars4;
u8 cdu_reserved; u8 cdu_reserved;
#endif #endif
u32 __more_packets_to_send; u32 __bd_prod;
#if defined(__BIG_ENDIAN) #if defined(__BIG_ENDIAN)
u16 __agg_vars5; u16 __agg_vars5;
u16 __agg_val4_th; u16 __agg_val4_th;
@ -1892,8 +1985,8 @@ struct eth_tx_bd_flags {
#define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1) #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
#define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2) #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<2)
#define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 2
#define ETH_TX_BD_FLAGS_END_BD (0x1<<3) #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
#define ETH_TX_BD_FLAGS_END_BD_SHIFT 3 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
@ -1909,7 +2002,7 @@ struct eth_tx_bd_flags {
/* /*
* The eth Tx Buffer Descriptor * The eth Tx Buffer Descriptor
*/ */
struct eth_tx_bd { struct eth_tx_start_bd {
__le32 addr_lo; __le32 addr_lo;
__le32 addr_hi; __le32 addr_hi;
__le16 nbd; __le16 nbd;
@ -1917,10 +2010,21 @@ struct eth_tx_bd {
__le16 vlan; __le16 vlan;
struct eth_tx_bd_flags bd_flags; struct eth_tx_bd_flags bd_flags;
u8 general_data; u8 general_data;
#define ETH_TX_BD_HDR_NBDS (0x3F<<0) #define ETH_TX_START_BD_HDR_NBDS (0x3F<<0)
#define ETH_TX_BD_HDR_NBDS_SHIFT 0 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
#define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6) #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
#define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
};
/*
* Tx regular BD structure
*/
struct eth_tx_bd {
u32 addr_lo;
u32 addr_hi;
u16 total_pkt_bytes;
u16 nbytes;
u8 reserved[4];
}; };
/* /*
@ -1930,8 +2034,8 @@ struct eth_tx_parse_bd {
u8 global_data; u8 global_data;
#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0) #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
#define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4) #define ETH_TX_PARSE_BD_UDP_CS_FLG (0x1<<4)
#define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4 #define ETH_TX_PARSE_BD_UDP_CS_FLG_SHIFT 4
#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5) #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
#define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6) #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
@ -1956,10 +2060,10 @@ struct eth_tx_parse_bd {
#define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7) #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
#define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
u8 ip_hlen; u8 ip_hlen;
s8 cs_offset; s8 reserved;
__le16 total_hlen; __le16 total_hlen;
__le16 lso_mss;
__le16 tcp_pseudo_csum; __le16 tcp_pseudo_csum;
__le16 lso_mss;
__le16 ip_id; __le16 ip_id;
__le32 tcp_send_seq; __le32 tcp_send_seq;
}; };
@ -1968,15 +2072,16 @@ struct eth_tx_parse_bd {
* The last BD in the BD memory will hold a pointer to the next BD memory * The last BD in the BD memory will hold a pointer to the next BD memory
*/ */
struct eth_tx_next_bd { struct eth_tx_next_bd {
u32 addr_lo; __le32 addr_lo;
u32 addr_hi; __le32 addr_hi;
u8 reserved[8]; u8 reserved[8];
}; };
/* /*
* union for 3 Bd types * union for 4 Bd types
*/ */
union eth_tx_bd_types { union eth_tx_bd_types {
struct eth_tx_start_bd start_bd;
struct eth_tx_bd reg_bd; struct eth_tx_bd reg_bd;
struct eth_tx_parse_bd parse_bd; struct eth_tx_parse_bd parse_bd;
struct eth_tx_next_bd next_bd; struct eth_tx_next_bd next_bd;
@ -2005,11 +2110,35 @@ struct xstorm_eth_st_context {
#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
u16 tx_bd_cons; u16 tx_bd_cons;
#endif #endif
u32 db_data_addr_lo; u32 __reserved1;
u32 db_data_addr_hi; u32 __reserved2;
u32 __pkt_cons; #if defined(__BIG_ENDIAN)
u32 __gso_next; u8 __ram_cache_index;
u32 is_eth_conn_1b; u8 __double_buffer_client;
u16 __pkt_cons;
#elif defined(__LITTLE_ENDIAN)
u16 __pkt_cons;
u8 __double_buffer_client;
u8 __ram_cache_index;
#endif
#if defined(__BIG_ENDIAN)
u16 __statistics_address;
u16 __gso_next;
#elif defined(__LITTLE_ENDIAN)
u16 __gso_next;
u16 __statistics_address;
#endif
#if defined(__BIG_ENDIAN)
u8 __local_tx_bd_cons;
u8 safc_group_num;
u8 safc_group_en;
u8 __is_eth_conn;
#elif defined(__LITTLE_ENDIAN)
u8 __is_eth_conn;
u8 safc_group_en;
u8 safc_group_num;
u8 __local_tx_bd_cons;
#endif
union eth_tx_bd_types __bds[13]; union eth_tx_bd_types __bds[13];
}; };
@ -2074,9 +2203,9 @@ struct eth_tx_doorbell {
/* /*
* ustorm status block * cstorm default status block, generated by ustorm
*/ */
struct ustorm_def_status_block { struct cstorm_def_status_block_u {
__le16 index_values[HC_USTORM_DEF_SB_NUM_INDICES]; __le16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
__le16 status_block_index; __le16 status_block_index;
u8 func; u8 func;
@ -2085,9 +2214,9 @@ struct ustorm_def_status_block {
}; };
/* /*
* cstorm status block * cstorm default status block, generated by cstorm
*/ */
struct cstorm_def_status_block { struct cstorm_def_status_block_c {
__le16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES]; __le16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
__le16 status_block_index; __le16 status_block_index;
u8 func; u8 func;
@ -2122,17 +2251,17 @@ struct tstorm_def_status_block {
*/ */
struct host_def_status_block { struct host_def_status_block {
struct atten_def_status_block atten_status_block; struct atten_def_status_block atten_status_block;
struct ustorm_def_status_block u_def_status_block; struct cstorm_def_status_block_u u_def_status_block;
struct cstorm_def_status_block c_def_status_block; struct cstorm_def_status_block_c c_def_status_block;
struct xstorm_def_status_block x_def_status_block; struct xstorm_def_status_block x_def_status_block;
struct tstorm_def_status_block t_def_status_block; struct tstorm_def_status_block t_def_status_block;
}; };
/* /*
* ustorm status block * cstorm status block, generated by ustorm
*/ */
struct ustorm_status_block { struct cstorm_status_block_u {
__le16 index_values[HC_USTORM_SB_NUM_INDICES]; __le16 index_values[HC_USTORM_SB_NUM_INDICES];
__le16 status_block_index; __le16 status_block_index;
u8 func; u8 func;
@ -2141,9 +2270,9 @@ struct ustorm_status_block {
}; };
/* /*
* cstorm status block * cstorm status block, generated by cstorm
*/ */
struct cstorm_status_block { struct cstorm_status_block_c {
__le16 index_values[HC_CSTORM_SB_NUM_INDICES]; __le16 index_values[HC_CSTORM_SB_NUM_INDICES];
__le16 status_block_index; __le16 status_block_index;
u8 func; u8 func;
@ -2155,8 +2284,8 @@ struct cstorm_status_block {
* host status block * host status block
*/ */
struct host_status_block { struct host_status_block {
struct ustorm_status_block u_status_block; struct cstorm_status_block_u u_status_block;
struct cstorm_status_block c_status_block; struct cstorm_status_block_c c_status_block;
}; };
@ -2171,15 +2300,6 @@ struct eth_client_setup_ramrod_data {
}; };
/*
* L2 dynamic host coalescing init parameters
*/
struct eth_dynamic_hc_config {
u32 threshold[3];
u8 hc_timeout[4];
};
/* /*
* regular eth FP CQE parameters struct * regular eth FP CQE parameters struct
*/ */
@ -2344,12 +2464,10 @@ struct eth_spe {
/* /*
* doorbell data in host memory * array of 13 bds as appears in the eth xstorm context
*/ */
struct eth_tx_db_data { struct eth_tx_bds_array {
__le32 packets_prod; union eth_tx_bd_types bds[13];
__le16 bds_prod;
__le16 reserved;
}; };
@ -2377,8 +2495,10 @@ struct tstorm_eth_function_common_config {
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9) #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10) #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
#elif defined(__LITTLE_ENDIAN) #elif defined(__LITTLE_ENDIAN)
u16 config_flags; u16 config_flags;
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
@ -2397,20 +2517,49 @@ struct tstorm_eth_function_common_config {
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9) #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10) #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
u8 rss_result_mask; u8 rss_result_mask;
u8 leading_client_id; u8 leading_client_id;
#endif #endif
u16 vlan_id[2]; u16 vlan_id[2];
}; };
/*
* RSS idirection table update configuration
*/
struct rss_update_config {
#if defined(__BIG_ENDIAN)
u16 toe_rss_bitmap;
u16 flags;
#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
#define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
#define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
#elif defined(__LITTLE_ENDIAN)
u16 flags;
#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
#define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
#define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
u16 toe_rss_bitmap;
#endif
u32 reserved1;
};
/* /*
* parameters for eth update ramrod * parameters for eth update ramrod
*/ */
struct eth_update_ramrod_data { struct eth_update_ramrod_data {
struct tstorm_eth_function_common_config func_config; struct tstorm_eth_function_common_config func_config;
u8 indirectionTable[128]; u8 indirectionTable[128];
struct rss_update_config rss_config;
}; };
@ -2455,8 +2604,9 @@ struct tstorm_cam_target_table_entry {
#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4) #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
u8 client_id; u8 reserved1;
u16 vlan_id; u16 vlan_id;
u32 clients_bit_vector;
}; };
/* /*
@ -2485,7 +2635,7 @@ struct mac_configuration_entry_e1h {
__le16 msb_mac_addr; __le16 msb_mac_addr;
__le16 vlan_id; __le16 vlan_id;
__le16 e1hov_id; __le16 e1hov_id;
u8 client_id; u8 reserved0;
u8 flags; u8 flags;
#define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0) #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
#define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
@ -2493,8 +2643,9 @@ struct mac_configuration_entry_e1h {
#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2) #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3) #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1 (0x1F<<3)
#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1_SHIFT 3
u32 clients_bit_vector;
}; };
/* /*
@ -2519,13 +2670,13 @@ struct tstorm_eth_approximate_match_multicast_filtering {
*/ */
struct tstorm_eth_client_config { struct tstorm_eth_client_config {
#if defined(__BIG_ENDIAN) #if defined(__BIG_ENDIAN)
u8 max_sges_for_packet; u8 reserved0;
u8 statistics_counter_id; u8 statistics_counter_id;
u16 mtu; u16 mtu;
#elif defined(__LITTLE_ENDIAN) #elif defined(__LITTLE_ENDIAN)
u16 mtu; u16 mtu;
u8 statistics_counter_id; u8 statistics_counter_id;
u8 max_sges_for_packet; u8 reserved0;
#endif #endif
#if defined(__BIG_ENDIAN) #if defined(__BIG_ENDIAN)
u16 drop_flags; u16 drop_flags;
@ -2537,8 +2688,8 @@ struct tstorm_eth_client_config {
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3) #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4) #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
u16 config_flags; u16 config_flags;
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0) #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
@ -2546,10 +2697,8 @@ struct tstorm_eth_client_config {
#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2) #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3) #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3)
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
#elif defined(__LITTLE_ENDIAN) #elif defined(__LITTLE_ENDIAN)
u16 config_flags; u16 config_flags;
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0) #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
@ -2558,10 +2707,8 @@ struct tstorm_eth_client_config {
#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2) #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3) #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3)
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
u16 drop_flags; u16 drop_flags;
#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0) #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
@ -2571,8 +2718,8 @@ struct tstorm_eth_client_config {
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3) #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4) #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
#endif #endif
}; };
@ -2695,7 +2842,6 @@ struct rate_shaping_vars_per_port {
u32 rs_threshold; u32 rs_threshold;
}; };
/* /*
* per-port fairness variables * per-port fairness variables
*/ */
@ -2705,7 +2851,6 @@ struct fairness_vars_per_port {
u32 fairness_timeout; u32 fairness_timeout;
}; };
/* /*
* per-port SAFC variables * per-port SAFC variables
*/ */
@ -2722,7 +2867,6 @@ struct safc_struct_per_port {
u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
}; };
/* /*
* Per-port congestion management variables * Per-port congestion management variables
*/ */
@ -2734,12 +2878,24 @@ struct cmng_struct_per_port {
}; };
/*
* Dynamic host coalescing init parameters
*/
struct dynamic_hc_config {
u32 threshold[3];
u8 shift_per_protocol[HC_USTORM_SB_NUM_INDICES];
u8 hc_timeout0[HC_USTORM_SB_NUM_INDICES];
u8 hc_timeout1[HC_USTORM_SB_NUM_INDICES];
u8 hc_timeout2[HC_USTORM_SB_NUM_INDICES];
u8 hc_timeout3[HC_USTORM_SB_NUM_INDICES];
};
/* /*
* Protocol-common statistics collected by the Xstorm (per client) * Protocol-common statistics collected by the Xstorm (per client)
*/ */
struct xstorm_per_client_stats { struct xstorm_per_client_stats {
struct regpair total_sent_bytes; __le32 reserved0;
__le32 total_sent_pkts;
__le32 unicast_pkts_sent; __le32 unicast_pkts_sent;
struct regpair unicast_bytes_sent; struct regpair unicast_bytes_sent;
struct regpair multicast_bytes_sent; struct regpair multicast_bytes_sent;
@ -2747,11 +2903,10 @@ struct xstorm_per_client_stats {
__le32 broadcast_pkts_sent; __le32 broadcast_pkts_sent;
struct regpair broadcast_bytes_sent; struct regpair broadcast_bytes_sent;
__le16 stats_counter; __le16 stats_counter;
__le16 reserved0; __le16 reserved1;
__le32 reserved1; __le32 reserved2;
}; };
/* /*
* Common statistics collected by the Xstorm (per port) * Common statistics collected by the Xstorm (per port)
*/ */
@ -2759,7 +2914,6 @@ struct xstorm_common_stats {
struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID]; struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
}; };
/* /*
* Protocol-common statistics collected by the Tstorm (per port) * Protocol-common statistics collected by the Tstorm (per port)
*/ */
@ -2770,19 +2924,16 @@ struct tstorm_per_port_stats {
__le32 mac_discard; __le32 mac_discard;
}; };
/* /*
* Protocol-common statistics collected by the Tstorm (per client) * Protocol-common statistics collected by the Tstorm (per client)
*/ */
struct tstorm_per_client_stats { struct tstorm_per_client_stats {
struct regpair total_rcv_bytes;
struct regpair rcv_unicast_bytes; struct regpair rcv_unicast_bytes;
struct regpair rcv_broadcast_bytes; struct regpair rcv_broadcast_bytes;
struct regpair rcv_multicast_bytes; struct regpair rcv_multicast_bytes;
struct regpair rcv_error_bytes; struct regpair rcv_error_bytes;
__le32 checksum_discard; __le32 checksum_discard;
__le32 packets_too_big_discard; __le32 packets_too_big_discard;
__le32 total_rcv_pkts;
__le32 rcv_unicast_pkts; __le32 rcv_unicast_pkts;
__le32 rcv_broadcast_pkts; __le32 rcv_broadcast_pkts;
__le32 rcv_multicast_pkts; __le32 rcv_multicast_pkts;
@ -2790,7 +2941,6 @@ struct tstorm_per_client_stats {
__le32 ttl0_discard; __le32 ttl0_discard;
__le16 stats_counter; __le16 stats_counter;
__le16 reserved0; __le16 reserved0;
__le32 reserved1;
}; };
/* /*
@ -2892,6 +3042,15 @@ struct pram_fw_version {
}; };
/*
* The send queue element
*/
struct protocol_common_spe {
struct spe_hdr hdr;
struct regpair phy_address;
};
/* /*
* a single rate shaping counter. can be used as protocol or vnic counter * a single rate shaping counter. can be used as protocol or vnic counter
*/ */

890
drivers/net/bnx2x_main.c
View file

File diff suppressed because it is too large Load diff

60
drivers/net/bnx2x_reg.h
View file

@ -370,7 +370,6 @@
#define CFC_REG_NUM_LCIDS_LEAVING 0x104018 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
/* [RW 8] The event id for aggregated interrupt 0 */ /* [RW 8] The event id for aggregated interrupt 0 */
#define CSDM_REG_AGG_INT_EVENT_0 0xc2038 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
#define CSDM_REG_AGG_INT_EVENT_1 0xc203c
#define CSDM_REG_AGG_INT_EVENT_10 0xc2060 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
#define CSDM_REG_AGG_INT_EVENT_11 0xc2064 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
#define CSDM_REG_AGG_INT_EVENT_12 0xc2068 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
@ -378,37 +377,27 @@
#define CSDM_REG_AGG_INT_EVENT_14 0xc2070 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
#define CSDM_REG_AGG_INT_EVENT_15 0xc2074 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
#define CSDM_REG_AGG_INT_EVENT_16 0xc2078 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
#define CSDM_REG_AGG_INT_EVENT_17 0xc207c
#define CSDM_REG_AGG_INT_EVENT_18 0xc2080
#define CSDM_REG_AGG_INT_EVENT_19 0xc2084
#define CSDM_REG_AGG_INT_EVENT_2 0xc2040 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
#define CSDM_REG_AGG_INT_EVENT_20 0xc2088
#define CSDM_REG_AGG_INT_EVENT_21 0xc208c
#define CSDM_REG_AGG_INT_EVENT_22 0xc2090
#define CSDM_REG_AGG_INT_EVENT_23 0xc2094
#define CSDM_REG_AGG_INT_EVENT_24 0xc2098
#define CSDM_REG_AGG_INT_EVENT_25 0xc209c
#define CSDM_REG_AGG_INT_EVENT_26 0xc20a0
#define CSDM_REG_AGG_INT_EVENT_27 0xc20a4
#define CSDM_REG_AGG_INT_EVENT_28 0xc20a8
#define CSDM_REG_AGG_INT_EVENT_29 0xc20ac
#define CSDM_REG_AGG_INT_EVENT_3 0xc2044 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
#define CSDM_REG_AGG_INT_EVENT_30 0xc20b0
#define CSDM_REG_AGG_INT_EVENT_31 0xc20b4
#define CSDM_REG_AGG_INT_EVENT_4 0xc2048 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
/* [RW 1] The T bit for aggregated interrupt 0 */ #define CSDM_REG_AGG_INT_EVENT_5 0xc204c
#define CSDM_REG_AGG_INT_T_0 0xc20b8 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050
#define CSDM_REG_AGG_INT_T_1 0xc20bc #define CSDM_REG_AGG_INT_EVENT_7 0xc2054
#define CSDM_REG_AGG_INT_T_10 0xc20e0 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058
#define CSDM_REG_AGG_INT_T_11 0xc20e4 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c
#define CSDM_REG_AGG_INT_T_12 0xc20e8 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
#define CSDM_REG_AGG_INT_T_13 0xc20ec or auto-mask-mode (1) */
#define CSDM_REG_AGG_INT_T_14 0xc20f0 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0
#define CSDM_REG_AGG_INT_T_15 0xc20f4 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4
#define CSDM_REG_AGG_INT_T_16 0xc20f8 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8
#define CSDM_REG_AGG_INT_T_17 0xc20fc #define CSDM_REG_AGG_INT_MODE_13 0xc21ec
#define CSDM_REG_AGG_INT_T_18 0xc2100 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0
#define CSDM_REG_AGG_INT_T_19 0xc2104 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4
#define CSDM_REG_AGG_INT_MODE_16 0xc21f8
#define CSDM_REG_AGG_INT_MODE_6 0xc21d0
#define CSDM_REG_AGG_INT_MODE_7 0xc21d4
#define CSDM_REG_AGG_INT_MODE_8 0xc21d8
#define CSDM_REG_AGG_INT_MODE_9 0xc21dc
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
/* [RW 16] The maximum value of the competion counter #0 */ /* [RW 16] The maximum value of the competion counter #0 */
@ -1421,6 +1410,8 @@
/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
only. */ only. */
#define MISC_REG_E1HMF_MODE 0xa5f8 #define MISC_REG_E1HMF_MODE 0xa5f8
/* [RW 32] Debug only: spare RW register reset by core reset */
#define MISC_REG_GENERIC_CR_0 0xa460
/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
these bits is written as a '1'; the corresponding SPIO bit will turn off these bits is written as a '1'; the corresponding SPIO bit will turn off
it's drivers and become an input. This is the reset state of all GPIO it's drivers and become an input. This is the reset state of all GPIO
@ -1729,6 +1720,7 @@
/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1- /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
tsdm enable; b2- usdm enable */ tsdm enable; b2- usdm enable */
#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
/* [RW 1] SAFC enable for port0. This register may get 1 only when /* [RW 1] SAFC enable for port0. This register may get 1 only when
~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
port */ port */
@ -2079,6 +2071,7 @@
#define PXP2_REG_PGL_ADDR_94_F0 0x120540 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
#define PXP2_REG_PGL_CONTROL0 0x120490 #define PXP2_REG_PGL_CONTROL0 0x120490
#define PXP2_REG_PGL_CONTROL1 0x120514 #define PXP2_REG_PGL_CONTROL1 0x120514
#define PXP2_REG_PGL_DEBUG 0x120520
/* [RW 32] third dword data of expansion rom request. this register is /* [RW 32] third dword data of expansion rom request. this register is
special. reading from it provides a vector outstanding read requests. if special. reading from it provides a vector outstanding read requests. if
a bit is zero it means that a read request on the corresponding tag did a bit is zero it means that a read request on the corresponding tag did
@ -2238,6 +2231,9 @@
/* [RW 8] The maximum number of blocks in Tetris Buffer that can be /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
allocated for vq22 */ allocated for vq22 */
#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
allocated for vq25 */
#define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
/* [RW 8] The maximum number of blocks in Tetris Buffer that can be /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
allocated for vq6 */ allocated for vq6 */
#define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
@ -3835,6 +3831,7 @@
#define TM_REG_LIN0_PHY_ADDR 0x164270 #define TM_REG_LIN0_PHY_ADDR 0x164270
/* [RW 1] Linear0 physical address valid. */ /* [RW 1] Linear0 physical address valid. */
#define TM_REG_LIN0_PHY_ADDR_VALID 0x164248 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
#define TM_REG_LIN0_SCAN_ON 0x1640d0
/* [RW 24] Linear0 array scan timeout. */ /* [RW 24] Linear0 array scan timeout. */
#define TM_REG_LIN0_SCAN_TIME 0x16403c #define TM_REG_LIN0_SCAN_TIME 0x16403c
/* [RW 32] Linear1 logic address. */ /* [RW 32] Linear1 logic address. */
@ -4363,6 +4360,7 @@
#define USDM_REG_AGG_INT_EVENT_31 0xc40b4 #define USDM_REG_AGG_INT_EVENT_31 0xc40b4
#define USDM_REG_AGG_INT_EVENT_4 0xc4048 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
#define USDM_REG_AGG_INT_EVENT_5 0xc404c #define USDM_REG_AGG_INT_EVENT_5 0xc404c
#define USDM_REG_AGG_INT_EVENT_6 0xc4050
/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
or auto-mask-mode (1) */ or auto-mask-mode (1) */
#define USDM_REG_AGG_INT_MODE_0 0xc41b8 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
@ -4379,6 +4377,10 @@
#define USDM_REG_AGG_INT_MODE_19 0xc4204 #define USDM_REG_AGG_INT_MODE_19 0xc4204
#define USDM_REG_AGG_INT_MODE_4 0xc41c8 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
#define USDM_REG_AGG_INT_MODE_5 0xc41cc #define USDM_REG_AGG_INT_MODE_5 0xc41cc
#define USDM_REG_AGG_INT_MODE_6 0xc41d0
/* [RW 1] The T bit for aggregated interrupt 5 */
#define USDM_REG_AGG_INT_T_5 0xc40cc
#define USDM_REG_AGG_INT_T_6 0xc40d0
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define USDM_REG_CFC_RSP_START_ADDR 0xc4008 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
/* [RW 16] The maximum value of the competion counter #0 */ /* [RW 16] The maximum value of the competion counter #0 */

2
firmware/Makefile
View file

@ -32,7 +32,7 @@ fw-shipped-$(CONFIG_ADAPTEC_STARFIRE) += adaptec/starfire_rx.bin \
adaptec/starfire_tx.bin adaptec/starfire_tx.bin
fw-shipped-$(CONFIG_ATARI_DSP56K) += dsp56k/bootstrap.bin fw-shipped-$(CONFIG_ATARI_DSP56K) += dsp56k/bootstrap.bin
fw-shipped-$(CONFIG_ATM_AMBASSADOR) += atmsar11.fw fw-shipped-$(CONFIG_ATM_AMBASSADOR) += atmsar11.fw
fw-shipped-$(CONFIG_BNX2X) += bnx2x-e1-4.8.53.0.fw bnx2x-e1h-4.8.53.0.fw fw-shipped-$(CONFIG_BNX2X) += bnx2x-e1-5.0.21.0.fw bnx2x-e1h-5.0.21.0.fw
fw-shipped-$(CONFIG_BNX2) += bnx2/bnx2-mips-09-4.6.17.fw \ fw-shipped-$(CONFIG_BNX2) += bnx2/bnx2-mips-09-4.6.17.fw \
bnx2/bnx2-rv2p-09-4.6.15.fw \ bnx2/bnx2-rv2p-09-4.6.15.fw \
bnx2/bnx2-mips-06-4.6.16.fw \ bnx2/bnx2-mips-06-4.6.16.fw \